Patent application number | Description | Published |
20130029432 | THIN-WAFER CURRENT SENSORS - Embodiments relate to IC current sensors fabricated using thin-wafer manufacturing technologies. Such technologies can include processing in which dicing before grinding (DBG) is utilized, which can improve reliability and minimize stress effects. While embodiments utilize face-up mounting, face-down mounting is made possible in other embodiments by via through-contacts. IC current sensor embodiments can present many advantages while minimizing drawbacks often associated with conventional IC current sensors. | 01-31-2013 |
20130033934 | Memory Cell Arrangement, Method for Controlling a Memory Cell, Memory Array and Electronic Device - In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well. | 02-07-2013 |
20130037932 | Flange for Semiconductor Die - A semiconductor package includes a curved body and a plurality of semiconductor die. The curved body includes first and second opposing end regions and an intermediate center region. The curved body has a first inflection point at the center region, a second inflection point at the first end region and a third inflection point at the second end region. The center region has a convex curvature with a minimal extremum at the first inflection point, the first end region has a concave curvature with a maximal extremum at the second inflection point and the second end region has a concave curvature with a maximal extremum at the third inflection point. The plurality of semiconductor die are attached to an upper surface of the curved body between the maximal extrema. | 02-14-2013 |
20130037954 | Metallization and Its Use In, In Particular, an IGBT or a Diode - A vertical power semiconductor component includes a semiconductor chip and at least one layer serving as a heat sink. The semiconductor chip has a top main surface at a front side of the semiconductor chip, wherein the top main surface is in a heat exchanging relationship with the at least one layer serving as the heat sink. This layer has a layer thickness of at least 15 μm and has a specific heat capacity per volume that is at least a factor of 1.3 higher than the specific heat capacity per volume of the semiconductor chip. The component further includes metallizations between the at least one layer and the top main surface. | 02-14-2013 |
20130043562 | Compressive Polycrystalline Silicon Film and Method of Manufacture Thereof - In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C. | 02-21-2013 |
20130059424 | Buried Gate Transistor - An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess. | 03-07-2013 |
20130069065 | SILICON CARBIDE MOSFET WITH HIGH MOBILITY CHANNEL - A semiconductor device may include a semiconductor body of silicon carbide (SiC) and a field effect transistor. The field effect transistor has the semiconductor body that includes a drift region. A polycrystalline silicon layer is formed over or on the semiconductor body, wherein the polycrystalline silicon layer has an average particle size in the range of 10 nm to 5 μm, and includes a source region and a body region. Furthermore, the field effect transistor includes a layer adjacent to the body region gate structure. | 03-21-2013 |
20130075478 | COVER STRUCTURE WITH INTEGRATED CHIP AND ANTENNA - In various embodiments, a cover structure for a personal identification document is provided. The cover structure may include a cover formed as a single layer; a chip module; the cover having a recess for completely receiving the chip module; and an antenna that is connected to the chip module. | 03-28-2013 |
20130075861 | Semiconductor structure including guard ring - One or more embodiments relate to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer guard ring and the conductive feature, the inner guard ring being electrically coupled to the conductive feature. | 03-28-2013 |
20130075932 | Power Semiconductor Module with Integrated Thick-Film Printed Circuit Board - A power semiconductor module includes a first printed circuit board having a first insulation carrier, and a first upper metallization and a first lower metallization applied to the first insulation carrier on mutually opposite sides, and a second printed circuit board having a second insulation carrier and a second upper metallization applied to the second insulation carrier. The second printed circuit board is spaced apart from the first printed circuit board in a vertical direction oriented perpendicular to the opposite sides of the first insulation carrier. A semiconductor chip is disposed between the printed circuit boards and electrically conductively connected at least to the second upper metallization. The first lower metallization and the second upper metallization face one another. The first printed circuit board has a first thick conductor layer at least partly embedded in the first insulation carrier and which has a thickness of at least 100 μm. | 03-28-2013 |
20130076250 | LED Driver With Compensation of Thermally Induced Color Drift - A circuit arrangement includes a number of light emitting diodes emitting light of different colors arranged adjacent to each other for additive color mixing to provide a desired color. A temperature sensing circuit is configured to provide a temperature signal representing temperature(s) of the light emitting diodes. Current sources are configured to provide the light emitting diodes with respective load currents in accordance with corresponding control signals received by the current sources. First and second modulator units are configured to generate the control signals which are modulated such that a time average value of each control signal corresponds to the value of a corresponding input signal of the respective sigma-delta modulator. A calibration circuit is configured to provide the input signals dependent on a color signal defining the desired color and dependent on the temperature signal. | 03-28-2013 |
20130077197 | ESD CLAMP ADJUSTMENT - Embodiments of this disclosure relate to electrostatic discharge (ESD) protection techniques. For example, some embodiments include a variable resistor that selectively shunts power of an incoming ESD pulse from a first circuit node to a second circuit node and away from a semiconductor device. A control voltage provided to the variable resistor causes the transistor to change between a fully-off mode where only sub-threshold current, if any, flows; a fully-on mode wherein a maximum amount of current flows; and an analog mode wherein an intermediate and time-varying amount of current flows. In particular, the analog mode allows the ESD protection device to shunt power more precisely than previously achievable, such that the ESD protection device can protect semiconductor devices from ESD pulses. | 03-28-2013 |
20130082112 | Smart Card Module for a Smart Card - The present invention describes a smart card module for a smart card, comprising a first laminate layer, a chip having electric contacts, a first conductive layer, wherein the electrical contacts of the chip are connected to the conductive layer and the first conductive layer is arranged between the chip and the first laminate layer, and wherein the smart card module furthermore comprises an adhesive means, wherein the adhesive means is arranged between the chip and the first conductive layer and/or the first laminate layer. | 04-04-2013 |
20130082340 | APPARATUS HAVING A BACK-BIAS MAGNET AND A SEMICONDUCTOR CHIP ELEMENT - An apparatus may include a back-bias magnet; and a semiconductor chip element; wherein the semiconductor chip element has a sensor for measuring a magnetic field strength; and wherein a contact surface is formed on a contact side of the back-bias magnet and on a contact side of the semiconductor chip element and wherein the contact side of the semiconductor chip element has one or more structures such that the contact surface of the back-bias magnet is shaped in a manner corresponding to the structures of the semiconductor chip element. | 04-04-2013 |
20130082350 | SILICON-ON-INSULATOR CHIP HAVING MULTIPLE CRYSTAL ORIENTATIONS - A silicon-on-insulator device having multiple crystal orientations is disclosed. In one embodiment, the silicon-on-insulator device includes a substrate layer, an insulating layer disposed on the substrate layer, a first silicon layer, and a strained silicon layer. The first silicon layer has a first crystal orientation and is disposed on a portion of the insulating layer, and the strained silicon layer is disposed on another portion of the insulating layer and has a crystal orientation different from the first crystal orientation. | 04-04-2013 |
20130082386 | INTEGRATED CIRCUIT PACKAGE AND A METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT PACKAGE - An integrated circuit package includes a package module including one or more circuit interconnections formed in a carrier, wherein at least one top-side package contact is formed over the top-side of the package module and electrically connected to at least one circuit interconnection of the one or more circuit interconnections and wherein a cavity is formed at the top-side of the package module; a chip disposed in the cavity, the chip including at least one chip front side contact and at least one chip back side contact, wherein the at least one chip front side contact is electrically connected to at least one further circuit interconnection of the one or more circuit interconnections; an electrically conductive structure connecting the at least one top-side package contact to the chip back side contact; and a metallic layer formed over the electrically conductive structure and on the chip back side contact. | 04-04-2013 |
20130082392 | DEVICE WITH CONTACT ELEMENTS - A device with contact elements. One embodiment provides an electrical device including a structure defining a main face. The structure includes an array of cavities and an array of overhang regions, each overhang region defining an opening to one of the cavities. The electrical device further includes an array of contact elements, each contact element only partially filling one of the cavities and protruding from the structure over the main face. | 04-04-2013 |
20130082675 | Digital Switching Converter Control - A control circuit can control the operation of a switching converter to provide a regulated load current to a load. The switching converter includes an inductor and a high-side and a low side-transistor for switching the load current provided via the inductor. A digital modulator is configured to provide a modulated signal having a duty cycle determined by a digital duty cycle value. A current sense circuit is coupled to at least one of the transistors and is configured to regularly sample a load current value. A comparator is coupled to the current sense circuit and is configured to compare the sampled load current value with a first threshold and to provide a respective comparator output signal. A regulator is configured to receive the comparator output signal and to calculate an updated digital duty cycle value. | 04-04-2013 |
20130087921 | Semiconductor Arrangement for Galvanically Isolated Signal Transmission and Method for Producing Such an Arrangement - A semiconductor arrangement includes an artificial chip having a semiconductor chip and an electrically insulating molding compound. The semiconductor chip has circuit structures and is embedded into the molding compound at all sides other than at a base area of the semiconductor chip in such a way that a base area of the artificial chip is enlarged by the molding compound relative to the base area of the semiconductor chip. A thin-film substrate is applied to the enlarged base area and extends beyond the base area of the semiconductor chip into the enlarged base area. The substrate has at least two layers composed of nonconductive material between which a structured metallization is disposed. A first coil is formed by one or a plurality of structured metallization layers in the substrate. A second coil is magnetically and/or capacitively coupled to the first coil and galvanically isolated from the first coil. | 04-11-2013 |
20130094559 | Interface Circuit and Method for Enabling an Output Driver of the Interface Circuit - An interface circuit includes an interface terminal, a voltage detection device, an output driver and an enable logic. The interface terminal is configured to connect to an interface line. The voltage detection device is configured to detect a voltage present at the interface terminal. The output driver is configured to apply an output signal to the interface terminal. The enable logic is configured to generate an enable signal for the output driver based on an evaluation signal output by the voltage detection device, wherein the enable signal affects an enabling of the output driver if the evaluation signal shows that the voltage present at the interface terminal meets a given condition. | 04-18-2013 |
20130094648 | Apparatus and Method for Producing a Bit Sequence - A method for reconstructing a physically unclonable function (PUF) A for use in an electronic appliance is provided. The method includes producing a checksum C, producing a defective PUF B and reconstructing the PUF A from the defective PUF B using an error correction algorithm. The algorithm produces a plurality of ambiguous results (A | 04-18-2013 |
20130095609 | Device and Method for Manufacturing a Device - A device includes a first semiconductor chip and a first encapsulant that encapsulates the first semiconductor chip and that includes a cavity. A carrier and an electrical component are mounted on the carrier. The carrier is arranged such that the electrical component is enclosed by the cavity. | 04-18-2013 |
20130099289 | Compact Memory Arrays - Embodiments of the invention describe compact memory arrays. In one embodiment, the memory cell array includes first, second, and third gate lines disposed over a substrate, the second gate lines are disposed between the first and the third gate lines. The first, the second, and the third gate lines form adjacent gate lines of the memory cell array. The memory cell array further includes first metal lines disposed over the first gate lines, the first metal lines coupled to the first gate lines; second metal lines disposed over the second gate lines, the second metal lines coupled to the second gate lines; and third metal lines disposed over the third gate lines, the third metal lines coupled to the third gate lines. The first metal lines, the second metal lines and the third metal lines are disposed in different metallization levels. | 04-25-2013 |
20130101075 | METHOD AND APPARATUS FOR REGULATING THE SAMPLING PHASE - Embodiments of the invention relate to methods and circuits for controlling the sampling phase of a signal that is to be regenerated by sampling, particularly a serial communication signal, having method steps or means for oversampling the signal in order to ascertain samples of the signal during predetermined sampling phases, for determining differential errors between the samples during different instances of the predetermined sampling phases, for determining a differential error rate between the samples to at least one first and at least one second sampling phase on the basis of the ascertained differential errors, and for comparing at least two differential error rates based on at least two different sampling phase pairs in order to ascertain a decision concerning which of the predetermined sampling phases can be selected as a reference sampling phase for correctly regenerating the signal. | 04-25-2013 |
20130114309 | Battery Module - A battery module and an arrangement including a number of battery modules connected in series are disclosed. An energy store has a positive and a negative connection. A boost converter has a first and a second converter output. The energy store is connected at the positive connection of the energy store to a first connection and at the negative connection of the energy store to a second connection. The first converter output is connected to a first compensation connection and the second converter output is connected to a second compensation connection. The converter is designed to draw energy from the energy store and to provide the energy to the converter outputs of the converter in the form of current. | 05-09-2013 |
20130119403 | Semiconductor Structure and a Method of Forming the Same - Some embodiments show a semiconductor structure including a substrate with a {100} crystal surface plane which includes a plurality of adjacent structured regions at a top side of the substrate. The plurality of adjacent structured regions includes adjacent substrate surfaces with {111} crystal planes and a III-V semiconductor material layer above the top side of the substrate. A semiconductor device region includes at least one semiconductor device structure. The semiconductor device region is arranged above the plurality of adjacent structured regions at the top side of the substrate. | 05-16-2013 |
20130119517 | Plasma Dicing and Semiconductor Devices Formed Thereof - In one embodiment, a method of forming a semiconductor device includes forming islands by forming deep trenches within scribe lines of a substrate. The islands have a first notch disposed on sidewalls of the islands. A first electrode stack is formed over a top surface of the islands. The back surface of the substrate is thinned to separate the islands. A second electrode stack is formed over a back surface of the islands. | 05-16-2013 |
20130119522 | Semiconductor Device and Substrate with Chalcogen Doped Region - A semiconductor substrate includes a first side and a second side opposite the first side. A semiconductor material extends between the first and second sides and is devoid of active device regions. The semiconductor material has a first region and a second region. The first region extends from the first side to a depth into the semiconductor material and includes chalcogen dopant atoms which provide a base doping concentration for the first region. The second region extends from the first region to the second side and is devoid of base doping. Further, a power semiconductor component is provided. | 05-16-2013 |
20130122660 | SENSOR DEVICE AND METHOD - A sensor device and method. One embodiment provides a first semiconductor chip having a sensing region. A porous structure element is attached to the first semiconductor chip. A first region of the porous structure element faces the sensing region of the first semiconductor chip. An encapsulation material partially encapsulates the first semiconductor chip and the porous structure element. | 05-16-2013 |
20130127066 | Integrated Circuit Including Interconnect Levels - An integrated circuit as described herein includes an upper interconnect level including a continuous upper interconnect area, the continuous upper interconnect area including a plurality of upper contact openings. The integrated circuit further includes a lower interconnect level including a continuous lower interconnect area, the continuous lower interconnect area including a plurality of lower contact openings. First contacts extend through the lower contact openings to the upper interconnect area and second contact openings extend through the upper contact openings to the lower interconnect area. | 05-23-2013 |
20130130470 | NONVOLATILE MEMORY ELEMENT AND PRODUCTION METHOD THEREOF AND STORAGE MEMORY ARRANGEMENT - A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form. | 05-23-2013 |
20130134420 | Stress-Inducing Structures, Methods, and Materials - Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material. | 05-30-2013 |
20130134539 | Photodiode Comprising Polarizer - A photodiode includes a photosensitive area and a polarizing grating located in front of the photosensitive area. The polarizing grating is formed by a plurality of galvanically conducting filaments. | 05-30-2013 |
20130134572 | SEMICONDUCTOR DEVICE INCLUDING CLADDED BASE PLATE - A semiconductor device includes a semiconductor chip joined with a substrate and a base plate joined with the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure. The second metal layer has a sub-layer that has no pins and no pin-fins. The first metal layer has a first thickness and the sub-layer has a second thickness. The ratio between the first thickness and the second thickness is at least 4:1. | 05-30-2013 |
20130135085 | TRANSPONDER UNIT, SYSTEM AND METHOD FOR CONTACTLESS DATA TRANSMISSION - In various embodiments, a transponder unit for the contactless transmission of modulated data to a reader is provided. The transponder unit may include: a clock generator configured to generate a clock signal and to synchronize the clock signal in a synchronization mode, on the basis of a signal received from the reader; and a modulator configured to take the clock signal from the clock generator as a basis for modulating data; wherein the modulator is configured to send a signal for starting the synchronization mode to the clock generator. | 05-30-2013 |
20130140626 | Field-Effect Device and Manufacturing Method Thereof - Embodiments relate to a field-effect device that includes a body region, a first source/drain region of a first conductivity type, a second source/drain region, and a pocket implant region adjacent to the first source/drain region, the pocket implant region being of a second conductivity type, wherein the second conductivity type is different from the first conductivity type. The body region physically contacts the pocket implant region. | 06-06-2013 |
20130140632 | Lateral Transistor Component and Method for Producing Same - A transistor component includes an active transistor region arranged in the semiconductor body. And insulation region surrounds the active transistor region in the semiconductor body in a ring-shaped manner. A source zone, a drain zone, a body zone and a drift zone are disposed in the active transistor region. The source zone and the drain zone are spaced apart in a lateral direction of the semiconductor body and the body zone is arranged between the source zone and the drift zone and the drift zone is arranged between the body zone and the drain zone. A gate and field electrode is arranged over the active transistor region. The dielectric layer has a first thickness in in a region near the body zone and a second thickness in a region near the drift zone. | 06-06-2013 |
20130141158 | LDO WITH DISTRIBUTED OUTPUT DEVICE - A method and apparatus for supplying independently switched, regulated power to a plurality of loads is disclosed. | 06-06-2013 |
20130141987 | Latch Based Memory Device - A method of testing a latch based memory device is disclosed. The latch based memory device includes a number of latches, electrical connections and a circuit environment of the latches. A storage functionality of the latches can be tested during a first test phase while a functionality of the electrical connections and the circuit environment of the latches can be tested during a second test phase. | 06-06-2013 |
20130143368 | SEMICONDUCTOR DEVICE - A module including a carrier and a semiconductor chip applied to the carrier. An external contact element is provided having a first portion and a second portion extending perpendicular to the first portion, wherein a thickness of the second portion is smaller than a thickness of the carrier. | 06-06-2013 |
20130146670 | CHIP CARD CONTACT ARRAY ARRANGEMENT - In various embodiments, a chip card contact array arrangement is provided, having a carrier, a plurality of contact arrays which are arranged on a first side of the carrier, an electrically conductive structure which is arranged on a second side of the carrier, which is arranged opposite the first side of the carrier, a first plated-through hole and a second plated-through hole, wherein the first plated-through hole is coupled to the electrically conductive structure, a connecting structure which is arranged on the first side of the carrier, wherein the connecting structure connects the first plated-through hole to the second plated-through hole, the connecting structure having a longitudinal extent which runs parallel to a direction in which a contact-connection device on a reading device is moved relative to the plurality of contacts. | 06-13-2013 |
20130146671 | BOOSTER ANTENNA STRUCTURE FOR A CHIP CARD - In various embodiments, a booster antenna structure for a chip card is provided, wherein the booster antenna structure may include a booster antenna; and an additional electrically conductive structure connected to the booster antenna. | 06-13-2013 |
20130146971 | Semiconductor Device Including First and Second Semiconductor Elements - A semiconductor device includes a first semiconductor element including a first pn junction between a first terminal and a second terminal. The semiconductor device further includes a semiconductor element including a second pn junction between a third terminal and a fourth terminal. The semiconductor element further includes a semiconductor body including the first semiconductor element and the second semiconductor element monolithically integrated. The first and third terminals are electrically coupled to a first device terminal. The second and fourth terminals are electrically coupled to a second device terminal. A temperature coefficient α | 06-13-2013 |
20130164939 | METHOD, APPARATUS FOR HOLDING AND TREATMENT OF A SUBSTRATE - Some embodiments discussed relates to an apparatus for holding a substrate, comprising a body with a surface for a semiconductor wafer to rest on, with the surface having a first surface area on which a first area of the semiconductor wafer can rest, and a second surface area on which a second area of the semiconductor wafer can rest, wherein the second surface area protrudes with respect to the first surface area. | 06-27-2013 |
20130167097 | Asymmetric Segmented Channel Transistors - Structures, layouts and methods of forming integrated circuits are described. In various embodiments, the current invention includes an asymmetric segmented transistor. The asymmetric segmented transistor includes a source region and a drain region disposed within an active region, a floating source/drain region disposed within the active region, a first channel region disposed in the active region between the source region and the floating source/drain region, the first channel having a first length and a first width. A second channel region is disposed in the active region between the drain region and the floating source/drain region, the second channel having a second length and a second width. A first gate dielectric overlies the first channel region and a second gate dielectric overlies the second channel region. A gate line overlies the first gate dielectric and the second gate dielectric. | 06-27-2013 |
20130171931 | Communication Method Between Electronic Appliances, and Corresponding Appliances - A communication method for the communication between two appliances which are set up for communication in a first communication mode is provided. The method includes sending an activation sequence in a second communication mode from the first to the second appliance in order to initiate communication based on the first communication mode; sending data from the second appliance to the first appliance based on the first communication mode. The activation sequence sent to the second appliance includes an initialization sequence and a request for data communication in the first communication mode. In addition, a corresponding electronic appliance and system are provided. | 07-04-2013 |
20130176053 | INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING THE SAME - An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates. | 07-11-2013 |
20130181256 | SEMICONDUCTOR DEVICES - In an embodiment, a semiconductor device is provided. The semiconductor device may include a substrate having a main processing surface, a first source/drain region comprising a first material of a first conductivity type, a second source/drain region comprising a second material of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, a body region electrically coupled between the first source/drain region and the second source/drain region, wherein the body region extends deeper into the substrate than the first source/drain region in a first direction that is perpendicular to the main processing surface of the substrate, a gate dielectric disposed over the body region, and a gate region disposed over the gate dielectric, wherein the gate region overlaps with at least a part of the first source/drain region and with a part of the body region in the first direction. | 07-18-2013 |
20130181703 | Sensor Package and Method for Producing a Sensor Package - Some embodiments herein relate to a sensor package. The sensor package includes a printed circuit board with a laminar current conductor arranged on a first main surface of the printed circuit board. The sensor package also includes a sensor chip adapted to measure a current flowing through the laminar current conductor, wherein the sensor chip comprises a magnetic field sensor. The sensor chip is electrically insulated from the current conductor by the printed circuit board, and is arranged on a second main surface of the printed circuit board opposite to the first main surface. The sensor chip is hermetically sealed between the mold material and the printed circuit board, or is arranged in the printed circuit board and hermetically sealed by the printed circuit board. | 07-18-2013 |
20130187211 | Multi-Layer Integrated Circuit Package - A multi-layer integrated circuit package includes a switched-mode power supply circuit including a plurality of transistors which form part of a main current loop of the switched-mode power supply circuit. The plurality of transistors are arranged in one or more layers of the integrated circuit package. The package further includes a conductive plate arranged in a different layer of the integrated circuit package than the plurality of transistors. The conductive plate is in close enough proximity to at least part of the main current loop so that a current can be electromagnetically induced in the conductive plate responsive to a change in current in the main current loop. | 07-25-2013 |
20130193510 | SEMICONDUCTOR DEVICE HAVING A TRENCH GATE AND METHOD FOR MANUFACTURING - A semiconductor device having a trench gate and method for manufacturing is disclosed. One embodiment includes a first semiconductor area and a second semiconductor area, a semiconductor body area between the first semiconductor area and the second semiconductor area, and a gate arranged in a trench and separated from the semiconductor body by an insulation layer, wherein the trench has a top trench portion which extends from the semiconductor surface at least to a depth which is greater than a depth of the first semiconductor area, wherein the trench further has a bottom trench portion extending subsequent to the top trench portion at least up to the second semiconductor area, and wherein the top trench portion has a first lateral dimension and the bottom trench portion has a second lateral dimension which is greater than the first lateral dimension. | 08-01-2013 |
20130193591 | Power Semiconductor Module with Pressed Baseplate and Method for Producing a Power Semiconductor Module with Pressed Baseplate - A power semiconductor module includes a baseplate having a top side, an underside, and a depression formed in the baseplate. The depression extends into the baseplate proceeding from the top side. A thickness of the baseplate is locally reduced in a region of the depression. The power semiconductor module further includes a circuit carrier arranged above the depression on the top side of the baseplate such that the depression is interposed between the circuit carrier and the underside of the baseplate. | 08-01-2013 |
20130195266 | Apparatus and Method for Producing a Message Authentication Code - An apparatus for producing a message authentication code based on a first message and an original key is provided. The apparatus includes a key generator configured to produce a generated key based on the original key and the first message. Furthermore, the apparatus includes a message authentication code generator configured to produce the message authentication code based on the generated key and the first message. | 08-01-2013 |
20130200909 | SENSOR SELF-DIAGNOSTICS USING MULTIPLE SIGNAL PATHS - Embodiments relate to systems and methods for self-diagnostics and/or error detection using multiple signal paths in sensor and other systems. In an embodiment, a sensor system comprises at least two sensors, such as magnetic field sensors, and separate signal paths associated with each of the sensors. A first signal path can be coupled to a first sensor and a first digital signal processor (DSP), and a second signal path can be coupled to a second sensor and a second DSP. A signal from the first DSP can be compared with a signal from the second DSP, either on-chip or off, to detect faults, errors, or other information related to the operation of the sensor system. Embodiments of these systems and/or methods can be configured to meet or exceed relevant safety or other industry standards, such as safety integrity level (SIL) standards. | 08-08-2013 |
20130200939 | SEMICONDUCTOR DEVICE ARRANGEMENT AND METHOD - A semiconductor device arrangement and a method. One embodiment includes at least one power transistor and at least one gate resistor located between a gate of the power transistor and a connecting point in the drive circuit of the power transistor. The semiconductor device arrangement includes a switchable element between the connecting point and a source of the power transistor. | 08-08-2013 |