| Patent application number | Description | Published |
|---|
| 20080229128 | System and Computer Program Product for Dynamically Managing Power in MicroProcessor Chips According to Present Processing Demands - A method, system, and computer program product are disclosed for dynamically managing power in a microprocessor chip that includes physical hardware elements within the microprocessor chip. A process is selected to be executed. Hardware elements that are necessary to execute the process are then identified. The power in the microprocessor chip is dynamically altered by altering a present power state of the hardware elements that were identified as being necessary. | 09-18-2008 |
| 20090224388 | SEMICONDUCTOR CHIP STACKING FOR REDUNDANCY AND YIELD IMPROVEMENT - A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of the first chip component within at least another unit chip so that the combination of the multiple instances of the first chip component across the multiple unit chips constitute a functional block providing the functionality of a fully functional instance of the first chip component. The stacked semiconductor chip may include multiple instances of a second chip component having a high yield and distributed across the multiple unit chips. Multiple low yield components constitute a functional block providing an enhanced overall yield, while high yield components are utilized to their full potential functionality. | 09-10-2009 |
| 20110271079 | MULTIPLE-CORE PROCESSOR SUPPORTING MULTIPLE INSTRUCTION SET ARCHITECTURES - A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. The multiple cores may share a common first level cache and be mutually-exclusively selected for operation, or multiple level-one caches may be provided, one associated with each of the cores and the cores operated as needed, including simultaneous execution of disparate ISAs. A hypervisor controls operation of the cores and locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received. | 11-03-2011 |
| 20120326333 | SEMICONDUCTOR CHIP STACKING FOR REDUNDANCY AND YIELD IMPROVEMENT - A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of the first chip component within at least another unit chip so that the combination of the multiple instances of the first chip component across the multiple unit chips constitute a functional block providing the functionality of a fully functional instance of the first chip component. The stacked semiconductor chip may include multiple instances of a second chip component having a high yield and distributed across the multiple unit chips. Multiple low yield components constitute a functional block providing an enhanced overall yield, while high yield components are utilized to their full potential functionality. | 12-27-2012 |
| Patent application number | Description | Published |
|---|
| 20120317356 | SYSTEMS AND METHODS FOR SHARING MEMORY BETWEEN A PLURALITY OF PROCESSORS - Systems and methods for sharing memory between a plurality of processors are provided. In one example, a shared memory system is disclosed. The system includes at least two processors and at least two memory devices, such as passive variable resistive memory (PVRM) devices. Each memory device is operatively connected to each processor via one of a plurality of processor interfaces. Each processor interface is dedicated to a single processor of the at least two processors. In this manner, any individual processor of the at least two processors is operative to access data stored in any individual memory device of the at least two memory devices via the processor interface dedicated to that respective individual processor. | 12-13-2012 |
| 20130070515 | METHOD AND APPARATUS FOR CONTROLLING STATE INFORMATION RETENTION IN AN APPARATUS - A method and apparatus for controlling state information retention determines at least a state information save or restore condition for at least one processing circuit such as one or more CPU or GPU cores or pipelines, in an integrated circuit. In response to determining the state information save or restore condition, the method and apparatus controls either or both of saving or restoring of state information for different virtual machines operating on the processing circuit, into corresponding on-die persistent passive variable resistance memory. The state information save or restore condition is a virtual machine level state information save or restore condition. State information for each of differing virtual machines is saved or restored from differing on-die passive variable resistance memory cells that are assigned on a per-virtual machine basis. | 03-21-2013 |
| 20130159812 | MEMORY ARCHITECTURE FOR READ-MODIFY-WRITE OPERATIONS - According to one embodiment, a memory architecture implemented method is provided, where the memory architecture includes a logic chip and one or more memory chips on a single die, and where the method comprises: reading values of data from the one or more memory chips to the logic chip, where the one or more memory chips and the logic chip are on a single die; modifying, via the logic chip on the single die, the values of data; and writing, from the logic chip to the one or more memory chips, the modified values of data. | 06-20-2013 |
| 20140040532 | STACKED MEMORY DEVICE WITH HELPER PROCESSOR - A processing system comprises one or more processor devices and other system components coupled to a stacked memory device having a set of stacked memory layers and a set of one or more logic layers. The set of logic layers implements a helper processor that executes instructions to perform tasks in response to a task request from the processor devices or otherwise on behalf of the other processor devices. The set of logic layers also includes a memory interface coupled to memory cell circuitry implemented in the set of stacked memory layers and coupleable to the processor devices. The memory interface operates to perform memory accesses for the processor devices and for the helper processor. By virtue of the helper processor's tight integration with the stacked memory layers, the helper processor may perform certain memory-intensive operations more efficiently than could be performed by the external processor devices. | 02-06-2014 |
| 20140040698 | STACKED MEMORY DEVICE WITH METADATA MANGEMENT - A processing system comprises one or more processor devices and other system components coupled to a stacked memory device having a set of stacked memory layers and a set of one or more logic layers. The set of logic layers implements a metadata manager that offloads metadata management from the other system components. The set of logic layers also includes a memory interface coupled to memory cell circuitry implemented in the set of stacked memory layers and coupleable to the devices external to the stacked memory device. The memory interface operates to perform memory accesses for the external devices and for the metadata manager. By virtue of the metadata manager's tight integration with the stacked memory layers, the metadata manager may perform certain memory-intensive metadata management operations more efficiently than could be performed by the external devices. | 02-06-2014 |
| 20140176187 | DIE-STACKED MEMORY DEVICE WITH RECONFIGURABLE LOGIC - A die-stacked memory device incorporates a reconfigurable logic device to provide implementation flexibility in performing various data manipulation operations and other memory operations that use data stored in the die-stacked memory device or that result in data that is to be stored in the die-stacked memory device. One or more configuration files representing corresponding logic configurations for the reconfigurable logic device can be stored in a configuration store at the die-stacked memory device, and a configuration controller can program a reconfigurable logic fabric of the reconfigurable logic device using a selected one of the configuration files. Due to the integration of the logic dies and the memory dies, the reconfigurable logic device can perform various data manipulation operations with higher bandwidth and lower latency and power consumption compared to devices external to the die-stacked memory device. | 06-26-2014 |
| 20140181415 | PREFETCHING FUNCTIONALITY ON A LOGIC DIE STACKED WITH MEMORY - Prefetching functionality on a logic die stacked with memory is described herein. A device includes a logic chip stacked with a memory chip. The logic chip includes a control block, an in-stack prefetch request handler and a memory controller. The control block receives memory requests from an external source and determines availability of the requested data in the in-stack prefetch request handler. If the data is available, the control block sends the requested data to the external source. If the data is not available, the control block obtains the requested data via the memory controller. The in-stack prefetch request handler includes a prefetch controller, a prefetcher and a prefetch buffer. The prefetcher monitors the memory requests and based on observed patterns, issues additional prefetch requests to the memory controller. | 06-26-2014 |
| 20140181417 | CACHE COHERENCY USING DIE-STACKED MEMORY DEVICE WITH LOGIC DIE - A die-stacked memory device implements an integrated coherency manager to offload cache coherency protocol operations for the devices of a processing system. The die-stacked memory device includes a set of one or more stacked memory dies and a set of one or more logic dies. The one or more logic dies implement hardware logic providing a memory interface and the coherency manager. The memory interface operates to perform memory accesses in response to memory access requests from the coherency manager and the one or more external devices. The coherency manager comprises logic to perform coherency operations for shared data stored at the stacked memory dies. Due to the integration of the logic dies and the memory dies, the coherency manager can access shared data stored in the memory dies and perform related coherency operations with higher bandwidth and lower latency and power consumption compared to the external devices. | 06-26-2014 |
| 20140181427 | Compound Memory Operations in a Logic Layer of a Stacked Memory - Some die-stacked memories will contain a logic layer in addition to one or more layers of DRAM (or other memory technology). This logic layer may be a discrete logic die or logic on a silicon interposer associated with a stack of memory dies. Additional circuitry/functionality is placed on the logic layer to implement functionality to perform various data movement and address calculation operations. This functionality would allow compound memory operations—a single request communicated to the memory that characterizes the accesses and movement of many data items. This eliminates the performance and power overheads associated with communicating address and control information on a fine-grain, per-data-item basis from a host processor (or other device) to the memory. This approach also provides better visibility of macro-level memory access patterns to the memory system and may enable additional optimizations in scheduling memory accesses. | 06-26-2014 |
| 20140181428 | QUALITY OF SERVICE SUPPORT USING STACKED MEMORY DEVICE WITH LOGIC DIE - A die-stacked memory device implements an integrated QoS manager to provide centralized QoS functionality in furtherance of one or more specified QoS objectives for the sharing of the memory resources by other components of the processing system. The die-stacked memory device includes a set of one or more stacked memory dies and one or more logic dies. The logic dies implement hardware logic for a memory controller and the QoS manager. The memory controller is coupleable to one or more devices external to the set of one or more stacked memory dies and operates to service memory access requests from the one or more external devices. The QoS manager comprises logic to perform operations in furtherance of one or more QoS objectives, which may be specified by a user, by an operating system, hypervisor, job management software, or other application being executed, or specified via hardcoded logic or firmware. | 06-26-2014 |
| 20140181457 | Write Endurance Management Techniques in the Logic Layer of a Stacked Memory - A system, method, and memory device embodying some aspects of the present invention for remapping external memory addresses and internal memory locations in stacked memory are provided. The stacked memory includes one or more memory layers configured to store data. The stacked memory also includes a logic layer connected to the memory layer. The logic layer has an Input/Output (I/O) port configured to receive read and write commands from external devices, a memory map configured to maintain an association between external memory addresses and internal memory locations, and a controller coupled to the I/O port, memory map, and memory layers, configured to store data received from external devices to internal memory locations. | 06-26-2014 |
| 20140181458 | DIE-STACKED MEMORY DEVICE PROVIDING DATA TRANSLATION - A die-stacked memory device incorporates a data translation controller at one or more logic dies of the device to provide data translation services for data to be stored at, or retrieved from, the die-stacked memory device. The data translation operations implemented by the data translation controller can include compression/decompression operations, encryption/decryption operations, format translations, wear-leveling translations, data ordering operations, and the like. Due to the tight integration of the logic dies and the memory dies, the data translation controller can perform data translation operations with higher bandwidth and lower latency and power consumption compared to operations performed by devices external to the die-stacked memory device. | 06-26-2014 |
| 20140181483 | Computation Memory Operations in a Logic Layer of a Stacked Memory - Some die-stacked memories will contain a logic layer in addition to one or more layers of DRAM (or other memory technology). This logic layer may be a discrete logic die or logic on a silicon interposer associated with a stack of memory dies. Additional circuitry/functionality is placed on the logic layer to implement functionality to perform various computation operations. This functionality would be desired where performing the operations locally near the memory devices would allow increased performance and/or power efficiency by avoiding transmission of data across the interface to the host processor. | 06-26-2014 |
| Patent application number | Description | Published |
|---|
| 20120315322 | NANOPARTICLE MEDIATED GENE THERAPY AND THERAPEUTIC PRODUCTS FOR ALZHEIMERS - The present disclosure provides compositions and methods of treating Alzheimers Disease. In an aspect, a nanoparticle is paired to one or more genetic materials that regulates inflammation in a microenvironment. Such nanoparticles can be used to target predefined target cell types in connection with treatment of at least one of the following Alzheimer's disease, Pick's disease, Lewy Body disease, or Idiopathic dementia. | 12-13-2012 |
| 20130330279 | NANOPARTICLE MEDIATED GENE THERAPY, DIAGNOSTIC PRODUCTS AND THERAPEUTIC PRODUCTS FOR BREAST CANCER - The present disclosure provides compositions and methods of treating Breast Cancer. Disclosed is a nanoparticle paired to at least one of W genetic materials that suppress key regulators of fat synthesis (e.g. Rev-erb) to cause a predefined target cell types apoptosis or X predefined targeting moieties that cause predefined target cell types apoptosis and correspond to Y predefined target parameters associated with Z predefined target cell types in connection with treatment of at least one of the following breast cancer, glioblastoma, head and neck cancer, pancreatic cancer, lung cancer, cancer of the nervous system, gastrointestinal cancer, prostate cancer, ovarian cancer, kidney cancer, retina, cancer, skin cancer, liver cancer, genital. | 12-12-2013 |
