Patent application number | Description | Published |
20130264232 | HANGING MULTI-SUIT BAG - The multi-suit bag contains a wardrobe member made of a soft fabric material. The wardrobe member has an elongated opening along a top side, a first top piece forming a first longer edge of the opening, a second top piece forming a second longer edge of the opening, and an elongated cover element attaching to the top edge of the second top piece. A fastener is configured between the first top piece and a first longer edge of the cover element. A number of supporting pieces and one or more top pieces are configured inside the cover element so as to enhance the cover element's strength. By receiving the hanging rod by the opening, flipping the cover element over the hanging rod, and closing the fastener, the multi-suit bag is quickly and conveniently hanged over the hanging rod. | 10-10-2013 |
20130270207 | RACK WITH DETACHABLE BEAM - The rack contains at least a column member and at least a beam. The column member contains a support element with at least a vertical chamber. The chamber has an upper section, an enlarged middle section, and a lower section sequentially in this order. The width of the lower section is smaller than the width of the enlarged middle section, but larger than the width of the upper section. The width of the beam is equal to the width of the lower section and the thickness of the beam is smaller than the width of the upper section. The beam is dropped into the chamber by its smaller thickness, turned for an angle in the enlarged middle section, and rested reliably in the lower section. | 10-17-2013 |
20140217046 | Assemblable Storage Rack - The assemblable storage rack comprises at least one shelf and multiple supporting brackets, wherein the supporting brackets can be fixed to a wall, and the shelf can be placed on top of the supporting brackets. Each supporting bracket is provided with a stopper on a horizontal bar assembly thereof and a step on a vertical bar thereof. The internal distance between the stopper and the vertical bar is greater than the external distance between the second beam and the third beam of the shelf. In use, the stoppers of the supporting brackets can be inserted into the corresponding gaps of the shelf to abut one side of the second beam that is far away from the third beam, whereas the third beam can be placed under the steps of the supporting brackets, so that the shelf can be prevented from detaching the supporting brackets. | 08-07-2014 |
Patent application number | Description | Published |
20090180332 | OPERATION METHOD OF NITRIDE-BASED FLASH MEMORY AND METHOD OF REDUCING COUPLING INTERFERENCE - A method for operating a nitride-based flash memory is provided. The operation method includes pre-performing an interference reduction operation (IRO) before the routine programming operating step. Through bias arrangement of the target memory cell, charges are injected into the charge trapping layer mainly above the junction regions of the memory cell before programming so as to reset the influences caused by coupling interference issues. The operation method of this present invention not only reduces coupling interference but also afford a wider operation window. | 07-16-2009 |
20100112797 | METHOD FOR FORMING A MEMORY ARRAY - The invention is directed to a method for forming a memory array. The method comprises steps of providing a substrate having a charge trapping structure formed thereon. A patterned material layer is formed over the substrate and the patterned material layer having a plurality of trenches expose a portion of the charge trapping structure. Furthermore, a plurality of conductive spacers are formed on the sidewalls of the trenches of the patterned material layer respectively and a portion of the charge trapping structure at the bottom of the trenches is exposed by the conductive spacers. An insulating layer is formed over the substrate to fill up the trenches of the patterned material layer. Moreover, a planarization process is performed to remove a portion of the insulating layer until a top surface of the patterned material layer and a top surface of each of the conductive spacers are exposed. | 05-06-2010 |
20100284220 | OPERATION METHOD OF NON-VOLATILE MEMORY - An operation method of a non-volatile memory for reducing the second-bit effect in the non-volatile memory is suitable for an N-level memory cell having a first storage position and a second storage position (wherein N is a positive integer greater than 2). The method includes following steps: determining sets of operation levels for operating the first storage position according to the level of the second storage position; when the level of the second storage position is a lower level, operating the first storage position according to a first set of operation levels; when the level of the second storage position is a higher level, operating the first storage position according to a second set of operation levels. Each of the levels in the second set of operation levels is greater than the corresponding level in the first set of operation levels. | 11-11-2010 |
20100289093 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device is described, which includes a substrate, a gate structure, doped regions and lightly doped regions. The substrate has a stepped upper surface, which includes a first surface, a second surface and a third surface. The second surface is lower than the first surface. The third surface connects the first surface and the second surface. The gate structure is disposed on the first surface. The doped regions are configured in the substrate at both sides of the gate structure and under the second surface. The lightly doped regions are configured in the substrate between the gate structure and the doped regions, respectively. Each lightly doped region includes a first part and a second part connecting with each other. The first part is disposed under the second surface, and the second part is disposed under the third surface. | 11-18-2010 |
20100302845 | MEMORY DEVICE AND METHODS FOR FABRICATING AND OPERATING THE SAME - The memory device is described, which includes a substrate, a conductive layer, a charge storage layer, a plurality of first doped regions and a plurality of second doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first doped regions are configured in the substrate adjacent to both sides of an upper portion of each trench, respectively. The first doped regions between the neighbouring trenches are separated from each other. The second doped regions are configured in the substrate under bottoms of the trenches, respectively. The second doped regions and the first doped regions are separated from each other, such that each memory cell includes six physical bits. | 12-02-2010 |
20100302855 | MEMORY DEVICE AND METHODS FOR FABRICATING AND OPERATING THE SAME - The memory device is described, which includes a substrate, a conductive layer, a plurality of charge storage layers and a plurality of doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layers are disposed between the substrate and the conductive layer in the trenches respectively, wherein the charge storage layers are separated from each other. The doped regions are configured in the substrate under bottoms of the trenches, respectively. | 12-02-2010 |
20100314680 | MEMORY ARRAY - A memory array includes a charge storage structure and a plurality of conductive materials over the charge storage structure is provided. Each conductive material, serving as a word line, has a substantially arc-sidewall and a substantially straight sidewall. | 12-16-2010 |
20110182123 | FLASH MEMORY AND MANUFACTURING METHOD AND OPERATING METHOD THEREOF - A flash memory and a manufacturing method and an operating method thereof are provided. The flash memory includes a substrate, a charge-trapping structure, a first gate, a second gate, a third gate, a first doped region and a second doped region. The substrate has a protrusion portion. The charge-trapping structure is disposed over the substrate. The first gate and the second gate are disposed respectively over the charge-trapping structure at two sides of the protrusion portion. The top surfaces of the first gate and the second gate are lower than the top surface of the charge-trapping structure located on the top of the protrusion portion. The third gate is disposed over the charge-trapping structure located on the top of the protrusion portion. The first doped region and the second doped region are disposed respectively in the substrate at two sides of the protrusion portion. | 07-28-2011 |
20120056259 | MEMORY CELL, MEMORY DEVICE AND METHOD FOR MANUFACTURING MEMORY CELL - A memory cell including a substrate, a stacked gate structure and a first isolation structure is provided. The substrate has a first doped region, a second doped and a channel region located between the first doped region and the second doped region. The stacked gate structure is disposed on the channel and at least includes a charge trapping layer and a gate from bottom to top. The first isolation structure is disposed in the substrate and is connected to the first doped region and extends downwards from the first doped region for a predetermined length, and a bottom of the first isolation structure is lower than a bottom of the first doped region. | 03-08-2012 |
20120126307 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a substrate, a gate structure, a first doped region, a second doped region and a pair of isolation structures. The gate structure is disposed on the substrate. The gate structure includes a charge storage structure, a gate and spacers. | 05-24-2012 |
20120127795 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF AND OPERATING METHOD OF MEMORY CELL - A non-volatile memory and a manufacturing method thereof and a method for operating a memory cell are provided. The non-volatile memory includes a substrate, first and second doped regions, a charged-trapping structure, first and second gates and an inter-gate insulation layer. The first and second doped regions are disposed in the substrate and extend along a first direction. The first and second doped regions are arranged alternately. The charged-trapping structure is disposed on the substrate. The first and second gates are disposed on the charged-trapping structure. Each first gate is located above one of the first doped regions. The second gates extend along a second direction and are located above the second doped regions. The inter-gate insulation layer is disposed between the first gates and the second gates. Adjacent first and second doped regions and the first gate, the second gate and the charged-trapping structure therebetween define a memory cell. | 05-24-2012 |
20120140556 | METHOD OF OPERATING FLASH MEMORY - A method of operating a flash memory is described. When a first storage site has 2 | 06-07-2012 |
20120261739 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device including a first doped region of a first conductivity type, a second doped region of a second conductivity type, a gate, and a dielectric layer is provided. The first doped region is located in a substrate and has a trench. The second doped region is located at the bottom of the trench to separate the first doped region into a source doped region and a drain doped region. A channel region is located between the source doped region and the drain doped region. The gate is located in the trench. The dielectric layer covers the sidewall and the bottom of the trench and separates the gate and the substrate. | 10-18-2012 |
20140159134 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory including a gate structure disposed on a substrate, doped regions, charge storage layers, and a first dielectric layer. There are recesses in the substrate at two sides of the gate structure. The gate structure includes a gate dielectric layer disposed on the substrate and a gate disposed on the gate dielectric layer. There is an interface between the gate dielectric layer and the substrate. The doped regions are disposed in the substrate around the recesses. The charge storage layers are disposed in the recesses, and a top surface of each of the charge storage layers is higher than the interface. The first dielectric layer is disposed between the charge storage layers and the substrate, and between the charge storage layers and the gate structure. | 06-12-2014 |
20140231900 | NON-VOLATILE MEMORY - A non-volatile memory is provided. The non-volatile memory includes a oxide and polysilicon stack structure and charge storage layers. The oxide and polysilicon stack structure is disposed on a substrate. There are recesses in the substrate at two sides of the oxide and polysilicon stack structure. The oxide and polysilicon stack structure includes an oxide layer and a polysilicon layer. The oxide layer is disposed on the substrate, wherein there is an interface between the oxide layer and the substrate. The polysilicon layer is disposed on the oxide layer. The charge storage layers are disposed in the recesses and extend to a side wall of the oxide and polysilicon stack structure, and a top surface of each of the charge storage layers is higher than the interface. | 08-21-2014 |
20150023098 | OPERATION METHOD OF MULTI-LEVEL MEMORY - An operation method of a multi-level memory is provided. A first read voltage lower than a standard read voltage is applied to a doped region in a substrate at one side of a control gate of the memory, so as to determine whether a first storage position and a second storage position are both at the lowest level. | 01-22-2015 |