Patent application number | Description | Published |
20130326199 | METHOD AND APPARATUS FOR CONTROLLING A MXCSR - Disclosed is an apparatus and method generally related to controlling a multimedia extension control and status register (MXCSR). A processor core may include a floating point unit (FPU) to perform arithmetic functions; and a multimedia extension control register (MXCR) to provide control bits to the FPU. Further an optimizer may be used to select a speculative multimedia extension status register (SPEC_MXSR) from a plurality of SPEC_MXSRs to update a multimedia extension status register (MXSR) based upon an instruction. | 12-05-2013 |
20130332705 | PROFILING ASYNCHRONOUS EVENTS RESULTING FROM THE EXECUTION OF SOFTWARE AT CODE REGION GRANULARITY - A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region. | 12-12-2013 |
20140019721 | MANAGED INSTRUCTION CACHE PREFETCHING - Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: indentifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache. | 01-16-2014 |
20140095849 | INSTRUCTION AND LOGIC FOR OPTIMIZATION LEVEL AWARE BRANCH PREDICTION - A computer-readable storage medium, method and system for optimization-level aware branch prediction is described. A gear level is assigned to a set of application instructions that have been optimized. The gear level is also stored in a register of a branch prediction unit of a processor. Branch prediction is then performed by the processor based upon the gear level. | 04-03-2014 |
20140156976 | METHOD, APPARATUS AND SYSTEM FOR SELECTIVE EXECUTION OF A COMMIT INSTRUCTION - Techniques and mechanisms for a processor to determine whether a commit action is to be performed. In an embodiment, a processor performs operations to determine whether a commit instruction is for contingent performance of a commit action. In another embodiment, one or more conditions of processor state are evaluated in response to determining that the commit instruction is for contingent performance of the commit action, where the evaluation is performed to determine whether the commit action indicated by the commit instruction is to be performed. | 06-05-2014 |
Patent application number | Description | Published |
20140032873 | WORKLOAD ADAPTIVE ADDRESS MAPPING - Embodiments of the invention describe an apparatus, system and method for workload adaptive address mapping. Embodiments of the invention may receive a request to initialize a system memory including a plurality of memory banks. Using a plurality of memory address mapping schemes for memory settings for the system memory, a system characterization workload is executed during the initialization of the system memory, the system characterization workload including a plurality of transactions directed towards the system memory. Embodiments of the invention may monitor target addresses of the plurality of transactions directed towards the system memory. One of the plurality of memory address mapping schemes is selected based, at least in part, on the target addresses of the plurality of transactions. | 01-30-2014 |
20140052891 | SYSTEM AND METHOD FOR MANAGING PERSISTENCE WITH A MULTI-LEVEL MEMORY HIERARCHY INCLUDING NON-VOLATILE MEMORY - An apparatus and method for implementing non-volatile store (nvstore) and non-volatile flush (nvflush) instructions. For example, a method according to one embodiment comprises: executing a set of non-volatile store instructions indicating data to be persisted to a non-volatile memory (NVM) of a multi-level system memory hierarchy; generating an entry in an NVM store queue prior to storing the data to the NVM, each entry indicating that the data associated therewith has not yet been persisted to non-volatile memory; executing a non-volatile flush instruction at a time when the data associated with each entry in the non-volatile store queue should be persisted to non-volatile memory; and removing the entries from the NVM store queue as the data associated with each entry is written to non-volatile memory | 02-20-2014 |
20140089559 | APPARATUS, SYSTEM AND METHOD FOR ADAPTIVE CACHE REPLACEMENT IN A NON-VOLATILE MAIN MEMORY SYSTEM - Techniques and mechanisms for adaptively changing between replacement policies for selecting lines of a cache for eviction. In an embodiment, evaluation logic determines a value of a performance metric which is for writes to a non-volatile memory. Based on the determined value of the performance metric, a parameter value of a replacement policy is determined. In another embodiment, cache replacement logic performs a selection of a line of cache for data eviction, where the selection is in response to the policy unit providing an indication of the determined parameter value. | 03-27-2014 |
20140089595 | UTILITY AND LIFETIME BASED CACHE REPLACEMENT POLICY - Embodiments of the invention describe an apparatus, system and method for utilizing a utility and lifetime based cached replacement policy as described herein. For processors having one or more processor cores and a cache memory accessible via the processor core(s), embodiments of the invention describe a cache controller to determine, for a plurality of cache blocks in the cache memory, an estimated utility and lifetime of the contents of each cache block, the utility of a cache block to indicate a likelihood of use its contents, the lifetime of a cache block to indicate a duration of use of its contents. Upon receiving a cache access request resulting in a cache miss, said cache controller may select one of the cache blocks to be replaced based, at least in part, on one of the estimated utility or estimated lifetime of the cache block. | 03-27-2014 |
20140189243 | SECTORED CACHE WITH HYBRID LINE GRANULARITY - A coarse-grained cache line may be associated with a way from a set in a cache. A first sector of the coarse-grained cache line may be stored in the way. The coarse-grained cache line may include a predetermined number of sectors. A fine-grained cache line may be associated with the way. A second sector of the fine-grained cache line may be stored in the way. The fine-grained cache line may include a predetermined number of sectors. The predetermined number of sectors in the fine-grained cache line may be lower than the predetermined number of sectors in the coarse-grained cache line. | 07-03-2014 |
20140189284 | SUB-BLOCK BASED WEAR LEVELING - Embodiments of the invention describe an apparatus, system and method for sub-block based wear leveling for memory devices. Embodiments of the invention may receive a write request to a physical memory address including a physical block address and a physical sub-block address. An address remapping table is accessed to translate the physical block address to a memory device block address to locate a plurality of memory device sub-blocks. A plurality of sub-block activity counters are accessed, each sub-block activity counter associated with one of the memory device sub-blocks. One of the plurality of memory device sub-blocks is selected to store write data of the write request based, at least in part, on values of the plurality of sub-block activity counters, and the value of the sub-block activity counter associated with the selected memory device sub-block is updated. | 07-03-2014 |
20140201495 | PAGE MISS HANDLER INCLUDING WEAR LEVELING LOGIC - Embodiments of the invention describe an apparatus, system and method for utilizing a page miss handler having wear leveling logic/modules for memory devices. Embodiments of the invention may track an amount of writes directed towards cells of a memory device, and determine whether a linear address specified by a system write transaction is included in a translation-lookaside buffer (TLB). In response to determining the linear address is not included in the TLB, resulting in a TLB miss, embodiments of the invention may perform a page table walk to obtain a corresponding physical address, and convert the physical address to a device address for accessing the memory device based the tracked amount of writes. Thus, embodiments of the invention are more efficient compared to prior art solutions, as instead of all memory operations, only those that miss in the TLB incur additional wear leveling address translation overhead. | 07-17-2014 |