Patent application number | Description | Published |
20090109642 | SEMICONDUCTOR MODULES AND ELECTRONIC DEVICES USING THE SAME - Semiconductor devices and electronic devices using the same. The semiconductor module may include a first semiconductor chip, and a module substrate having a top surface on which the first semiconductor chip is mounted and a second surface opposite the top surface, wherein the module substrate includes a first buffer layer to relieve stress occurring due to a difference of thermal expansions between the first semiconductor chip and the module substrate. | 04-30-2009 |
20090111217 | Method of manufacturing chip-on-chip semiconductor device - Provided is a method of fabricating a chip-on-chip (COC) semiconductor device. The method of fabricating a chip-on-chip (COC) semiconductor device may include preparing a first semiconductor device with a metal wiring having at least one discontinuous spot formed therein, preparing a second semiconductor device with at least one bump formed on a surface of the second semiconductor device corresponding to the at least one discontinuous spot, aligning the first semiconductor device onto the second semiconductor device, and connecting the at least one bump of the second semiconductor device to the at least one discontinuous spot formed in the metal wiring of the first semiconductor device. | 04-30-2009 |
20090168382 | SEMICONDUCTOR MODULE - A semiconductor module can include a printed circuit board (PCB) and a semiconductor package inserted into an inner space of the PCB. The semiconductor package may be electrically connected to the PCB. The PCB may thus surround the semiconductor package so that cracks may not be generated in the outer terminals. | 07-02-2009 |
20090184411 | SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME - Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure. | 07-23-2009 |
20090215229 | Board on chip package and method of manufacturing the same - A ball grid array type board on chip package may include an integrated circuit chip having an active surface that supports a plurality of contact pads. An interposer may be adhered to the active surface of the integrated circuit chip. At least one hole may be provided through the interposer to expose the contact pads. A board, which may have a first surface supporting a plurality of metal lines, may have a second surface adhered to the interposer. The board may have an opening through which the contact pads may be exposed. A plurality of bonding wires may connect the contact pads to the metal lines through the opening. | 08-27-2009 |
20090230548 | SEMICONDUCTOR PACKAGE AND MULTI-CHIP PACKAGE USING THE SAME - A semiconductor package may have a semiconductor chip that includes a chip pad formed on a substrate including an integrated circuit, and a passivation layer exposing the chip pad, a first redistribution wiring layer that is connected to the chip pad and extends on the semiconductor chip and includes a wire bonding pad to provide wire bonding and a first solder pad to connect the first redistribution wiring layer to a second semiconductor chip, and a second redistribution wiring layer that is connected to the first redistribution wiring layer on the first redistribution wiring layer and includes a second solder pad to connect the second redistribution wiring layer to a third semiconductor chip. | 09-17-2009 |
20090302418 | FUSE STRUCTURE OF A SEMICONDUCTOR DEVICE - Provided is a fuse structure of a semiconductor device. The fuse structure may include an insulating layer pattern structure, a fuse and a protecting layer pattern. The insulating layer pattern structure may be formed on a substrate. The insulating layer pattern structure may have an opening. The fuse may be formed in the opening. The protecting layer pattern may be formed in the opening of the insulating layer pattern structure to cover the fuse. | 12-10-2009 |
20090315177 | Semiconductor package with joint reliability - A semiconductor package with improved joint reliability and a method of fabricating the semiconductor package are disclosed. A conductive connector may be formed on a surface of a semiconductor wafer on which semiconductor devices may be arranged. A first insulating layer including a first opening through which a portion of the connection pad is exposed may be formed on the connection pad and the semiconductor wafer. A rewiring line electrically connected to an exposed portion of the connection pad may be formed on the first insulating layer. A second insulating layer including a second opening through which a portion of the rewiring line is exposed may be formed on the rewiring line and the first insulating layer. A connection terminal including one or more entangled wires may be formed on an exposed portion of the rewiring line so as to be electrically connected to the rewiring line. | 12-24-2009 |
20100032807 | Wafer level semiconductor module and method for manufacturing the same - A wafer level semiconductor module may include a module board and an IC chip set mounted on the module board. The IC chip set may include a plurality of IC chips having scribe lines areas between the adjacent IC chips. Each IC chip may have a semiconductor substrate having an active surface with a plurality of chip pads and a back surface. A passivation layer may be provided on the active surface of the semiconductor substrate of each IC chip and may having openings through which the chip pads may be exposed. Sealing portions may be formed in scribe line areas. | 02-11-2010 |
20100078819 | INTER CONNECTION STRUCTURE INCLUDING COPPER PAD AND PAD BARRIER LAYER, SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME - A semiconductor device including an interconnection structure including a copper pad, a pad barrier layer and a metal redistribution layer, an interconnection structure thereof and methods of fabricating the same are provided. The semiconductor device includes a copper pad disposed on a first layer, a pad barrier layer including titanium disposed on the copper pad, an inorganic insulating layer disposed on the pad barrier layer, a buffer layer disposed on the inorganic insulating layer, wherein the inorganic insulating layer and the buffer layer expose a portion of the pad barrier layer, a seed metal layer disposed on the exposed buffer layer, a metal redistribution layer disposed on the seed metal layer, and a first protective layer disposed on the metal redistribution layer. | 04-01-2010 |
20100105169 | SEMICONDUCTOR CHIP HAVING VIA ELECTRODES AND STACKED SEMICONDUCTOR CHIPS INTERCONNECTED BY THE VIA ELECTRODES - A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another. | 04-29-2010 |
20110104888 | SEMICONDUCTOR DEVICES HAVING REDISTRIBUTION STRUCTURES AND PACKAGES, AND METHODS OF FORMING THE SAME - Semiconductor devices and methods of forming the same, including forming a chip pad on a chip substrate, forming a passivation layer on the chip pad and the chip substrate, forming a first insulation layer on the passivation layer, forming a recess and a first opening in the first insulation layer, forming a second opening in the passivation layer to correspond to the first opening, forming a redistribution line in a redistribution line area of the recess, the first opening, and the second opening, forming a second insulation layer on the redistribution line and the first insulation layer, and forming an opening in the second insulation to expose a portion of the redistribution line as a redistribution pad. | 05-05-2011 |
20120129334 | SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME - Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure. | 05-24-2012 |
20120299194 | SEMICONDUCTOR CHIP HAVING VIA ELECTRODES AND STACKED SEMICONDUCTOR CHIPS INTERCONNECTED BY THE VIA ELECTRODES - A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another. | 11-29-2012 |
20130200525 | VIA CONNECTION STRUCTURES, SEMICONDUCTOR DEVICES HAVING THE SAME, AND METHODS OF FABRICATING THE STRUCTURES AND DEVICES - A semiconductor device including a lower layer, an insulating layer on a first side of the lower layer, an interconnection structure in the insulating layer, a via structure in the lower layer. The via structure protrudes into the insulating layer and the interconnection structure. | 08-08-2013 |
20130244419 | INTER CONNECTION STRUCTURE INCLUDING COPPER PAD AND PAD BARRIER LAYER, SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME - A semiconductor device including an interconnection structure including a copper pad, a pad barrier layer and a metal redistribution layer, an interconnection structure thereof and methods of fabricating the same are provided. The semiconductor device includes a copper pad disposed on a first layer, a pad barrier layer including titanium disposed on the copper pad, an inorganic insulating layer disposed on the pad barrier layer, a buffer layer disposed on the inorganic insulating layer, wherein the inorganic insulating layer and the buffer layer expose a portion of the pad barrier layer, a seed metal layer disposed on the exposed buffer layer, a metal redistribution layer disposed on the seed metal layer, and a first protective layer disposed on the metal redistribution layer. | 09-19-2013 |
20130264720 | Semiconductor Chips Having Through Silicon Vias and Related Fabrication Methods and Semiconductor Packages - A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer. | 10-10-2013 |