Patent application number | Description | Published |
20080248632 | Methods of Fabricating Multi-Bit Phase-Change Memory Devices and Devices Formed Thereby - Methods of forming integrated circuit devices include forming at least one non-volatile memory cell on a substrate. The memory cell includes a plurality of phase-changeable material regions therein that are electrically coupled in series. This plurality of phase-changeable material regions are collectively configured to support at least 2-bits of data when serially programmed using at least four serial program currents. Each of the plurality of phase-changeable material regions has different electrical resistance characteristics when programmed. | 10-09-2008 |
20080266942 | Multiple level cell phase-change memory device having pre-reading operation resistance drift recovery, memory systems employing such devices and methods of reading memory devices - A memory device comprises a plurality of memory cells, each memory cell comprising a memory cell material that has an initial resistance that is determined in response to an applied programming current in a programming operation, the resistance of the memory cell varying from the initial resistance over a time period following the programming operation, and each memory cell being connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a read operation. A modification circuit modifies the resistance of a memory cell of the plurality of memory cells selected for a read operation to return its resistance to near the initial resistance prior to a read operation of the memory cell. | 10-30-2008 |
20080277720 | NON-VOLATILE MEMORY DEVICE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A non-volatile memory device which can be highly-integrated without a decrease in reliability, and a method of fabricating the same, are provided. In the non-volatile memory device, a first doped layer of a first conductivity type is disposed on a substrate. A semiconductor pillar of a second conductivity type opposite to the first conductivity type extends upward from the first doped layer. A first control gate electrode substantially surrounds a first sidewall of the semiconductor pillar. A second control gate electrode substantially surrounds a second sidewall of the semiconductor pillar and is separated from the first control gate electrode. A second doped layer of the first conductivity type is disposed on the semiconductor pillar. | 11-13-2008 |
20080316804 | Multiple level cell phase-change memory devices having controlled resistance drift parameter, memory systems employing such devices and methods of reading memory devices - In a method of controlling resistance drift in a memory cell of a resistance-changeable material memory device, the resistance changeable material in the memory cell is treated so that a drift parameter for the memory cell is less than about 0.18, wherein a change in resistance of a memory cell over the time period is determined according to the relationship: | 12-25-2008 |
20090016099 | Multiple level cell phase-change memory devices having post-programming operation resistance drift saturation, memory systems employing such devices and methods of reading memory devices - In a memory device and in a method of programming the same, a memory device comprises: a plurality of memory cells, each memory cell comprising a resistance-changeable material that has an initial resistance that is determined in response to an applied programming current in a programming operation; and a modification circuit that modifies the resistance of the memory cell following a programming operation of the memory cell to vary the resistance of the memory cell from the initial resistance to a second resistance by applying a saturation current in a saturation operation. Each memory cell is connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation, that is used to apply the saturation current to the corresponding memory cell in the saturation operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a subsequent read operation. | 01-15-2009 |
20090075414 | BIOCHIP AND METHOD OF FABRICATION - A method of fabricating a biochip and a biochip fabricated by the method are provided. The method can include providing a substrate including a plurality of first areas separated from each other by a second area, forming a plurality of activation patterns on each of the first areas, coupling a plurality of probes to each of the activation patterns, and cutting the substrate along the second area to form a plurality of chips. | 03-19-2009 |
20090093625 | APPARATUS FOR AND METHOD OF SYNTHESIZING BIOPOLYMER AND METHOD OF RECOVERING REAGENT FOR SYNTHESIZING BIOPOLYMER - An apparatus for synthesizing a biopolymer includes a reaction chamber, an outlet tube connected to the reaction chamber, a plurality of recovery tanks connected to the outlet tube, and a plurality of recovery valves configured to open or block the passageway between the outlet tube and each of the recovery tanks. | 04-09-2009 |
20090099039 | BINARY-COUPLED PROBE ARRAY, BIOCHIP, AND METHOD OF FABRICATION - A binary-coupled type probe array for analyzing components of a biological sample using probes, a biochip, and a method of fabricating the same, are provided. The binary-coupled probe array can include a substrate, a plurality of first probes immobilized on a top surface of the substrate, and a plurality of second probes immobilized on a bottom surface of the substrate. | 04-16-2009 |
20090201721 | Phase change memory device and write method thereof - A phase change memory device and a write method thereof allow writing of both volatile and non-volatile data on the phase change memory device. The phase change memory device may be written by setting a write mode as one of a volatile write mode and a non-volatile write mode, and writing data as volatile or non-volatile by applying a write pulse corresponding to the write mode, wherein, when power is not supplied to the phase change memory device, the non-volatile data is retained and the volatile data is not retained. | 08-13-2009 |
20090230376 | RESISTIVE MEMORY DEVICES - Provided is a resistive memory device that can be integrated with a high integration density and method of forming the same. In an embodiment, a bit line is formed of copper using a damascene technique, and when the copper bit line, a copper stud may be formed around the copper bit line | 09-17-2009 |
20090230378 | RESISTIVE MEMORY DEVICES - Provided is a resistive memory device that can be integrated with a high integration density and method of forming the same. An insulating layer enclosing a resistive memory element and an insulating layer enclosing a conductive line connected with the resistive memory element have different stresses, hardness, porosity degrees, dielectric constant or heat conductivities. | 09-17-2009 |
20090275190 | METHOD FOR FORMING BUFFER LAYER FOR GaN SINGLE CRYSTAL - Disclosed is a method for forming a buffer layer for growing gallium nitride single crystals on a sapphire substrate using hydride vapor phase epitaxy (HVPE), wherein the buffer layer is formed in the form of a doped vertical gallium nitride (GaN) single crystal film with a nanoporosity of 0.10 to 0.15 μm on the sapphire substrate by reacting HCl and NH | 11-05-2009 |
20100072453 | Phase-Changeable Fuse Elements and Memory Devices Containing Phase-Changeable Fuse Elements and Memory Cells Therein - Non-volatile memory devices include an array of phase-changeable memory cells, which have first phase-changeable material patterns therein, and at least one phase-changeable fuse element. This phase-changeable fuse element includes a second phase-changeable material pattern therein with a higher crystallization temperature relative to the first phase-changeable material patterns in the array of phase-changeable memory cells. This higher crystallization temperature may be greater than about 300° C. According to additional embodiments of the present invention, the at least one phase-changeable fuse element includes a composite of the second phase-changeable material pattern and a third phase-changeable material pattern, which is formed of the same material at the first phase-changeable material patterns. | 03-25-2010 |
20100090194 | MULTI-BIT PHASE-CHANGE RANDOM ACCESS MEMORY (PRAM) WITH DIAMETER-CONTROLLED CONTACTS AND METHODS OF FABRICATING AND PROGRAMMING THE SAME - A phase-change random-access memory (PRAM) device includes a chalcogenide element, the chalcogenide element comprising a material which can assume a crystalline state or an amorphous state upon application of a heating current. A first contact is connected to a first region of the chalcogenide element and has a first cross-sectional area. A second contact is connected to a second region of the chalcogenide element and having a second cross-sectional area. A first programmable volume of the chalcogenide material is defined in the first region of the chalcogenide element, a state of the first programmable volume being programmable according to a resistance associated with the first contact. A second programmable volume of the chalcogenide material is defined in the second region of the chalcogenide element, a state of the second programmable volume being programmable according to a second resistance associated with the second contact. | 04-15-2010 |
20110188304 | MULTIPLE LEVEL CELL PHASE-CHANGE MEMORY DEVICES HAVING PRE-READING OPERATION RESISTANCE DRIFT RECOVERY, MEMORY SYSTEMS EMPLOYING SUCH DEVICES AND METHODS OF READING MEMORY DEVICES - A memory device comprises a plurality of memory cells, each memory cell comprising a memory cell material that has an initial resistance that is determined in response to an applied programming current in a programming operation, the resistance of the memory cell varying from the initial resistance over a time period following the programming operation, and each memory cell being connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a read operation. A modification circuit modifies the resistance of a memory cell of the plurality of memory cells selected for a read operation to return its resistance to near the initial resistance prior to a read operation of the memory cell. | 08-04-2011 |