Huo
Caihong Huo, Foshan City CN
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20150335270 | DETECTING APPARATUS FOR CURVED SURFACE OF SOLE AND DISTRIBUTION OF PRESSURE THEREON - A detecting apparatus for curved surface of sole and distribution of pressure thereon, that includes a housing, a top plate enclosed at an opening of the housing, a detecting mechanism capable of vertical reciprocating movement and contacting the curved surface of sole, a detecting circuit collecting the vertical movement data of the detecting mechanism and transferring the vertical movement data to a data processing system, and the data processing system receiving and analyzing the data as well as re-constructing the profile of sole. The detection and reconstruction for 3D surface of the sole and pressure distribution thereon can be achieved by emitting and receiving an infrared ray, with high precision, strong anti-jamming ability, low power consumption and low cost. | 11-26-2015 |
Caihong Huo, Foshan City, Guangdong CN
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20150335270 | DETECTING APPARATUS FOR CURVED SURFACE OF SOLE AND DISTRIBUTION OF PRESSURE THEREON - A detecting apparatus for curved surface of sole and distribution of pressure thereon, that includes a housing, a top plate enclosed at an opening of the housing, a detecting mechanism capable of vertical reciprocating movement and contacting the curved surface of sole, a detecting circuit collecting the vertical movement data of the detecting mechanism and transferring the vertical movement data to a data processing system, and the data processing system receiving and analyzing the data as well as re-constructing the profile of sole. The detection and reconstruction for 3D surface of the sole and pressure distribution thereon can be achieved by emitting and receiving an infrared ray, with high precision, strong anti-jamming ability, low power consumption and low cost. | 11-26-2015 |
Changqin Huo, Alberta CA
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20100027721 | Method and System for Implementing a Multiple-Input Multiple-Output (MIMO) Decoder Scheme - The teachings of the present disclosure relate to a method for receiving “N” data streams (wherein “N” is a number greater than one) from “N” endpoints. Each of the data streams are received from a different respective endpoint. The method also includes decoding the “N” data streams by generating a decoding signal input comprising the “N” data streams and then iteratively repeating the following steps “N”−1 times: determine a most reliable stream; decode the most reliable stream using linear multiple-input and multiple-output (MIMO) decoding; output the decoded most reliable stream; estimate a signal estimate based on the most reliable stream and modulation information associated with the most reliable stream; and generate a residual signal that comprises the remaining data streams less the signal estimate. Upon the residual signal comprising two data streams, the method includes updating the decoding signal input to be the residual signal. Upon the residual signal comprising a single received stream, the method includes decoding the residual signal using a maximum likelihood decoder. | 02-04-2010 |
Chenfu Huo, Hangzhou CN
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20150339700 | METHOD, APPARATUS AND SYSTEM FOR PROCESSING PROMOTION INFORMATION - The present disclosure provides a method, an apparatus and a system for processing promotion information. In one aspect, embodiments of the present disclosure introduce a PS, which is used to characterize the quality of promotion information, into an eCTR as a new calculation factor, and therefore ensure the consistency between calculation logics of the PS and a RS, and can avoid the problem of inconsistency between the quality of the promotion information and the position of presenting the promotion information caused by the inconsistency between the calculation logics of the PS and the RS, thereby improving the effectiveness of pushing the promotion information. | 11-26-2015 |
Dawei Huo, Shenzhen CN
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20150339748 | RADIO CHANNEL CONTROL METHOD, TRAFFIC PACKAGE TRADING AND RECOMMENDING METHODS, AND RELATED DEVICE - A radio channel control method includes: collecting a real-time user experience index for access to a media service by a user terminal, and collecting a media service transmission parameter of the media service provided by a server; determining whether the real-time user experience index is less than a user experience index defined in a user experience level of an ordered traffic package of the user terminal, and if the real-time user experience index is less than the user experience index defined in the user experience level of the ordered traffic package of the user terminal, calculating, by using the real-time user experience index and the media service transmission parameter, a radio channel parameter that is required by the user experience index; and transmitting the radio channel parameter to a core network device. | 11-26-2015 |
Donald Tai-Chan Huo, Hsinchu TW
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20120138991 | HIGH-EFFICIENCY LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - This invention provides a high-efficiency light-emitting device and the manufacturing method thereof The high-efficiency light-emitting device includes a substrate; a reflective layer; a bonding layer; a first semiconductor layer; an active layer; and a second semiconductor layer formed on the active layer. The second semiconductor layer includes a first surface having a first lower region and a first higher region. | 06-07-2012 |
Fengwei Huo, Nanyang Heights SG
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20120097058 | Multiplexed Biomolecule Arrays Made By Polymer Pen Lithography - Methods of patterning multiple biomolecules on a surface are disclosed. The method includes inking a polymer pen array, where tips are inked with selected inks comprising the biomolecules, and transferring the biomolecules to a surface using a polymer pen lithography technique. Methods of using the multiple patterned biomolecules on a surface are also disclosed. | 04-26-2012 |
20120128882 | GEL POLYMER PEN LITHOGRAPHY - The disclosure relates to methods of printing indicia on a substrate using a tip array comprised of elastomeric, compressible gel polymers. The tip array can be prepared using conventional photolithographic methods and can be tailored to have any desired number and/or arrangement of tips. Numerous copies (e.g., greater than 15,000, or greater than 11 million) of a pattern can be made in a parallel fashion in as little as 40 minutes. | 05-24-2012 |
Jiaquan Huo, Hurtsville Grove AU
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20150023514 | Method and Apparatus for Acoustic Echo Control - Embodiments of method and apparatus for acoustic echo control are described. According to the method, an echo energy-based doubletalk detection is performed to determine whether there is a doubletalk in a microphone signal with reference to a loudspeaker signal. A spectral similarity between spectra of the microphone signal and the loudspeaker signal is calculated. It is determined that there is no doubletalk in the microphone signal if the spectral similarity is higher than a threshold level. Adaption of an adaptive filter for applying acoustic echo cancellation or acoustic echo suppression on the microphone signal is enabled if it is determined that there is no doubletalk in the microphone signal through the echo energy-based doubletalk detection, or there is no doubletalk through the spectral similarity-based doubletalk detection. | 01-22-2015 |
Ker Hsiao Huo, Zhubei City TW
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20150262995 | SERIES RESISTOR OVER DRAIN REGION IN HIGH VOLTAGE DEVICE - Some embodiments relate to a semiconductor device. The semiconductor device includes a drain region and a channel region surrounding the drain region. A source region surrounds the channel region such that the channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and has an inner edge proximate to the drain. A resistor structure, which is made up of a curved or polygonal path of resistive material, is arranged over the drain and is coupled to the drain. The resistor structure is perimeterally bounded by the inner edge of the gate electrode. | 09-17-2015 |
Ker-Hsiao Huo, Hsinchu County TW
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20160111498 | Insulated Gate Bipolar Transistor Structure Having Low Substrate Leakage - A method of making a high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), is disclosed. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate. | 04-21-2016 |
Ker-Hsiao Huo, Taichung City TW
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20110241114 | HIGH VOLTAGE MOS TRANSISTOR - A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS) and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. One portion of the second well surrounds the source and the other portion of the second well extends laterally from the first portion in the first well. | 10-06-2011 |
20120139041 | HIGH SIDE GATE DRIVER DEVICE - The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region. | 06-07-2012 |
20120181629 | HV Interconnection Solution Using Floating Conductors - A device includes a first and a second heavily doped region in a semiconductor substrate. An insulation region has at least a portion in the semiconductor substrate, wherein the insulation region is adjacent to the first and the second heavily doped regions. A gate dielectric is formed over the semiconductor substrate and having a portion over a portion of the insulation region. A gate is formed over the gate dielectric. A floating conductor is over and vertically overlapping the insulation region. A metal line includes a portion over and vertically overlapping the floating conductor, wherein the metal line is coupled to, and carries a voltage of, the second heavily doped region. | 07-19-2012 |
20120299096 | HIGH VOLTAGE AND ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGES - A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages. | 11-29-2012 |
20130161689 | INSULATED GATE BIPOLAR TRANSISTOR STRUCTURE HAVING LOW SUBSTRATE LEAKAGE - A high voltage laterally diffused metal-oxide-semiconductor (HV LDMOS) device, particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate having at least one highly doped buried portion, a first doped well grown over the substrate, a gate structure formed on the first well, a source and a drain formed on either side of the gate structure, and a second doped well having a U-shaped cross section formed in the first well. A portion of the drain is formed over the first well outside of the second well. | 06-27-2013 |
20130207187 | INSULATED GATE BIPOLAR TRANSISTOR STRUCTURE HAVING LOW SUBSTRATE LEAKAGE - A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate. | 08-15-2013 |
20130313617 | Embedded JFETs for High Voltage Applications - A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET. | 11-28-2013 |
20140021560 | HIGH VOLTAGE DEVICE WITH A PARALLEL RESISTOR - Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a transistor having a gate, a source, and a drain. The source and the drain are formed in a doped substrate and are separated by a drift region of the substrate. The gate is formed over the drift region and between the source and the drain. The transistor is configured to handle high voltage conditions that are at least a few hundred volts. The high voltage semiconductor device includes a dielectric structure formed between the source and the drain of the transistor. The dielectric structure protrudes into and out of the substrate. Different parts of the dielectric structure have uneven thicknesses. The high voltage semiconductor device includes a resistor formed over the dielectric structure. The resistor has a plurality of winding segments that are substantially evenly spaced apart. | 01-23-2014 |
20140035035 | INSULATED GATE BIPOLAR TRANSISTOR STRUCTURE HAVING LOW SUBSTRATE LEAKAGE - A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate. | 02-06-2014 |
20140054695 | High Side Gate Driver Device - The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region. | 02-27-2014 |
20140139282 | Embedded JFETs for High Voltage Applications - A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET. | 05-22-2014 |
20140231884 | BOOTSTRAP MOS FOR HIGH VOLTAGE APPLICATIONS - A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region. | 08-21-2014 |
20140327075 | HIGH VOLTAGE AND ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGES - A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages. | 11-06-2014 |
20150072496 | METHOD OF MAKING AN INSULATED GATE BIPOLAR TRANSISTOR STRUCTURE - A method for fabricating a high voltage semiconductor transistor includes growing a first well region over a substrate having a first conductivity type, the first well region having a second type of conductivity. First, second and third portions of a second well region having the first type of conductivity are doped into the first well region. A first insulating layer is grown in and over the first well portion within the second well region. A second insulating layer is grown on the substrate over the third portion of the second well region. An anti-punch through region is doped into the first well region. A gate structure is formed on the substrate. A source region is formed in the first portion of the second well region on an opposite side of the gate structure from the first insulating layer. A drain region is formed in the first well region. | 03-12-2015 |
20150263164 | HIGH VOLTAGE AND ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICES WITH INCREASED BREAWKDOWN VOLTAGES - A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages. | 09-17-2015 |
20160056303 | Bootstrap MOS for High Voltage Applications - A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region. | 02-25-2016 |
Ming Huo, Windsor CA
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20140154455 | COMPONENT FOR A VEHICLE - A component for a vehicle, includes at least one component part, which is made of a magnetically active foam material and/or a foam material which can be magnetically activated and/or a dielectric elastomer. The component is at least partially or completely laterally delimited so that the component elastically expandable in at least one degree of freedom. The component can be a switch element, a transducer, an active muffler, and/or an energy conversion element. | 06-05-2014 |
Ping Huo, Chengdu CN
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20150276078 | Valve Stem and Valve Core Assembly and Valve Comprising the Assembly - The present invention relates to a valve stem and valve core assembly and a valve comprising the assembly. The valve core sleeves the valve stem, an adjusting device is arranged on the valve stem, an elastic element is arranged between the adjusting device and the valve core, and a clearance exists among the valve core, the valve stem and the adjusting device, so that the valve core can move relative to the valve stem and the valve can have a good closing performance. | 10-01-2015 |
20150277450 | Drive Device and Valve Comprising the Same - The invention relates to a drive device and a valve comprising the drive device; the drive device senses the pressure of the working medium and generates the drive force to control the flow of the working medium; the drive device comprises a sensing part with a chamber and a drive shaft; vents and an air exhausting device are arranged on the chamber. The drive device and the valve comprising the drive device in the invention can exhaust air entering the chamber along the working medium out of the chamber by the vents on the chamber; and it optimizes the performance of the drive device and the valve and keeps the work stability. | 10-01-2015 |
20150277451 | Driving Apparatus and Valve Including the Same - The present invention relates to a driving apparatus and a valve including the same. The driving apparatus senses a pressure of a fluid medium and generating a driving force, and includes: a drive shaft, a sensing device, a limiting device, a support body, and a protruding member. The limiting device is provided with a groove, and the protruding member is engaged in the groove. The limiting device can automatically limit the rotation of the drive shaft, to avoid damaging to the sensing device, thereby facilitating maintenance and installation of the valve. | 10-01-2015 |
Shoudong Huo, Dhahran SA
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20120290213 | FREQUENCY-VARYING FILTERING OF SIMULTANEOUS SOURCE SEISMIC DATA - Seismic data acquired by independent simultaneous sweeping (ISS®) techniques are processed is to attenuate random uncompressed cross-talk signals and improve the resolution of the pre-stack migrated time image. A frequency-varying mean filter is applied on cross-spread offset-azimuth gathers of the data. The frequency-space domain filter may vary its window size according to the characteristics of the cross-talk. | 11-15-2012 |
20120290214 | COUPLED TIME-DISTANCE DEPENDENT SWEPT FREQUENCY SOURCE ACQUISITION DESIGN AND DATA DE-NOISING - Acquisition of data by managing crosstalk interference with sector designs and unique sweeps is conducted and the resultant data are processed in 3D common receiver domain to attenuate crosstalk noise while preserving the signals for high source and receiver density acquisition designs. High-amplitude spectral amplitudes are attenuated and inter-ensemble statics or structural time delays are applied to achieve optimum filter performance. If the spectral amplitudes have been attenuated to a level consistent with non-simultaneous acquisition, conventional surface consistent processing can be performed to correct for statics and amplitude variations. A 3-point filter in different frequency bands may then be applied to remove any remaining residual crosstalk noise. | 11-15-2012 |
Shoudong Huo, Ras Tanura SA
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20130155813 | ITERATIVE DIP-STEERING MEDIAN FILTER FOR SEISMIC DATA PROCESSING - An iterative dip-steering median filter is provided for random noise attenuation in seismic data where conflicting dips are indicated in the data. A number of dominant dips inside a processing window or sample of the data are identified by a Fourier-radial transform in the frequency-wavenumber domain. A median filter is then applied along the dominant dip to remove noise, and the remaining signal after filtering is retained for further median filter iterations. Iterations are repeated to apply the median filter along the most dominant dip in the remaining data. The processing continues in subsequent iterations until all selected dips have been processed. The remaining signal of each iteration is then summed for final output. | 06-20-2013 |
Tong-Wang Huo, New Taipei City TW
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20150296037 | PUSHLET INSTANT MESSAGING FRAMEWORK AND PUSHLET INSTANT MESSAGING METHOD - A Pushlet IM method for pushing a message from a first client device to a second client device includes the steps of: providing a Java-based web service; receiving a message from the first client device, the message including information of a recipient entity; verifying identity of a sender entity who intends to send the message to the recipient entity using the first client device; and creating a thread according to the information of the recipient entity for pushing the message to the second client device that is associated with the recipient entity. | 10-15-2015 |
Xiao Huo, Hong Kong HK
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20110299202 | NMOS-Based Feedback Power-Clamp for On-Chip ESD Protection - A power-to-ground clamp transistor provides electrostatic discharge (ESD) protection. A filter capacitor and resistor generate a filter voltage that is buffered by three stages to drive the gate of the clamp transistor. The filter capacitor is about twenty times smaller than in a conventional clamp circuit. Feedback in the circuit keeps the clamp transistor turned on after the R-C time constant of the capacitor and resistor in the filer has elapsed, allowing for a smaller capacitor to turn on the clamp transistor longer. A sub-threshold-conducting transistor in the first stage conducts only a small sub-threshold current, which extends the discharge time of the first stage. The gate of the sub-threshold-conducting transistor is driven by feedback from the second stage. A feed-forward resistor has a high resistance value to slowly raise the voltage of the second stage from the filter voltage, and thus slowly raise the gate of the sub-threshold-conducting transistor. | 12-08-2011 |
20140222882 | Phase-to-Amplitude Converter for Direct Digital Synthesizer (DDS) with Reduced AND and Reconstructed ADD Logic Arrays - A sine wave generator for a Direct Digital Synthesizer (DDS) converts a digital phase input into a digital sine wave output. Sine values and slopes are stored in read-only memory (ROM) for coarse upper phase bits in a first quadrant. A quadrant folder and phase splitter reflects and inverts values from the first quadrant to generate amplitudes for all four quadrants. Each sine value and slope is stored for a range of lower phase bits. A Delta bit separates upper and lower phase bits. Delta conditionally inverts the lower phase bits, the sine value, and the final polarity. A reduced AND logic array multiplies the slope by the conditionally inverted lower phase bits. A reconstructed ADD logic array then adds the conditionally inverted sine value. The conditionally inverted polarity is added to generate the final sine value. Sine generation logic is streamlined with conditional inversion based on the Delta bit. | 08-07-2014 |
20140376135 | Electro-Static-Discharge (ESD) Protection Structure With Stacked Implant Junction Transistor and Parallel Resistor and Diode Paths to Lower Trigger Voltage and Raise Holding Volatge - An electro-static-discharge (ESD) protection circuit has a vertical NPN transistor with a floating p-type base created by a deep p-type implant under an N+ source region. The deep p-type implant may be an ESD implant in a standard CMOS process. The p-type implant provides a low initial snap-back trigger voltage, but the holding voltage may be too low, creating latch-up problems. The holding voltage is raised by about one volt by connecting the emitter of the vertical NPN transistor to parallel resistor and diode paths. When the vertical NPN transistor is triggered, its current initially flows through the resistor, creating an increasing voltage drop through the resistor as current rises. Once the voltage across the resistor reaches 0.5 volt, the diode in parallel with the resistor becomes forward biased and shunts a higher current than the resistor, raising the holding voltage. A clamp transistor may replace the diode. | 12-25-2014 |
Xuan Huo, Toronto CA
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20120096956 | PHOTONIC CRYSTAL PRESSURE SENSOR - The present invention provides a microscale pressure sensor that exhibits high sensitivity in a small form factor. The sensor is a bridged device in which a photonic crystal waveguide, surrounded by a photonic crystal slab, is suspended over a dielectric substrate. Under applied pressure, the photonic crystal waveguide is deflected toward the substrate, causing a decrease in optical transmission across the waveguide due to the coupling of the evanescent field of the guided mode to the dielectric substrate. In a preferred embodiment, the waveguide is coupled to a photonic crystal microcavity, which increases evanescent coupling. | 04-26-2012 |
Yan Jenny Huo, Hong Kong HK
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20090092328 | METHOD FOR MOTION COMPENSATION - A method for use in video compression is disclosed. In particular, the claimed invention relates to a method of more efficient fractional-pixel interpolation in two steps by a fixed filter ( | 04-09-2009 |
Zhu Dong Huo, Keelung City TW
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20110318966 | Electrical Connector and Conductive Member Thereof - An electrical connector and a conductive member thereof are provided. In one embodiment of the present invention, the conductive member is installed in an insulating body, and a solder ball is retained between two retaining ends of the conductive member to form the electrical connector. In the conductive member, a base extends downwards to form two soldering arms, each of the soldering arms has an extending arm and a retaining end extending from the extending arm, the retaining ends are exposed outside the insulating body, and at least one of the retaining ends is provided with a recessed portion, so as to enable the solder ball, when entering between the two retaining ends, to prop the two retaining ends and partially enter the recessed portion, so that the solder ball is securely retained by the two retaining ends, thereby preventing the solder ball from falling off from the two retaining ends when the electrical connector is under an external force. | 12-29-2011 |
20120058691 | ELECTRICAL CONNECTOR - An electrical connector includes an insulating body, having at least one receiving housing running through the insulating body; at least one conductive member, comprising a contact portion disposed in the receiving housings, and has a middle part higher than two ends; a pair of first retaining arms, extending downwards from one end of the contact portion, wherein a retaining hole is formed between the two arms, and each of the two arms has a hook portion extending towards the retaining hole; a second retaining arm, extending downwards from the other end of the contact portion, wherein the second retaining arm extends towards the retaining hole, and has a width smaller than the retaining hole; and at least one solder ball, disposed in the receiving housing, received in the retaining hole, and pressed against by the two hook portions of the two first retaining arms and the second retaining arm. | 03-08-2012 |