Patent application number | Description | Published |
20100199000 | DATA STORAGE DEVICE AND METHOD FOR OPERATING THE SAME - A data storage device including a main body and a storage element is provided. The main body has a first connecting part and a second connecting part, suitable for being connected to a first electronic device and a second electronic device, respectively. The storage element is disposed at the main body and is electrically connected to the first connecting part and the second connecting part, wherein the data storage device is suitable for receiving data from the first electronic device, and the data is stored in the storage element, or is transmitted to the second electronic device, or the data is stored in the storage element and is transmitted to the second electronic device. In addition, an operating method of the data storage device is also provided. | 08-05-2010 |
20100240310 | EARPIECE - The invention provides an earpiece. The earpiece includes a main body and a speaker disposed in the main body. The main body includes a sound output member and a bending member connected to the sound output member, wherein the sound output member and the bending member are integrally formed as a single piece. | 09-23-2010 |
20100302108 | MOBILE COMMUNICATION DEVICE - A mobile communication device including a first appearance and an antenna is provided. An upper surface of the first appearance is bent a first angle from a border between a display area and a non-display area toward a display direction, and a lower surface of the first appearance is bent a second angle from a bending point toward the display direction, wherein the bending point of the lower surface is corresponding to the display area of the upper surface. The antenna is disposed in the mobile communication device and corresponding to the non-display area of the first appearance. The antenna transmits and receives signals processed by the mobile communication device. | 12-02-2010 |
20130314349 | METHOD FOR CONTROLLING DISPLAY OF ELECTRONIC DEVICE AND ELECTRONIC DEVICE USING THE SAME - A method for controlling a display of an electronic device is proposed along with the electronic device using the same. The electronic device has the display and a touch sensor disposed on the display. The method includes the following steps. The touch sensor is driven when the display is not driven to display an image. A sensing signal is received from the touch sensor. First information is determined based on the sensing signal. The first information is compared with first predetermined information. The display is driven to display the image when the first information matches the predetermined information. | 11-28-2013 |
20130321313 | METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR CROPPING SCREEN FRAME - A screen frame cropping method, a screen frame cropping apparatus, and a computer program product adapted to an electronic apparatus having a touch screen are provided. In the screen frame cropping method, a frame is displayed on the touch screen, and a first touch and a second touch preformed by a user on the touch screen are detected. When the first touch and the second touch satisfy a predetermined condition, a cropped frame of the frame is stored as an image file. The cropped frame is determined according to at least one first touch position of the first touch and at least one second touch position of the second touch. | 12-05-2013 |
Patent application number | Description | Published |
20120119228 | LED DEVICE WITH IMPROVED THERMAL PERFORMANCE - An apparatus includes a wafer with a number of openings therein. For each opening, an LED device is coupled to a conductive carrier and the wafer in a manner so that each of the coupled LED device and a portion of the conductive carrier at least partially fill the opening. A method of fabricating an LED device includes forming a number of openings in a wafer. The method also includes coupling light-emitting diode (LED) devices to conductive carriers. The LED devices with conductive carriers at least partially fill each of the openings. | 05-17-2012 |
20120129282 | WAFER LEVEL CONFORMAL COATING FOR LED DEVICES - Provided is a method of fabricating a light-emitting diode (LED) device. The method includes providing a wafer. The wafer has light-emitting diode (LED) devices formed thereon. The method includes immersing the wafer into a polymer solution that has a surface tension lower than that of acetic acid. The polymer solution contains a liquid polymer and phosphor particles. The method includes lifting the wafer out of the polymer solution at a substantially constant speed. The method includes drying the wafer. The above processes form a conformal coating layer at least partially around the LED devices. The coating layer includes the phosphor particles. The coating layer also has a substantially uniform thickness. | 05-24-2012 |
20120205694 | METHOD OF FORMING A LIGHT EMITTING DIODE EMITTER SUBSTRATE WITH HIGHLY REFLECTIVE METAL BONDING - The present disclosure provides one embodiment of a method for fabricating a light emitting diode (LED) package. The method includes forming a plurality of through silicon vias (TSVs) on a silicon substrate; depositing a dielectric layer over a first side and a second side of the silicon substrate and over sidewall surfaces of the TSVs; forming a metal layer patterned over the dielectric layer on the first side and the second side of the silicon substrate and further filling the TSVs; and forming a plurality of highly reflective bonding pads over the metal layer on the second side of the silicon substrate for LED bonding and wire bonding. | 08-16-2012 |
20120228650 | Light Emitting Diode Emitter Substrate with Highly Reflective Metal Bonding - The present disclosure provides one embodiment of a method for fabricating a light emitting diode (LED) package. The method includes forming a plurality of through silicon vias (TSVs) on a silicon substrate; depositing a dielectric layer over a first side and a second side of the silicon substrate and over sidewall surfaces of the TSVs; forming a metal layer patterned over the dielectric layer on the first side and the second side of the silicon substrate and further filling the TSVs; and forming a plurality of highly reflective bonding pads over the metal layer on the second side of the silicon substrate for LED bonding and wire bonding. | 09-13-2012 |
20120264296 | METHODS OF FORMING THROUGH SILICON VIA OPENINGS - A method of forming a through-silicon-via (TSV) opening includes forming a TSV opening through a substrate. A recast of a material of the substrate on sidewalls of the TSV opening is removed with a first chemical. The sidewalls of the TSV opening are cleaned with a second chemical by substantially removing a residue of the first chemical. | 10-18-2012 |
20120286240 | Methods of Fabricating Light Emitting Diode Packages - An LED array comprises a growth substrate and at least two separated LED dies grown over the growth substrate. Each of LED dies sequentially comprise a first conductive type doped layer, a multiple quantum well layer and a second conductive type doped layer. The LED array is bonded to a carrier substrate. Each of separated LED dies on the LED array is simultaneously bonded to the carrier substrate. The second conductive type doped layer of each of separated LED dies is proximate to the carrier substrate. The first conductive type doped layer of each of LED dies is exposed. A patterned isolation layer is formed over each of LED dies and the carrier substrate. Conductive interconnects are formed over the patterned isolation layer to electrically connect the at least separated LED dies and each of LED dies to the carrier substrate. | 11-15-2012 |
20120326198 | LED STRUCTURE - A light emitting diode (LED) structure comprises a first dopant region, a dielectric layer on top of the first dopant region, a bond pad layer on top of a first portion the dielectric layer, and an LED layer having a first LED region and a second LED region. The bond pad layer is electrically connected to the first dopant region. The first LED region is electrically connected to the bond pad layer. | 12-27-2012 |
20130020589 | WAFER LEVEL PHOTONIC DEVICE DIE STRUCTURE AND METHOD OF MAKING THE SAME - A vertical Light Emitting Diode (LED) device includes an epi structure with a first-type-doped portion, a second-type-doped portion, and a quantum well structure between the first-type-doped and second-type-doped portions and a carrier structure with a plurality of conductive contact pads in electrical contact with the epi structure and a plurality of bonding pads on a side of the carrier structure distal the epi structure, in which the conductive contact pads are in electrical communication with the bonding pads using at least one of vias and a Redistribution Layer (RDL). The vertical LED device further includes a first insulating film on a side of the carrier structure proximal the epi structure and a second insulating film on a side of the carrier structure distal the epi structure. | 01-24-2013 |
20130089937 | METHOD AND APPARATUS FOR ACCURATE DIE-TO-WAFER BONDING - A method of light-emitting diode (LED) packaging includes coupling a number of LED dies to corresponding bonding pads on a sub-mount. A mold apparatus having concave recesses housing LED dies is placed over the sub-mount. The sub-mount, the LED dies, and the mold apparatus are heated in a thermal reflow process to bond the LED dies to the bonding pads. Each recess substantially restricts shifting of the LED die with respect to the bonding pad during the heating. | 04-11-2013 |
20130241683 | Inductor for Post Passivation Interconnect - An inductor device and method of forming the inductor device are provided. In some embodiments the inductor device includes a post passivation interconnect (PPI) layer disposed and an under bump metallization (UBM) layer, each disposed over a substrate. The PPI layer forms a coil and dummy pads. The dummy pads are disposed around a substantial portion of the coil to shield the coil from electromagnetic interference. A first portion of the UBM layer is electrically coupled to the coil and configured to interface with an electrical coupling member. | 09-19-2013 |
20130332092 | Calibration Kits for RF Passive Devices - A method includes measuring a first calibration kit in a wafer to obtain a first performance data. The wafer includes a substrate, and a plurality of dielectric layers over the substrate. The first calibration kit includes a first passive device over the plurality of dielectric layers, wherein substantially no metal feature is disposed in the plurality of dielectric layers and overlapped by the first passive device. The method further includes measuring a second calibration kit in the wafer to obtain a second performance data. The second calibration kit includes a second passive device identical to the first device and over the plurality of dielectric layers, and dummy patterns in the plurality of dielectric layers and overlapped by the second passive device. The first performance data and the second performance data are de-embedded to determine an effect of metal patterns in the plurality of dielectric layers to overlying passive devices. | 12-12-2013 |
20140061688 | LED Structure - A light emitting diode (LED) structure comprises a first dopant region, a dielectric layer on top of the first dopant region, a bond pad layer on top of a first portion the dielectric layer, and an LED layer having a first LED region and a second LED region. The bond pad layer is electrically connected to the first dopant region. The first LED region is electrically connected to the bond pad layer. | 03-06-2014 |
20140065741 | Method and Apparatus for Accurate Die-to-Wafer Bonding - A method of light-emitting diode (LED) packaging includes coupling a number of LED dies to corresponding bonding pads on a sub-mount. A mold apparatus having concave recesses housing LED dies is placed over the sub-mount. The sub-mount, the LED dies, and the mold apparatus are heated in a thermal reflow process to bond the LED dies to the bonding pads. Each recess substantially restricts shifting of the LED die with respect to the bonding pad during the heating. | 03-06-2014 |
20140084244 | Wafer Level Photonic Device Die Structure and Method of Making the Same - A vertical Light Emitting Diode (LED) device includes an epi structure with a first-type-doped portion, a second-type-doped portion, and a quantum well structure between the first-type-doped and second-type-doped portions and a carrier structure with a plurality of conductive contact pads in electrical contact with the epi structure and a plurality of bonding pads on a side of the carrier structure distal the epi structure, in which the conductive contact pads are in electrical communication with the bonding pads using at least one of vias and a Redistribution Layer (RDL). The vertical LED device further includes a first insulating film on a side of the carrier structure proximal the epi structure and a second insulating film on a side of the carrier structure distal the epi structure. | 03-27-2014 |
20140145346 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first functional region of an integrated circuit over a workpiece, and forming a second functional region of the integrated circuit over the workpiece. The method includes forming a guard ring around the first functional region of the integrated circuit. The guard ring is formed in a material layer disposed over the first functional region and the second functional region. | 05-29-2014 |
20140183690 | Guard Ring Design for Maintaining Signal Integrity - A structure includes a metal feature, and a passivation layer having a portion overlapping the metal feature. The passivation layer includes a non-low-k dielectric material. A polymer layer is over the passivation layer. A Post-Passivation Interconnect (PPI) extends into the polymer layer to electrically couple to the metal feature. A guard ring includes a second PPI, wherein the guard ring is electrically grounded. The second PPI substantially encircles the first PPI. | 07-03-2014 |
20140183693 | Capacitor in Post-Passivation Structures and Methods of Forming the Same - A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer. | 07-03-2014 |
20140235053 | Methods of Forming Through Silicon Via Openings - A method of forming a through-silicon-via (TSV) opening includes forming a TSV opening through a substrate. A recast of a material of the substrate on sidewalls of the TSV opening is removed with a first chemical. The sidewalls of the TSV opening are cleaned with a second chemical by substantially removing a residue of the first chemical. | 08-21-2014 |
20140239323 | Method and Apparatus for Accurate Die-to-Wafer Bonding - A plurality of conductive pads are disposed on a substrate. A plurality of semiconductor dies are each disposed on a respective one of the conductive pads. A mold device is positioned over the substrate. The mold device contains a plurality of recesses that are each configured to accommodate a respective one of the semiconductor dies underneath. | 08-28-2014 |
20140264735 | Inductor System and Method - A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors. For example, a two turn inductor and a three turn inductor may share masks for interconnects and coils, while only masks necessary for connections between the interconnects and coils may need to be newly developed. | 09-18-2014 |
20140264927 | Single Mask Package Apparatus and Method - Disclosed herein is a single mask package apparatus on a device comprising a first substrate having a land disposed on a first surface, a stud disposed on the land and a protective layer disposed over the first surface of the first substrate and around the stud. The protective layer may optionally have a thickness of at least 3 μm. A PPI may be disposed over the protective layer and in electrical contact with the stud, with a first portion of the PPI extending laterally from the stud. An interconnect may be disposed on and in electrical contact with the first portion of the PPI, and a second substrate mounted on the interconnect. A molding compound may be disposed over the PPI and around the interconnect. The stud may be a substantially solid material having a cylindrical cross section and may optionally be wirebonded to the land. | 09-18-2014 |
20140266542 | Programmable Inductor - A system and method for providing and programming a programmable inductor is provided. The structure of the programmable inductor includes multiple turns, with programmable interconnects incorporated at various points around the turns to provide a desired isolation of the turns during programming. In an embodiment the programming may be controlled using the size of the vias, the number of vias, or the shapes of the interconnects. | 09-18-2014 |
20140339579 | LED Structure - A light emitting diode (LED) structure comprises a first dopant region, a dielectric layer on top of the first dopant region, a bond pad layer on top of a first portion the dielectric layer, and an LED layer having a first LED region and a second LED region. The bond pad layer is electrically connected to the first dopant region. The first LED region is electrically connected to the bond pad layer. | 11-20-2014 |
20150017778 | Capacitor in Post-Passivation Structures and Methods of Forming the Same - A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer. | 01-15-2015 |
20150123267 | PACKAGED SEMICONDUCTOR DEVICE - A semiconductor device with an under-bump metallurgy (UBM) over a dielectric is provided. The UBM has a trench configured to be offset from a central point of the UBM. A distance between a center of the trench to an edge of the UBM is larger than a distance between the center of the trench to an opposite edge of the UBM. A probe pin is configured to contact the UBM and collect measurement data. | 05-07-2015 |
20150137355 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first substrate including a surface, and a pad array on the surface of the substrate, wherein the pad array comprises a first type pad and a second type pad located on a same level. The semiconductor device further includes a conductive bump connecting either the first type pad or the second type pad to a second substrate and a via connected a conductive feature at a different level to the first type pad and the via located within a projection area of the first type pad and directly contacting the first type pad. The semiconductor device also has a dielectric in the substrate and directly contacting the second type pad, wherein the second type pad is floated on the dielectric. | 05-21-2015 |
Patent application number | Description | Published |
20100136579 | BIOMARKERS USEFUL IN LIVER FIBROSIS DIAGNOSIS - Identification of urokinase-type plasminogen, matrix metalloproteinase 9, and β-2-microglobulin as novel biomarkers associated with liver fibrosis and uses thereof in diagnosing liver fibrosis. | 06-03-2010 |
20110079077 | Urine and Serum Biomarkers Associated with Diabetic Nephropathy - Use of urine and serum biomarkers in diagnosing diabetic nephropathy, staging diabetic nephropathy, monitoring diabetic nephropathy progress, and assessing efficacy of diabetic nephropathy treatments. These biomarkers include urine precursor alpha-2-HS-glycoprotein, urine alpha-1 antitrypsin, urine alpha-1 acid glycoprotein, urine osteopontin, serum osteopontin, their fragments, and combinations thereof. | 04-07-2011 |
20110086371 | URINE AND SERUM BIOMARKERS ASSOCIATED WITH DIABETIC NEPHROPATHY - Use of urine and serum biomarkers in diagnosing diabetic nephropathy, staging diabetic nephropathy, monitoring diabetic nephropathy progress, and assessing efficacy of diabetic nephropathy treatments. These biomarkers include urine precursor alpha-2-HS-glycoprotein, urine alpha-1 antitrypsin, urine alpha-1 acid glycoprotein, urine osteopontin, serum osteopontin, their fragments, and combinations thereof. | 04-14-2011 |
20130252267 | URINE AND SERUM BIOMARKERS ASSOCIATED WITH DIABETIC NEPHROPATHY - Described are uses of urine and serum biomarkers in diagnosing diabetic nephropathy, staging diabetic nephropathy, monitoring diabetic nephropathy progress, and assessing efficacy of diabetic nephropathy treatments. These biomarkers include urine precursor alpha-2-HS-glycoprotein, urine alpha-1 antitrypsin, urine alpha-1 acid glycoprotein, urine osteopontin, serum osteopontin, their fragments, and combinations thereof. | 09-26-2013 |
Patent application number | Description | Published |
20100242008 | METHOD FOR DUMMY METAL AND DUMMY VIA INSERTION - A method for dummy metal and dummy via insertion is provided. In one embodiment, dummy metals are inserted using a place and route tool, where the place and route tool has timing-awareness. Then, dummy vias arrays are inserted inside an overlap area of dummy metals using a design-rule-checking utility. Fine-grained dummy vias arrays are inserted in available space far away from main patterns. The dummy-patterns resulting from the inserted dummy vias are compressed using the design-rule-checking utility to reduce the size of a graphic data system file generated from the integrated circuit design. The dummy vias can be inserted with relaxed via spacing rules. The dummy metals are inserted with a constant line-end spacing between them for better process control and the maximum length of the dummy metal can be limited for smaller coupling effects. The dummy vias can have various sizes and a square or rectangular shape. | 09-23-2010 |
20110083115 | ROBUST METHOD FOR INTEGRATION OF BUMP CELLS IN SEMICONDUCTOR DEVICE DESIGN - A system and method for computer-aided design of semiconductor integrated circuit devices provides for having dummy vias beneath UBM of bump cells to prevent delamination at the bump cell sites during bonding. The dummy vias are inserted into the design and bump cell placement occurs during the floorplanning stage and prior to placement and routing of the active integrated circuit components. In this manner, a sufficiently high via density is achieved and design information on the bump cells including the dummy vias is provided to a computer-aided design, CAD, system along with program instructions for carrying out the indicated sequence of design operations. | 04-07-2011 |
20130097571 | METHOD FOR DUMMY METAL AND DUMMY VIA INSERTION - A method of inserting dummy metal and dummy via in an integrated circuit design. The method includes inserting, by a computer, dummy metals using a place and route tool, wherein the place and route tool has timing-awareness to improve a timing performance of the integrated circuit design. The method further includes inserting, by the computer, dummy vias using a design-rule-checking utility separately from the inserting of the dummy metals, wherein at least one of the dummy vias has a different size than at least another of the dummy vias. | 04-18-2013 |
20140137060 | METHOD FOR DUMMY METAL AND DUMMY VIA INSERTION - A method of inserting dummy metal and dummy via in an integrated circuit design includes inserting, by a computer, dummy metals using a place and route tool, wherein the place and route tool has timing-awareness to improve a timing performance of the integrated circuit design, and the dummy metals have a length less than or equal to a predetermined maximum length. The method further includes inserting, by the computer, dummy vias using a design-rule-checking utility separately from the inserting of the dummy metals. | 05-15-2014 |
Patent application number | Description | Published |
20120092828 | SERVER CABINET AND SERVER STRUCTURE USING THE SAME - A server structure is disclosed including a server cabinet, spaced fixing units, and server groups. Each server unit includes a first server unit and a second server unit fixed to supporting frames of the server cabinet by first fixing plates and the second fixing plates of the fixing units, respectively. The first server unit alternately abuts the second server unit, and the stacked height of each first server unit and the abutting second server unit is equivalent to the height along the supporting frame occupied by the corresponding fixing unit. | 04-19-2012 |
20130242503 | APPARATUS FOR RECEIVING SERVERS - An apparatus includes a server cabinet configured to receive a plurality of servers therein, and a single heat dissipation device mounted on the server cabinet and positioned outside of the plurality of servers. The heat dissipation device includes a plurality of fans, and each of the plurality of fans is configured to dissipate heat generated in the overall server cabinet. | 09-19-2013 |
20140005977 | COMPUTER AND OBJECT TOLERANCE CALCULATION METHOD | 01-02-2014 |
20140055934 | SERVER - A 2 unit (U) server includes a 2U chassis, two system modules, and two power supply units. The chassis includes a bottom plate, two side plates, a cover, and a middle plate arranged between the side plates in parallel. A supporting plate is connected between rear ends of the middle plate and each side plate. A distance between each supporting plate and the cover, and a distance between each supporting plate and the bottom plate is the same, being equal to 1U. A space between the middle plate and each side plate receives one of the system modules. A height of a front end of each system module is 2U. A height of a rear end of each system module is 1U. The rear end of each system module is received between the bottom plate and one of the supporting plates. Each supporting plate supports a power supply unit. | 02-27-2014 |
20140106620 | CONNECTOR ASSEMBLY - A connector assembly includes a female connector and a mal connector. The female connector includes a first main body and a number of slots defined in the first main body, and each slot receives a conductive terminal therein. First and second row conductive terminals are arranged along an opposite direction. A number of cables are attached to the first main body and electrically connected to the conductive terminals. A male connector includes a second main body and a number of conductive pins extend through the second main body. Third row conductive pins are corresponding to the first row conductive terminals. Fourth row conductive pins are corresponding to the second row conductive terminals. The connector assembly can transmit signals normally whatever the male connector is plugged to the female connector. | 04-17-2014 |
20140153187 | RACK-MOUNT SERVER ASSEMBLY WITH CABLE MANAGEMENT APPARATUS - A rack-mount server assembly includes a rack, server modules, and a cable management apparatus. The rack includes a support pole defining a number of through holes arrayed a row along a lengthwise direction of the support pole. The cable management apparatus includes a bracket, a number of cable binding members, and a number of cable positioning members. The bracket includes an installing plate mounted on an outer side surface of the rack adjacent to the support pole, a rear side plate, and an extending plate extending from the rear side plate. The cable binding members are attached to an outer surface of the installing plate. The cable positioning members are mounted on an outer surface of the extending plate. Cables of the server modules are extended through the through holes and are respectively clamped in the cable positioning members, and are then bound by the cable binding members. | 06-05-2014 |
20150093933 | FIXING DEVICE FOR TWO CONNECTED CONNECTORS - A fixing device for fixing two connectors connected to each other includes two holding members and a connecting member connected between the holding members. Each holding member includes a connecting piece and two arms extending down from opposite ends of the connecting piece to sandwich one of the connectors. | 04-02-2015 |