Patent application number | Description | Published |
20100090256 | SEMICONDUCTOR STRUCTURE WITH STRESS REGIONS - A semiconductor structure with stress regions includes a substrate defining a first and a second device zone; a first and a second stress region formed in each of the first and second device zones to yield stress different in level; and a barrier plug separating the two device zones from each other. Due to the stress yielded at the stress regions, increased carrier mobility and accordingly, increased reading current can be obtained, and a relatively lower reading voltage is needed to obtain initially required reading current. As a result, the probability of stress-induced leakage current (SILC) is reduced and the semiconductor memory structure may have enhanced data retention ability. | 04-15-2010 |
20100227447 | METHOD OF MANUFACTURING FLASH MEMORY DEVICE - A flash memory device manufacturing process includes the steps of providing a semiconductor substrate; forming two gate structures on the substrate; performing an ion implantation process to form two first source regions in the substrate at two lateral outer sides of the two gate structures; performing a further ion implantation process to form a first drain region in the substrate between the two gate structures; performing a pocket implantation process between the gate structures to form two doped regions in the substrate at two opposite sides of the first drain region; forming two facing L-shaped spacer walls between the two gate structures above the first drain region; performing an ion implantation process to form a second drain region beneath the first drain region, both of which having a steep junction profile compared to the first source regions; and forming a barrier plug above the first drain region. | 09-09-2010 |
20110230028 | MANUFACTURING METHOD OF STRAIGHT WORD LINE NOR TYPE FLASH MEMORY ARRAY - In a manufacturing method of a straight word line NOR flash memory array, a source line is implanted after the formation of a word line in the NOR type flash memory array is completed, and a discrete implant region is formed in the NOR type flash memory array and parallel to a component isolation structure, and each discrete implant region constitutes an electric connection with a low impedance between a source line and source contacts on the source line. With such discrete distribution, adjacent memory cells will not be short-circuited or failed even if a deviation of a mash occurs during the manufacturing process. | 09-22-2011 |
20130171815 | MANUFACTURING METHOD OF FLASH MEMORY STRUCTURE WITH STRESS AREA - In a manufacturing method of a flash memory structure with a stress area, a better stress effect can be achieved by controlling the manufacturing process of a tunneling oxide layer formed in a gate structure and contacted with a silicon substrate, so that an L-shaped spacer (or a first stress area) and a contact etch stop layer (or a second stress area) of each L-shaped spacer are formed between two gate structures and aligned towards each other to enhance the carrier mobility of the gate structure, so as to achieve the effects of improving a read current, obtaining the required read current by using a lower read voltage, reducing the possibility of having a stress-induced leakage current, and enhancing the data preservation of the flash memory. | 07-04-2013 |
Patent application number | Description | Published |
20080277735 | MOS devices having elevated source/drain regions - A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a deep source/drain region adjacent the gate electrode; a silicide region over the deep source/drain region; and an elevated metallized source/drain region between the silicide region and the gate electrode. The elevated metallized source/drain region adjoins the silicide region. | 11-13-2008 |
20090140351 | MOS Devices Having Elevated Source/Drain Regions - A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming a slim spacer on sidewalls of the gate dielectric and the gate electrode; forming a silicon carbon (SiC) region adjacent the slim spacer; forming a deep source/drain region comprising at least a portion of the silicon carbon region; blanket forming a metal layer, wherein a first interface between the metal layer and the deep source/drain is higher than a second interface between the gate dielectric and the semiconductor substrate; and annealing the semiconductor device to form a silicide region. Preferably, a horizontal spacing between an inner edge of the silicide region and a respective edge of the gate electrode is preferably less than about 150 Å. | 06-04-2009 |
20100065893 | SEMICONDUCTOR MEMORY STRUCTURE WITH STRESS REGIONS - A semiconductor memory structure with stress regions includes a substrate defining a first and a second device zone; a first and a second stress region formed in each of the first and second device zone to yield stress different in level; a barrier plug separating the two device zones from each other; and a plurality of oxide spacers being located between the first stress regions and the barrier plug while in direct contact with the first stress regions. Due to the stress yielded at the stress regions, increased carrier mobility and accordingly, increased reading current can be obtained, and only a relatively lower reading voltage is needed to obtain an initially required reading current. As a result, the probability of stress-induced leakage current is reduced to enhance the data retention ability. | 03-18-2010 |
20110223727 | CMOS Devices with Schottky Source and Drain Regions - A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device is reduced by forming the PMOS device over a semiconductor layer having a low valence band. | 09-15-2011 |
20140094008 | CMOS Devices with Schottky Source and Drain Regions - A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device is reduced by forming the PMOS device over a semiconductor layer having a low valence band. | 04-03-2014 |
Patent application number | Description | Published |
20080224225 | MOS transistors with selectively strained channels - The channels of first and second CMOS transistors can be selectively stressed. A gate structure of the first transistor includes a stressor that produces stress in the channel of the first transistor. A gate structure of the second transistor is disposed in contact with a layer of material that produces stress in the channel of the second transistor. | 09-18-2008 |
20080224227 | BiCMOS performance enhancement by mechanical uniaxial strain and methods of manufacture - A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT. | 09-18-2008 |
20090117695 | BiCMOS Performance Enhancement by Mechanical Uniaxial Strain and Methods of Manufacture - A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT. | 05-07-2009 |
Patent application number | Description | Published |
20120293364 | POSITIONING DEVICE AND POSITIONING METHOD THEREOF - A positioning device and a positioning method thereof are provided. The positioning device can cooperate with a first satellite group and a second satellite group, and it comprises a storage, a receiver and a processor. The receiver is configured to receive a first satellite group signal from the first satellite group and a second satellite group signal from the second satellite group. The processor is electrically connected to the storage and the receiver, and configured to calculate a positioning offset value according to one of the first satellite group signal and the second satellite group signal. In addition, the processor is configured to calculate a positioning result according to the second satellite group signal and the positioning offset, and store the positioning result in the storage. | 11-22-2012 |
20130119302 | HEAT TRANSFER ENHANCING AGENT - An enhancing agent for increasing heat transfer efficiency is disclosed, which is an additive composed of a nano-scale powder and a micro-scale powder that is to be added into a heat-transfer fluid circulating in an heat exchange system or in a coolant circulating in a cooling system for enhancing the heat conductivity of the heat-transfer fluid or the coolant while helping the tank and the fluid passages used in those systems to maintain clean, and eventually enabling those systems to operate with improved heat dissipation effect. By adding the aforesaid enhancing agent into a cooling system of an internal-combustion engine, the heat shock inside the engine that is originated from the fuel burning in the engine can be reduced, resulting that not only the amount of green house gas emission is reduced, but also the chance of engine juddering that is generally originated from poor heat dissipation can be decreased. | 05-16-2013 |
20140040150 | LOG-IN METHOD FOR PRODUCT AND APPLICATION PROGRAM THEREOF - A log-in method for a product and an application program thereof applies to a mobile device in order to execute the application program, the application program connects with a community website and executes a check-in procedure on the community website. When the check-in procedure is being executed, the application program obtains the product information and the sales information both related to the product and automatically fills out the information in an executing page having a check-in function. Hence, a sales end server defines check-in information, including a check-in landmark, check-in contents, a check-in time, a check-in name, etc., as the log-in information of the product, so as to execute the log-in activity of the product. | 02-06-2014 |