Patent application number | Description | Published |
20100244247 | VIA STRUCTURE AND VIA ETCHING PROCESS OF FORMING THE SAME - A via etching process forms a through-substrate via having a round corner and a tapered sidewall profile. A method includes providing a semiconductor substrate; forming a hard mask layer and a patterned photoresist layer on the semiconductor substrate; forming an opening in the hard mask and exposing a portion of the semiconductor substrate; forming a via passing through at least a part of the of semiconductor substrate using the patterned photoresist layer and hard mask layer as a masking element; performing a trimming process to round the top corner of the via; and removing the photoresist layer. | 09-30-2010 |
20110241040 | NOVEL SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIAS - The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns. | 10-06-2011 |
20110241061 | HEAT DISSIPATION BY THROUGH SILICON PLUGS - The package substrates with through silicon plugs (or vias) described above provide lateral and vertical heat dissipation pathways for semiconductor chips that require thermal management. Designs of through silicon plugs (TSPs) with high duty ratios can most effectively provide heat dissipation. TSP designs with patterns of double-sided combs can provide high duty ratios, such as equal to or greater than 50%. Package substrates with high duty ratios are useful for semiconductor chips that generate large amount of heat. An example of such semiconductor chip is a light-emitting diode (LED) chip. | 10-06-2011 |
20120007132 | REDUCTION OF ETCH MICROLOADING FOR THROUGH SILICON VIAS - The patterns (or layout), and pattern densities of TSVs described above provide layout of TSVs that could be etched with reduced etch microloading effect(s) and with good within-die uniformity. The patterns and pattern densities of TSVs for different groups of TSVs (or physically separated groups, or groups with different functions) should be fairly close amongst different groups. Different groups of TSVs (or TSVs with different functions, or physically separated TSV groups) should have relatively close shapes, sizes, and depths to allow the aspect ratio of all TSVs to be within a controlled (and optimal) range. The size(s) and depths of TSVs should be carefully selected to optimize the etching time and the metal gap-fill time. | 01-12-2012 |
20130059443 | REDUCTION OF ETCH MICROLOADING FOR THROUGH SILICON VIAS - A method of making a support structure is provided. The method includes depositing a photoresist layer on a substrate of the support structure and patterning the photoresist layer. The method further includes etching the patterned photoresist layer. Etching the patterned photoresist includes forming a first group of through silicon vias (TSVs) configured to electrically connect a first surface of the substrate to a first electrical interface adjacent an opposite second surface of the substrate. Etching the patterned photoresist further includes forming a second group of TSVs configured to conduct thermal energy from the first surface of the substrate to a thermal interface adjacent the second surface of the substrate. A difference in cross-sectional area between TSVs in the first group of TSVs and TSVs in the second group of TSVs is less than 10%, and the first electrical interface is separated from the thermal interface. | 03-07-2013 |
20130062767 | VIA STRUCTURE AND VIA ETCHING PROCESS OF FORMING THE SAME - An integrated circuit structure includes a semiconductor substrate and a hard mask layer formed on the semiconductor substrate. The integrated circuit structure further includes at least a conductive layer formed in the hard mask layer and a via extending from the hard mask layer to at least a portion of the semiconductor substrate, wherein the via has a round corner and a tapered sidewall. | 03-14-2013 |
20130087908 | BUMP WITH PROTECTION STRUCTURE - A semiconductor device includes a bump structure formed on a post-passivation interconnect (PPI) line and surrounded by a protection structure. The protection structure includes a polymer layer and at least one dielectric layer. The dielectric layer may be formed on the top surface of the polymer layer, underlying the polymer layer, inserted between the bump structure and the polymer layer, inserted between the PPI line and the polymer layer, covering the exterior sidewalls of the polymer layer, or combinations thereof. | 04-11-2013 |
20130302979 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THROUGH SILICON PLUGS - A method of making a semiconductor device, the method includes forming a first opening and a second opening in a substrate. The method further includes forming a conductive material in the first opening and in the second opening, the conductive material comprising a joined portion where the conductive material in the first opening and the conductive material in the second opening are electrically and thermally connected together at a first surface of the substrate. The method further includes reducing a thickness of the substrate from a second surface of the substrate, opposite the first surface, to expose the conductive material in the first opening and the conductive material in the second opening. The method further includes connecting a device to the second surface of the substrate. | 11-14-2013 |
20150147834 | NOVEL SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIAS - The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns. | 05-28-2015 |
Patent application number | Description | Published |
20090008794 | Thickness Indicators for Wafer Thinning - A wafer thinning system and method are disclosed that includes grinding away substrate material from a backside of a semiconductor device. A current change is detected in a grinding device responsive to exposure of a first set of device structures through the substrate material, where the grinding is stopped in response to the detected current change. Polishing repairs the surface and continues to remove an additional amount of the substrate material. Exposure of one or more additional sets of device structures through the substrate material is monitored to determine the additional amount of substrate material to remove, where the additional sets of device structures are located in the semiconductor device at a known depth different than the first set. | 01-08-2009 |
20090283871 | System, Structure, and Method of Manufacturing a Semiconductor Substrate Stack - A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside. | 11-19-2009 |
20100140805 | Bump Structure for Stacked Dies - A bump structure that may be used for stacked die configurations is provided. Through-silicon vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon vias. The isolation film is thinned to re-expose the through-silicon vias. Bump pads and redistribution lines are formed on the backside of the semiconductor substrate providing an electrical connection to the through-silicon vias. Another isolation film is deposited and patterned, and a barrier layer is formed to provide contact pads for connecting to an external device, e.g., another die/wafer or circuit board. | 06-10-2010 |
20100171197 | Isolation Structure for Stacked Dies - An isolation structure for stacked dies is provided. A through-silicon via is formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon via. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon via. The isolation film is thinned to re-expose the through-silicon via, and conductive elements are formed on the through-silicon via. The conductive element may be, for example, a solder ball or a conductive pad. The conductive pad may be formed by depositing a seed layer and an overlying mask layer. The conductive pad is formed on the exposed seed layer. Thereafter, the mask layer and the unused seed layer may be removed. | 07-08-2010 |
20110241217 | Multi-Layer Interconnect Structure for Stacked Dies - A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements. | 10-06-2011 |
20120068218 | THERMALLY EFFICIENT PACKAGING FOR A PHOTONIC DEVICE - The present disclosure provides a method of packaging for a photonic device, such as a light-emitting diode device. The packaging includes an insulating structure. The packaging includes first and second conductive structures that each extend through the insulating structure. A substantial area of a bottom surface of the light-emitting diode device is in direct contact with a top surface of the first conductive structure. A top surface of the light-emitting diode device is bonded to the second conductive structure through a bonding wire. | 03-22-2012 |
20120083116 | Cost-Effective TSV Formation - A device includes a substrate having a first surface, and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the substrate. A dielectric layer is disposed over the substrate. A metal pad is disposed in the dielectric layer and physically contacting the TSV, wherein the metal pad and the TSV are formed of a same material, and wherein no layer formed of a material different from the same material is between and spacing the TSV and the metal pad apart from each other. | 04-05-2012 |
20130001799 | Multi-Layer Interconnect Structure for Stacked Dies - A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements. | 01-03-2013 |
20130023065 | Apparatus and Methods for End Point Determination in Reactive Ion Etching - Methods and apparatus for performing end point determination. A method includes receiving a wafer into an etch tool chamber for performing an RIE etch; beginning the RIE etch to form vias in the wafer; receiving in-situ measurements of one or more physical parameters of the etch tool chamber that are correlated to the RIE etch process; providing a virtual metrology model for the RIE etch in the chamber; inputting the received in-situ measurements to the virtual metrology model for the RIE etch in the chamber; executing the virtual metrology model to estimate the current via depth; comparing the estimated current via depth to a target depth; and when the comparing indicates the current via depth is within a predetermined threshold of the target depth; outputting a stop signal. An apparatus for use with the method embodiment is disclosed. | 01-24-2013 |
20130024019 | APPARATUS AND METHODS FOR END POINT DETERMINATION IN SEMICONDUCTOR PROCESSING - Methods and apparatus for performing end point determination are disclosed. An embodiment includes an apparatus comprising a process tool and a programmable processor. The process tool has an output for signaling in-situ measurements of physical parameters during processing of a wafer in the process tool, and the process tool has an input for receiving a signal indicating a modification of a recipe for the processing. The programmable processor is for executing a virtual metrology model of the process tool to estimate an estimated characteristic of the wafer achieved during the processing. The estimated characteristic is based on the in-situ measurements and the virtual metrology model. The programmable processor has an output for transmitting the signal when the estimated characteristic exceeds a predetermined threshold based on a target characteristic. | 01-24-2013 |
20130299992 | Bump Structure for Stacked Dies - A bump structure that may be used for stacked die configurations is provided. Through-silicon vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon vias. The isolation film is thinned to re-expose the through-silicon vias. Bump pads and redistribution lines are formed on the backside of the semiconductor substrate providing an electrical connection to the through-silicon vias. Another isolation film is deposited and patterned, and a barrier layer is formed to provide contact pads for connecting to an external device, e.g., another die/wafer or circuit board. | 11-14-2013 |
20140232013 | Backside Through Vias in a Bonded Structure - A wafer thinning system and method are disclosed that includes grinding away substrate material from a backside of a semiconductor device. A current change is detected in a grinding device responsive to exposure of a first set of device structures through the substrate material, where the grinding is stopped in response to the detected current change. Polishing repairs the surface and continues to remove an additional amount of the substrate material. Exposure of one or more additional sets of device structures through the substrate material is monitored to determine the additional amount of substrate material to remove, where the additional sets of device structures are located in the semiconductor device at a known depth different than the first set. | 08-21-2014 |
20150024546 | System, Structure, and Method of Manufacturing a Semiconductor Substrate Stack - A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside. | 01-22-2015 |
20160071765 | Through Via Structure and Method - A device comprises a via in a substrate comprising a lower via portion with a first width formed of a first conductive material and an upper via portion with a second width greater than the first width, wherein the upper via portion comprises a protection layer formed of the first conductive material and a via fill material portion formed of a second conductive material. | 03-10-2016 |
Patent application number | Description | Published |
20140092628 | ILLUMINATION DEVICE - An illumination device including a light guiding element, a light emitting element, and a reflective element is provided. The light guiding element has a light incident surface, a light emitting surface, a first surface and a second surface. The light incident surface surrounds the light guiding element and is connected between the light emitting surface and the first surface. The first surface is connected between the light incident surface and the second surface so that the second surface is substantially opposite to the light incident surface. The second surface constructs a depression structure having a diameter gradually changed from the first surface towards the light emitting surface. The light emitting element surrounds the light guiding element to emit a light towards the light incident surface. The reflective element is disposed at least on the first surface. | 04-03-2014 |
20140160743 | LIGHT TUBE - A light tube includes a tube body, at least one light emitting diode, and a transparent cover. The light emitting diode is assembled with the tube body. The transparent cover is disposed on the tube body to cover the light emitting diode and has a roof portion and two side arm portions. A first microstructure region and a second microstructure region are formed on a surface of the roof portion corresponding to the light emitting diode. The second microstructure region extends from two ends of the first microstructure region. A third microstructure region is formed on a surface of each side arm portion corresponding to the light emitting diode. A microstructure density of the second microstructure region is less than or equal to a microstructure density of the first microstructure region, and is greater than or equal to a microstructure density of the third microstructure region. | 06-12-2014 |
20140198496 | ILLUMINATION APPARATUS - An illumination apparatus includes a transparent case, an opaque member, a ring-shaped light emitting device, and a ring-shaped transparent cover. The transparent case has a central region. The opaque member is disposed on the central region. The ring-shaped light emitting device is disposed in the transparent case corresponding to the central region. The ring-shaped transparent cover is disposed on the ring-shaped light emitting device and has a first arc-shaped ring portion relatively close to the opaque member and a second arc-shaped ring portion relatively away from the opaque member. A refraction microstructure region is formed on an inner surface of the first arc-shaped ring portion for refracting light emitted by the ring-shaped light emitting device. | 07-17-2014 |
20150036352 | LIGHT EMITTING DIODE LAMP AND DIFFUSING CAP THEREOF - A light emitting diode (LED) lamp is provided. The LED lamp includes a circuit board, at least one LED, a diffusing cap and a heat sink structure. The LED is disposed on the circuit board for emitting a light. The diffusing cap covers the LED and the circuit board. The diffusing cap includes an outer emitting portion and a lateral emitting portion. The outer emitting portion has a concave. The lateral emitting portion is connected to the outer emitting portion. The concave is used for reflecting part of the light toward a lateral surface of the lateral emitting portion. The heat sink structure is disposed below the circuit board for dissipating a heat generated from the LED and the circuit board. | 02-05-2015 |
Patent application number | Description | Published |
20090240862 | System Design for a Digital Electronic Sign Board - A system design for a digital electronic sign board comprises a main circuit module, an adapter module and a computer module; wherein the adapter module is fixed between the main circuit module and the computer module. The main circuit module and the adapter module are fixed in the digital electronic sign board. The computer module is externally inserted into the digital electronic sign board. Therefore the computer module and the main circuit module are electrically connected through the adapter module. The system design of the present invention removable and attached the computer module with the main circuit module. As a result, when a maintenance worker needs to perform maintenance on the computer module, he or she can conveniently pull out the computer module from the digital electronic sign board and insert the computer module back to the digital electronic sign board after maintenance is done so as to improve the efficiency and quality of maintenance. | 09-24-2009 |
20110250414 | TCO COATING WITH A SURFACE PLASMA RESONANCE EFFECT AND MANUFACTURING METHOD THEREOF - A novel TCO coating and its manufacturing method are disclosed. The TCO coating of the present invention consists of titanium oxide, silicon oxide and metal. The TCO coating is manufactured according to electromagnetic field simulation software basing on the Maxwell Equations. Because the manufacturing method (including steam plating and sputter plating) of the present invention may be carried out under the room temperature, base boards that are made of polymer and that can not withstand high temperatures may be used and hence base boards may have wider applications. Also, less time is needed in the production, production cost is lowered and mass-production may be achieved. | 10-13-2011 |
20120081853 | MEDICAL ANTIBACTERIAL FULL-FLAT TOUCH SCREEN - A medical antibacterial full-flat touch screen comprises an antibacterial housing, an antibacterial rubber strip and an antibacterial full-flat panel, wherein a recessed edge is configured around the periphery at the bottom of the antibacterial rubber strip which recessed edge encompassing the periphery of the antibacterial full-flat panel, and a plurality of upright buckle holes are configured on the inner side of the periphery of the antibacterial full-flat panel. In addition, a groove is configured around the periphery at the top of the antibacterial rubber strip such that the antibacterial housing can be directly inserted into the groove, and a plurality of bumps configured on the inner side of the antibacterial housing can be positioned into the upright buckle holes thereby allowing the antibacterial housing and the antibacterial full-flat panel to combine together. Furthermore, the antibacterial rubber strip closely joined between the antibacterial housing and the antibacterial full-flat panel can effectively prevent the breeding of bacteria inside the gap of the assembled body and the infiltration of any liquid into the body as well. | 04-05-2012 |
20120084728 | BUTTON CONTROL SYSTEM FOR MEDICAL TOUCH SCREEN AND METHOD THEREOF - A button control system for medical touch screen and method thereof comprises a central control module, a touch signal input module, a lock time control module, a button lock module, a button unlock module and a cleanse display module, wherein the central control module determines the signal inputted by the touch signal input module, and selects to control the button lock module or the button unlock module thereby locking or unlocking a touch button; furthermore, the lock time control module is configured to set up the lock time for the touch button so as to preset the lock time of the touch button as cleansing the touch screen by the user, and after pressing down the cleanse touch button on the touch screen, it allows to control to lock or unlock other touch buttons and also to effectively prevent the occurrence of the situation where the screen button is erroneously touched as performing the cleanse process. | 04-05-2012 |