Hung, Hsin-Chu
Bin-Yuan Hung, Hsin-Chu TW
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20100308444 | Method of Manufacturing an Electronic Device - In order to protect IMD layers, particularly low-k dielectrics, a protection film is formed on the sidewall of an opening in the IMD layers prior to etching a trench in the underlying silicon substrate. After etching the trench, such as through a TMAH wet etch, at least part of the protection film can be removed. The protection film can be removed in an anisotropic etch process such that a portion of the protection film remains as a sidewall spacer on the sidewall of the opening within the IMD layers. | 12-09-2010 |
Cheng-Lung Hung, Hsin-Chu TW
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20100105185 | REDUCING POLY-DEPLETION THROUGH CO-IMPLANTING CARBON AND NITROGEN - A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer over the semiconductor substrate; forming a gate electrode layer over the gate dielectric layer; doping carbon and nitrogen into the gate electrode layer; and, after the step of doping carbon and nitrogen, patterning the gate dielectric layer and the gate electrode layer to form a gate dielectric and a gate electrode, respectively. | 04-29-2010 |
Chen-Hsiu Hung, Hsin-Chu TW
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20150241764 | PROJECTOR AND BRIGHTNESS ADJUSTING METHOD THEREOF - The invention provides a projector and a brightness adjusting method thereof. The projector includes a light source module, a color wheel module, a brightness adjusting device, and a brightness processing module. The light source module is used for emitting a light beam. The color wheel module is used for being excited to generate at least one color light beam by the light beam emitted from the light source module. The brightness adjusting device includes a light sensor and a brightness processing module, wherein the light sensor is disposed on a transmission path of a portion of the color light beam and the brightness processing module is electrically connected to the light sensor for adjusting the brightness value of the color light beam. The brightness adjusting method of projector is also provided. | 08-27-2015 |
Chia-Chun Hung, Hsin-Chu TW
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20120143490 | VEHICLE RECORDING APPARATUS AND VIDEO RECORDING METHOD - A vehicle recording apparatus includes a video capturing unit, a storage unit and a processing unit. The video capturing unit is for capturing a video. The storage unit includes a file including an index block and a plurality of storage blocks. The processing unit stores the video into the storage block according to a data index in the index block. The aforementioned vehicle recording apparatus may prevent an execution of file opening or closing from causing the video unable to be recorded, or an abnormal file close from leading to the damage of the file. A video recording method is also disclosed. | 06-07-2012 |
20120174153 | VIDEO PLAYBACK APPARATUS AND METHOD - A video playback apparatus includes a user interface, an image processing module and a playback module. The user interface allows a user to select an original playback mode or a compensated playback mode, and outputs a corresponding playback mode signal. The image processing module is for receiving a video signal and the playback mode signal and sending the video signal substantially unaltered or compensating the video signal before sending according to the playback mode signal. The playback module is for playing back the video signal from the image processing module. The aforementioned video playback apparatus provides the user different playback mode selections for the same video. | 07-05-2012 |
20120262299 | EARTHQUAKE-TRIGGERED EMERGENCY INDICATOR - An earthquake-triggered emergency indicator includes an earthquake detector, an indicator, a controller, and a battery module. The earthquake detector is configured for detecting a vibration. The indicator is configured for generating an indication signal in a form of light, sound or vibration to guide a user to take an emergency measure. The controller is configured for generating a trigger signal based on a magnitude and a lasting time of the vibration so as to trigger the indicator to output the correspondent indication signal. The battery module is configured for providing power supply required for operation of the earthquake-triggered emergency indicator. Preferably, the above-mentioned earthquake-triggered emergency indicator includes a wireless communication module for connecting multiple earthquake-triggered emergency indicators to reduce adverse effects caused by malfunctioning single emergency indicator. | 10-18-2012 |
Chia-Hsing Hung, Hsin-Chu TW
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20130038809 | LIQUID CRYSTAL DISPLAY DEVICE - A liquid crystal display device includes a backlight module, a liquid crystal display panel, an insulating cover and a touch panel assembly. The insulating cover includes a reflective bottom plate for supporting the backlight module, at least one first sidewall with a first end and an opposite second end, at least one second sidewall with a third end and an opposite fourth end and a supporting plate connected to the opposite second end of the first sidewall and the third end of the second sidewall. The supporting plate is arranged in parallel with the reflective bottom plate and has an upper surface for supporting the liquid crystal display panel. The securing frame has a first end portion fixed to a lower surface of the supporting and a second end portion. | 02-14-2013 |
20140160375 | LIQUID CRYSTAL DISPLAY DEVICE - A liquid crystal display device includes a backlight module, a liquid crystal display panel, an insulating cover and a touch panel assembly. The insulating cover includes a reflective bottom plate for supporting the backlight module, at least one first sidewall with a first end and an opposite second end, at least one second sidewall with a third end and an opposite fourth end and a supporting plate connected to the opposite second end of the first sidewall and the third end of the second sidewall. The supporting plate is arranged in parallel with the reflective bottom plate and has an upper surface for supporting the liquid crystal display panel. The securing frame has a first end portion fixed to a lower surface of the supporting and a second end portion. | 06-12-2014 |
Chien-Yao Hung, Hsin-Chu TW
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20100127722 | CIS Circuit Test Probe Card - A CIS test probe card with an optic assembly is disclosed. At least one embodiment relates to the optic assembly being located close to the CIS test probe card to collimate a light before it is projected through the CIS test probe card to the wafer. At least one embodiment relates to a change in the geometric configuration of the hole(s) and the probe(s) in the CIS test probe card. Small holes corresponding to the CIS chips in a one-on-one fashion can be implemented, such that each small hole is located over a corresponding CIS chip. | 05-27-2010 |
20140091827 | PROBE CARD FOR CIRCUIT-TESTING - A probe card for circuit-testing comprising a testing PCB, a probe head, and a silicon interposer substrate is provided. The probe head has a plurality of probes provided with a fine pitch arrangement and held inside. The silicon interposer substrate is used for conveying signals between said probes and said test PCB. The interconnection of said silicon interposer substrate is formed by utilizing the through-silicon via process. A plurality of upper terminals and a plurality of lower terminals are respectively array-arranged on the top surface and the bottom surface of said silicon interposer substrate. The pitch between the upper terminals is larger than the pitch between the lower terminals and the pitch between adjacent lower terminals is equal to the fine pitch of the arrangement of probes. | 04-03-2014 |
20150334835 | PRINTED CIRCUIT BOARD OF PROBE CARD - The present invention relates to a printed circuit board of a probe card. The printed circuit board comprises a first side, a second side, a plurality of plated through holes and at least one electric barrier. The first side includes a plurality of first contacts and a plurality of second contacts respectively corresponding to the first contacts. The second side includes a plurality of third contacts respectively corresponding to the second contacts and a plurality of second-side traces extended to a predefined/specific region. The plated through holes penetrate through the first side and the second side, so that the third contacts are electrically connected to the second contacts. The at least one electric barrier is installed among at least two of the second side traces. | 11-19-2015 |
20150342021 | PRINTED CIRCUIT BOARD STRUCTURE - The invention relates to a printed circuit board structure, which comprises a first body, a second body and a sleeve. The sleeve is arranged between and connected with the first body and the second body so as to generate a differential height between the first body and the second body. Via the differential height are solved the problems of insufficient probe stiffness and poor wafer-sort quality, which is caused by decreasing the probe diameter to adapt to miniaturized chips. | 11-26-2015 |
Chih-Shin Hung, Hsin-Chu TW
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20160133233 | DISPLAY DEVICE AND DISPLAY METHOD FOR DISPLAY DEVICE - A display device and a display method for the display device are provided. An image processing unit actively reads indicator bits stored in a receiving unit to determine whether the receiving unit receives an image signal. When it is determined that the receiving unit receives the image signal, the image processing unit enters a synchronous processing period to start receiving the image signal from the receiving unit. | 05-12-2016 |
Chih-Wei Hung, Hsin-Chu TW
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20100290284 | Single-Transistor EEPROM Array and Operation Methods - An integrated circuit structure includes an electrically erasable programmable read-only memory (EEPROM) array, which includes EEPROM cells arranged as rows and columns; a plurality of word-lines and a plurality of drain-lines extending in a column direction, and a plurality of source-lines extending in a row direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. Each of the plurality of drain-lines is connected to drains of the EEPROM cells in a same column, wherein none of the plurality of drain-lines are shared by neighboring columns of the EEPROM cells. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row. | 11-18-2010 |
20120134209 | Single-Transistor EEPROM Array and Operation Methods - A method includes performing an operation on an electrically erasable programmable read-only memory (EEPROM) array. The operation is selected from a program operation and an erase operation. The EEPROM array includes EEPROM cells arranged in rows and columns, and a plurality of word-lines extending in a column direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. The EEPROM array further includes a plurality of source-lines extending in a row direction. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row. During the operation, a first source-line in the plurality of source-lines is applied with a first source-line voltage, and a second source-line in the plurality of source-lines is applied with a second source-line voltage different from the first source-line voltage. | 05-31-2012 |
Chih-Yi Hung, Hsin-Chu TW
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20140048777 | ORGANIC LIGHT EMITTING DIODE MODULE - An organic light emitting diode module is provided and includes a substrate, a first electrode located on the substrate, a pair of second electrodes located on the substrate, a light emitting element located on the substrate, a first copper foil electrically connected to the first electrode, a pair of second copper foils respectively electrically connected to the second electrodes, and a cross connection conductor electrically connected to the second copper foils. The second electrodes are in an arrangement opposite to one another. The light emitting element includes a first electrode layer electrically connected to the first electrode, a second electrode layer located between the second electrodes and electrically connected to the second electrodes, and an organic light emitting layer located between the first and second electrode layers. | 02-20-2014 |
Chun-Chang Hung, Hsin-Chu TW
Patent application number | Description | Published |
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20100163898 | LIGHT EMITTING DIODE APPARATUS - A light emitting diode apparatus comprises a substrate having a circuit pattern, a reflection layer disposed on the substrate, at least one light emitting element disposed on the reflection layer, a reflector disposed around the at least one light emitting element, a sealing material formed over the at least one light emitting element and a phosphor layer disposed over the sealing material. The light emitting element comprises a conductive portion electrically coupled to the circuit pattern. In one embodiment, a plurality of light emitting elements are linearly arrayed, and a spacer is disposed between every two adjacent light emitting elements. | 07-01-2010 |
20100188615 | Display Device, Manufacturing Method Thereof, and Color Adjusting Method Used Thereon - A display device, a manufacturing method thereof, and a color adjusting method used thereon are provided. The display device includes a blue light source and a display panel which includes a substrate having a color adjusting layer, a blue filter layer, and an inner polarizer disposed thereon. The color adjusting layer includes a plurality of color excitation units, wherein each color excitation unit contains a plurality of wavelength transformation materials. The blue filter layer allows only blue light to pass therethrough and absorbs other color light. The blue light passes through the inner polarizer and the blue filter layer to reach the color excitation units. The blue light further excites the wavelength transformation materials to generate different color light. A part of the different color light is transmitted to and absorbed by the blue filter layer. | 07-29-2010 |
20100232178 | Light Guide Plate Assembly - Alight guide plate assembly for a backlight module is provided. The light guide plate assembly includes a plurality of light guide plates. Each light guide plate has a top face, at least one side face, and at least one connecting part. The connecting part is formed on the side face of the light guide plate. The connecting part has a connecting face, wherein the adjacent connecting faces are connected to each other. The top faces of the plurality of light guide plates are coplanar. A distance between the connecting face and the top face is ⅓ to 1/20 of the thickness of the light guide plate. | 09-16-2010 |
Chun-Hsiung Hung, Hsin-Chu TW
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20130155777 | CURRENT SENSING TYPE SENSE AMPLIFIER AND METHOD THEREOF - The configurations of sense amplifier and methods thereof are provided. The proposed sense amplifier includes a switch circuit having a main control switch, a sensing switch and a holding switch, wherein the three switches have a first bias, a second bias and a third bias respectively, and an auxiliary control switch electrically connected to the holding switch to control an operation of the holding switch. | 06-20-2013 |
20130208544 | FLASH MEMORY WITH READ TRACKING CLOCK AND METHOD THEREOF - The configurations of a flash memory having a read tracking clock and method thereof are provided. The proposed flash memory includes a first and a second storage capacitors, a first current source providing a first current flowing through the first storage capacitor, a second current source providing a second current flowing through the second storage capacitor, and a comparator electrically connected to the first and the second current sources, and sending out a signal indicating a developing time being accomplished when the second current is larger than the first current. | 08-15-2013 |
20140153326 | CELL SENSING CIRCUIT FOR PHASE CHANGE MEMORY AND METHODS THEREOF - A cell sensing circuit for a phase changing memory and methods thereof are provided. A specific one of the proposed methods includes: providing a sensing circuit having a sense amplifier, and two identical stable currents respectively received by a reference cell and a target cell; establishing a cell voltage on a cell side and a reference voltage on a reference side respectively via the two identical stable currents; and using the sense amplifier to determine a logic state of the target cell based on a voltage difference between the reference voltage and the cell voltage. | 06-05-2014 |
Chun-Lung Hung, Hsin-Chu TW
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20110298759 | Method of Reducing Noises on a Touch Panel - During test of a display, a synchronous reference signal is determined, and an appearing moment of a minimal-noise signal is determined based on a start moment of the synchronous reference signal. Therefore, during other tests or usage by a user on the display, noise from data lines due to data coupling may be avoided, and detection and determination of touch commands on a touch panel of the display may be isolated from being disturbed by the noise. | 12-08-2011 |
20120154322 | METHOD FOR DETERMINING SCANNING TIMES OF TOUCH DRIVING PULSE IN A TOUCH PANEL - A method for determining scanning times of touch driving pulse in a touch panel includes steps of: judging a current gate line scan period is in which one of a data updating time period and a blanking time period; if the current gate line scan period is in the data updating time period, setting a scanning times of touch driving pulse in the current gate line scan period to be a first value; and if the current gate line scan period is in the blanking time period, setting the scanning times of touch driving pulse in the current gate line scan period to be a second value. The first value is different from the second value, and a time for touch driving pulse scanning is non-overlapped with another time for providing display data to data lines of the touch panel in each scan line scan period. | 06-21-2012 |
20120242595 | METHOD FOR DETERMINING TOUCH POINT - An exemplary method for determining a touch point includes the following steps of: performing a first operation to determine whether a detected result of a first touch detection point exceeds a first threshold; performing a second operation to determine whether all detected results of multiple second touch detection points are no more than the detection result of the first touch detection point, the second touch detection points neighboring with the first touch detection point; performing a third operation to determine whether a sum of detected results of multiple third touch detection points exceeds a second threshold, the third touch detection points neighboring with the first touch detection point; and determining the first touch detection point as the touch point is being touched if the determine results of the first through third operations are all true. | 09-27-2012 |
20130153753 | LIGHT SENSING APPARATUS AND ADJUSTMENT METHOD THEREOF - A light sensing apparatus includes a light sensing module, a signal conversion module and a processing module. The light sensing module is configured to output a first and second sense signals according to a light intensity emitting thereon. The signal conversion module is electrically coupled to the light sensing module and configured to receive the first and second sense signals and output a sense value according to a relative difference between the first and second sense signals, The comparison module is electrically coupled to the signal conversion module and configured to adjust a light sensing characteristic of the light sensing module according to the sense value so as to adjust a light sensing characteristic of the light sensing module. An adjustment method for a light sensing apparatus is also provided. | 06-20-2013 |
Chun-Shiung Hung, Hsin-Chu TW
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20090128115 | VOLTAGE REGULATOR AND CONTROLLING METHOD THEREOF - A controlling method of a voltage regulator is provided. The voltage regulator at least includes a differential circuit and a pump high-voltage circuit which has a bias path, an output transistor and an output terminal. The controlling method includes steps of: providing at least a pre-charge path to the pump high-voltage circuit, closing the bias path and charging the output terminal with the pre-charge path when the output terminal is transient, detecting an output level of the output terminal, and closing the pre-charge path and open the bias path to bias the output transistor when the output level reaches a predetermined value. | 05-21-2009 |
Jonathan Hung, Hsin-Chu TW
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20080224785 | Temperature tracking oscillator circuit - A temperature-dependent oscillator includes a first current source, wherein a first current provided by the first current source has a positive temperature coefficient, a second current source serially connected to the first current source, wherein a second current provided by the second current source has a negative temperature coefficient, and a capacitor serially connected to the first current source and parallel connected to the second current source. | 09-18-2008 |
20090251975 | Circuit and Method for a Sense Amplifier with Instantaneous Pull Up/Pull Down Sensing - A circuit and method for a sense amplifier for sensing the charge stored when a select signal couples a memory cell to the sense amplifier. A pull up voltage and a pull down voltage are instantaneously supplied to the sense amplifier to sense the small signal differential input on the complementary bit lines and to simultaneously restore the value stored in the memory cell. A differential output signal generator circuit is provided to instantaneously supply the pull up and pull down voltages. In another preferred embodiment the signal generator provides the pull up and pull down voltages at a first level and subsequently increases the pull up voltage to a voltage greater than the positive supply voltage and decreases the pull down voltage. A method of sensing is disclosed wherein the sense and restore actions are performed instantaneously to provide memory cell sensing with greater tolerance of device mismatches. | 10-08-2009 |
Jui-Pin Hung, Hsin-Chu TW
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20130001776 | Interconnect Structure for Wafer Level Package - A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI. | 01-03-2013 |
20130037990 | Molding Wafer Chamber - A bottom chase and a top chase of a molding system form a cavity to house a molding carrier and one or more devices. The molding carrier is placed in a desired location defined by a guiding component. The guiding component may be entirely within the cavity, or extend above a surface of the bottom chase and extend over a contacting edge of the top chase and the bottom chase, so that there is a gap between the edge of the top chase and the edge of the molding carrier which are filled by molding materials to cover the edge of the molding carrier. Releasing components may be associated with the top chase and/or the bottom chase, which may be a plurality of tape roller with a releasing film, or a plurality of vacuum holes within the bottom chase, or a plurality of bottom pins with the bottom chase. | 02-14-2013 |
20130062760 | Packaging Methods and Structures Using a Die Attach Film - Packaging methods and structures for semiconductor devices that utilize a novel die attach film are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer and forming a die attach film (DAF) that includes a polymer over the carrier wafer. A plurality of dies is attached to the DAF, and the plurality of dies is packaged. At least the carrier wafer is removed from the packaged dies, and the packaged dies are singulated. | 03-14-2013 |
20130075892 | Method for Three Dimensional Integrated Circuit Fabrication - A method for fabricating three dimensional integrated circuits comprises providing a wafer stack wherein a plurality of semiconductor dies are mounted on a first semiconductor die, forming a molding compound layer on the first side of the first semiconductor die, wherein the plurality of semiconductor dies are embedded in the molding compound layer. The method further comprises grinding a second side of the first semiconductor die until a plurality of through vias become exposed, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages. | 03-28-2013 |
20130087916 | Methods of Packaging Semiconductor Devices and Structures Thereof - Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies. | 04-11-2013 |
20130087951 | Molding Chamber Apparatus and Curing Method - An embodiment is a molding chamber. The molding chamber comprises a mold-conforming chase, a substrate-base chase, a first radiation permissive component, and a microwave generator coupled to a first waveguide. The mold-conforming chase is over the substrate-base chase, and the mold-conforming chase is moveable in relation to the substrate-base chase. The first radiation permissive component is in one of the mold-conforming chase or the substrate-base chase. The microwave generator and the first waveguide are together operable to direct microwave radiation through the first radiation permissive component. | 04-11-2013 |
20130115854 | End Point Detection in Grinding - A method for performing grinding includes selecting a target wheel loading for wafer grinding processes, and performing a grinding process on a wafer. With the proceeding of the grinding process, wheel loadings of the grinding process are measured. The grinding process is stopped after the target wheel loading is reached. The method alternatively includes selecting a target reflectivity of wafer grinding processes, and performing a grinding process on a wafer. With a proceeding of the grinding process, reflectivities of a light reflected from a surface of the wafer are measured. The grinding process is stopped after one of the reflectivities reaches the target reflectivity. | 05-09-2013 |
20130119533 | Package for Three Dimensional Integrated Circuit - A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package. | 05-16-2013 |
20130119552 | Method for Forming Chip-on-Wafer Assembly - A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip. | 05-16-2013 |
20130122689 | Methods for De-Bonding Carriers - A method includes performing a dicing on a composite wafer including a plurality of dies, wherein the composite wafer is bonded on a carrier when the step of dicing is performed. After the step of dicing, the composite wafer is mounted onto a tape. The carrier is then de-bonded from the composite wafer and the first tape. | 05-16-2013 |
20130187270 | Multi-Chip Fan Out Package and Methods of Forming the Same - A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line. | 07-25-2013 |
20130203215 | Packaging Methods for Semiconductor Devices - Methods of packaging semiconductor devices are disclosed. In one embodiment, a packaging method for semiconductor devices includes providing a workpiece including a plurality of first dies, and coupling a plurality of second dies to the plurality of first dies. The plurality of second dies and the plurality of first dies are partially packaged and separated. Top surfaces of the second dies are coupled to a carrier, and the partially packaged plurality of second dies and plurality of first dies are fully packaged. The carrier is removed, and the fully packaged plurality of second dies and plurality of first dies are separated. | 08-08-2013 |
20130207306 | Methods for Molding Integrated Circuits - A method includes molding a polymer onto a package component. The step of molding includes a first molding stage performed at a first temperature, and a second molding stage performed at a second temperature different from the first temperature. | 08-15-2013 |
20140001612 | Multiple Die Packaging Interposer Structure and Method | 01-02-2014 |
20140084459 | Multiple Die Packaging Interposer Structure and Method - System and method for providing a multiple die interposer structure. An embodiment comprises a plurality of interposer studs in a molded interposer, with a redirection layer on each side of the interposer. Additionally, the interposer studs may be initially attached to a conductive mounting plate by soldering or wirebond welding prior to molding the interposer, with the mounting plate etched to form one of the redirection layers. Integrated circuit dies may be attached to the redirection layers on each side of the interposer, and interlevel connection structures used to mount and electrically connect a top package having a third integrated circuit to the interposer assembly. | 03-27-2014 |
20140151890 | PACKAGE WITH A FAN-OUT STRUCTURE AND METHOD OF FORMING THE SAME - An embodiment is a device comprising a semiconductor die, an adhesive layer on a first side of the semiconductor die, and a molding compound surrounding the semiconductor die and the adhesive layer, wherein the molding compound is at a same level as the adhesive layer. The device further comprises a first post-passivation interconnect (PPI) electrically coupled to a second side of the semiconductor die, and a first connector electrically coupled to the first PPI, wherein the first connector is over and aligned to the molding compound. | 06-05-2014 |
20140183731 | Package on Package (PoP) Bonding Structures - Various embodiments of mechanisms for forming through package vias (TPVs) with multiple conductive layers and/or recesses in a die package and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. One of the multiple conductive layers acts as a protective layer of the main conductive layer of the TPVs. The protective layer is less likely to oxidize and also has a slower formation rate of intermetallic compound (IMC) when exposed to solder. The recesses in TPVs of a die package are filled by solder from the other die package and the IMC layer formed is below the surface of TPVs, which strengthen the bonding structures. | 07-03-2014 |
20140210081 | Packaging Methods and Packaged Semiconductor Devices - Packaging methods and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging semiconductor devices includes forming first contact pads on a carrier, forming a wiring structure over the first contact pads, and forming second contact pads over the wiring structure. A first packaged semiconductor device is coupled to a first set of the second contact pads, and a second packaged semiconductor device is coupled to a second set of the second contact pads. The carrier is removed. The second packaged semiconductor device comprises a different package type than the first packaged semiconductor device. | 07-31-2014 |
20140210101 | Die package with Openings Surrounding End-portions of Through Package Vias (TPVs) and Package on Package (PoP) Using the Die Package - Various embodiments of mechanisms for forming through package vias (TPVs) with openings surrounding end-portions of the TPVs and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. The openings are formed by removing materials, such as by laser drill, surrounding the end-portions of the TPVs. The openings surrounding the end-portions of the TPVs of the die package enable solders of the bonding structures formed between another die package to remain in the openings without sliding and consequently increases yield and reliability of the bonding structures. Polymers may also be added to fill the openings surrounding the TPVs or even the space between the die packages to reduce cracking of the bonding structures under stress. | 07-31-2014 |
20140252646 | Interconnect Structure for Package-on-Package Devices - An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package. | 09-11-2014 |
20140264828 | Method and Apparatus for a Conductive Pillar Structure - A method and apparatus for a conductive pillar structure is provided. A device may be provided, which may include a substrate, a first passivation layer formed over the substrate, a conductive interconnect extending through the first passivation layer and into the substrate, a conductive pad formed over the first passivation layer, and a second passivation layer formed over the interconnect pad and the second passivation layer. A portion of the interconnect pad may be exposed from the second passivation layer. The conductive pillar may be formed directly over the interconnect pad using one or more electroless plating processes. The conductive pillar may have a first and a second width and a first height corresponding to a distance between the first width and the second width. | 09-18-2014 |
20140264839 | Packaged Semiconductor Devices, Methods of Packaging Semiconductor Devices, and PoP Devices - Packaged semiconductor devices, methods of packaging semiconductor devices, and package-on-package (PoP) devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming through-package vias (TPVs) over a carrier, and coupling a semiconductor device to the carrier. The semiconductor device includes contact pads disposed on a surface thereof and an insulating material disposed over the contact pads. A molding material is formed over the carrier between the TPVs and the semiconductor device. Openings are formed in the insulating material using a laser drilling process over the contact pads, and a redistribution layer (RDL) is formed over the insulating material and the openings in the insulating material. A portion of the RDL is coupled to a top surface of each of the contact pads. | 09-18-2014 |
20140264853 | Adhesion between Post-Passivation Interconnect Structure and Polymer - An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a thin oxide film layer directly over a top surface of the PPI structure, and a polymer layer over the thin oxide film layer and PPI structure. | 09-18-2014 |
20140287553 | Method for Forming Chip-on-Wafer Assembly - A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip. | 09-25-2014 |
20140312492 | Package with a Fan-out Structure and Method of Forming the Same - An embodiment is a device comprising a semiconductor die, an adhesive layer on a first side of the semiconductor die, and a molding compound surrounding the semiconductor die and the adhesive layer, wherein the molding compound is at a same level as the adhesive layer. The device further comprises a first post-passivation interconnect (PPI) electrically coupled to a second side of the semiconductor die, and a first connector electrically coupled to the first PPI, wherein the first connector is over and aligned to the molding compound. | 10-23-2014 |
20140322866 | Package for Three Dimensional Integrated Circuit - A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package. | 10-30-2014 |
20140339696 | Interconnect Structure for Wafer Level Package - A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI. | 11-20-2014 |
20140346665 | Integrated Circuit Structure and Method for Reducing Polymer Layer Delamination - An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM. | 11-27-2014 |
20150050779 | Packaged Semiconductor Devices, Methods of Packaging Semiconductor Devices, and PoP Devices - Packaged semiconductor devices, methods of packaging semiconductor devices, and package-on-package (PoP) devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming through-package vias (TPVs) over a carrier, and coupling a semiconductor device to the carrier. The semiconductor device includes contact pads disposed on a surface thereof and an insulating material disposed over the contact pads. A molding material is formed over the carrier between the TPVs and the semiconductor device. Openings are formed in the insulating material using a laser drilling process over the contact pads, and a redistribution layer (RDL) is formed over the insulating material and the openings in the insulating material. A portion of the RDL is coupled to a top surface of each of the contact pads. | 02-19-2015 |
20150050783 | Molding Chamber Apparatus and Curing Method - An embodiment is a molding chamber. The molding chamber comprises a mold-conforming chase, a substrate-base chase, a first radiation permissive component, and a microwave generator coupled to a first waveguide. The mold-conforming chase is over the substrate-base chase, and the mold-conforming chase is moveable in relation to the substrate-base chase. The first radiation permissive component is in one of the mold-conforming chase or the substrate-base chase. The microwave generator and the first waveguide are together operable to direct microwave radiation through the first radiation permissive component. | 02-19-2015 |
20150061149 | Packages, Packaging Methods, and Packaged Semiconductor Devices - Packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a redistribution layer (RDL) and a plurality of through package vias (TPV's) coupled to the RDL. Each of the plurality of TPV's comprises a first region proximate the RDL and a second region opposite the first region. The first region comprises a first width, and the second region comprises a second width. The second width is greater than the first width. | 03-05-2015 |
20150069623 | Integrated Fan-Out Structure with Guiding Trenches in Buffer Layer - A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding compound. A device die is molded in the molding compound. A guiding trench extends from a top surface of the buffer layer into the buffer layer, wherein the guiding trench is misaligned with the device die. | 03-12-2015 |
20150076713 | Integrated Fan-Out Package Structures with Recesses in Molding Compound - A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface. | 03-19-2015 |
20150084190 | Multi-Chip Package Structure and Method of Forming Same - A device comprises a first semiconductor die embedded in a molding compound layer, a surface-mount device embedded in the molding compound layer, a plurality of interconnect structures formed on the molding compound layer, wherein the first semiconductor die is electrically coupled to the interconnect structures and the surface-mount device is electrically coupled to the interconnect structures through at least one V-shaped via and a plurality of bumps formed on and electrically coupled to the interconnect structures. | 03-26-2015 |
20150084191 | Multi-Chip Package and Method of Formation - A device comprises a first semiconductor die embedded in a molding compound layer, a surface-mount device embedded in the molding compound layer, a plurality of interconnect structures formed on the molding compound layer, wherein the first semiconductor die is electrically coupled to the interconnect structures and the surface-mount device is electrically coupled to the interconnect structures through at least a metal pillar and a plurality of bumps formed on and electrically coupled to the interconnect structures. | 03-26-2015 |
20150115464 | Chip on Package Structure and Method - A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die. | 04-30-2015 |
20150132892 | Packaging Methods for Semiconductor Devices - Methods of packaging semiconductor devices are disclosed. In one embodiment, a packaging method for semiconductor devices includes providing a workpiece including a plurality of first dies, and coupling a plurality of second dies to the plurality of first dies. The plurality of second dies and the plurality of first dies are partially packaged and separated. Top surfaces of the second dies are coupled to a carrier, and the partially packaged plurality of second dies and plurality of first dies are fully packaged. The carrier is removed, and the fully packaged plurality of second dies and plurality of first dies are separated. | 05-14-2015 |
20150187724 | Method and Apparatus for a Conductive Pillar Structure - A method and apparatus for a conductive pillar structure is provided. A device may be provided, which may include a substrate, a first passivation layer formed over the substrate, a conductive interconnect extending through the first passivation layer and into the substrate, a conductive pad formed over the first passivation layer, and a second passivation layer formed over the interconnect pad and the second passivation layer. A portion of the interconnect pad may be exposed from the second passivation layer. The conductive pillar may be formed directly over the interconnect pad using one or more electroless plating processes. The conductive pillar may have a first and a second width and a first height corresponding to a distance between the first width and the second width. | 07-02-2015 |
20150255447 | Interconnect Structure for Package-on-Package Devices - An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package. | 09-10-2015 |
20150364395 | Methods of Packaging Semiconductor Devices and Structures Thereof - Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies. | 12-17-2015 |
20160118272 | Interconnect Structure for Wafer Level Package - A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI. | 04-28-2016 |
Kevin Hung, Hsin-Chu TW
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20100174933 | System and Method for Reducing Processor Power Consumption - A system and method for reducing active power in processors is disclosed. A method embodiment comprises the steps of determining when a particular logic block is inactive, determining the powered state of the particular logic block, isolating the particular logic block from a main processor core, and powering off the particular logic block. When the system needs the particular logic block, the method further comprises reactivating the block. A system embodiment comprises software and a processor coupled to a clock control module, an isolation control module and a header/footer module, operable to isolate a particular logic block and power off a particular logic block, thereby reducing power. Another embodiment comprises a logic module coupled to a clock by a clock gating module, an isolation module for isolating the logic module, a header/footer module for disabling power to the logic module, and a power and clock gating control module for controlling the clock gating module and the header/footer module. | 07-08-2010 |
Kuang-I Hung, Hsin-Chu TW
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20130268707 | MICRO SD CARD ADAPTER DEVICE - A card adapter device includes a card slot for receiving a micro SD card therein; a SD interface for coupling electrically to a portable electronic device; a processing chip including a dynamic switch coupled electrically to the card slot and the SD interface, and a processor unit coupled electrically to the dynamic switch; and a wireless transmission/reception interface coupled electrically to the dynamic switch. Upon receiving a first signal from the wireless transmission/reception interface, the dynamic switch detects an operation mode of the SD interface and upon detecting that the SD interface is in an idle mode, the processor unit converts the dynamic switch to be coupled electrically to the wireless transmission/reception interface, thereby enabling the dynamic switch to transfer the first signal to the card slot, which, in turn, enables the wireless transmission/reception interface to access into the SD card. | 10-10-2013 |
Kuen-Jen Hung, Hsin-Chu TW
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20120161521 | STANDBY WAKE-UP CIRCUIT FOR ELECTRONIC DEVICE - A standby wake-up circuit is configured for determining whether to wake an electronic device which is powered by a power-supplying module. The power-supply module is able to supply a standby power to the electronic device when the electronic device is in standby, and supply a main power to the electronic device when the electronic device is wakened. The standby wake-up circuit comprises an input-signal detecting circuit and a processing module. The input-signal detecting circuit comprises a power-key detecting module, an input-signal detecting module, a multiplexer and a power controller. The power-key detecting module and the input-signal detecting module are configured for detecting whether a signal is inputted. When inputting the signal, the power controller sends out a waken signal for supplying the main power to the electronic device. | 06-28-2012 |
Kuo-Tai Hung, Hsin-Chu TW
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20100253276 | Power supply system and circuit control method thereof - A power supply system is adapted to providing a rated power to a load, and includes a fuel cell, a secondary battery, a charging device, and a control unit. The fuel cell provides a first power. The secondary battery provides a second power and is electrically connected with the fuel cell. The charging device is electrically connected with the fuel cell and the secondary battery. | 10-07-2010 |
Lei-Ken Hung, Hsin-Chu TW
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20110063875 | BACKLIGHT MODULE - A backlight module includes at least one light emitting device capable of emitting a light beam, a light guide plate, and a thermal insulation light guide element. The light guide plate has two surfaces opposite to each other and a side surface connecting the two surfaces. The light emitting device is disposed beside the side surface. The light beam enters the light guide plate through the side surface. The thermal insulation light guide element has a light incident surface and a light emitting surface. The light incident surface having at least one first recess is located in a transmission path of the light beam and between the light emitting device and the side surface. The light emitting surface is disposed between the light incident surface and the side surface. The glass transition temperature of the thermal insulation light guide element is higher than that of the light guide plate. | 03-17-2011 |
20110292314 | DISPLAY APPARATUS AND BACKLIGHT MODULE - A display apparatus and a backlight module are provided. The display apparatus includes a liquid crystal panel and a backlight module. The backlight module includes a frame, a plurality of latch members, and a backlight source. The frame has a receiving slot. The liquid crystal panel is disposed in the receiving slot. The latch members are disposed on the frame and located at an inner wall of the receiving slot. The latch members support the liquid crystal panel. A material of each latch member is a debris-resistant material. The backlight source is disposed on the frame and located at one side of the liquid crystal panel. The invention may prevent the producing of debris when the latch members and the liquid crystal panel are rubbed against each other. | 12-01-2011 |
Lin Chun Hung, Hsin-Chu TW
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20080218189 | Method and System for Automatically Managing Probe Mark Shifts - Disclosed is a method and a system for automatically managing probe mark shifts. A determination is made from test data as to whether a die on a wafer is defective. A probe mark check on the wafer is made to determine whether a probe mark is shifted. Necessary recovery action is performed in response to the probe mark being shifted. In the probe mark check, a plurality of probe mark positions are selected from the test data. A determination is then made as to whether at least one of the plurality of probe mark positions violates an engineering rule. | 09-11-2008 |
Mau-Yuan Hung, Hsin-Chu TW
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20100171904 | Backlight Module and Double-Sided Liquid Crystal Display Device - A backlight module includes a plate and a plurality of light sources. The plate has a first surface and a second surface opposite to the first surface. The plate is bent to form a plurality of first grooves on the first surface and a plurality of second grooves on the second surface. The light sources are respectively disposed in the first grooves and the second grooves. The backlight module is capable of providing two plane light sources to different directions and has thinner thickness. A double-sided liquid crystal display using the above-mentioned backlight module is also provided. | 07-08-2010 |
Meng-Chu Hung, Hsin-Chu TW
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20090237630 | Open-closed structure applied to a lamp door of a projector - An open-closed structure is used to open or close a lamp door of a projector. The projector includes a main lid. The lamp door covers the outer side of the main lid. The open-closed structure includes a base and a knob. The base is disposed at the inner side of the main lid. The knob is rotatably disposed on the base, and has an axial portion, a hook portion and a stick-like portion. One end of the hook portion is connected to the axial portion, and another end of that is selectively engaged with or separated from the lamp door. One end of the stick-like portion is also connected to the axial portion. When the axial portion of the knob is rotated to make the another end of the hook portion separated from the lamp door, another end of the stick-like portion is dependently moved to push the lamp door. | 09-24-2009 |
Meng-Yi Hung, Hsin-Chu TW
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20100085292 | LIQUID CRYSTAL DISPLAY HAVING DUAL DATA SIGNAL GENERATION MECHANISM - A liquid crystal display having dual data signal generation mechanism is disclosed for simplifying the display structure and retaining high display quality. The liquid crystal display includes a dual data signal generator, a preliminary data line, a first data line, a second data line, and a pixel unit. The dual data signal generator functions to convert a preliminary data signal, received from the preliminary data line, into a first data signal and a second data signal. The first and second data signals are furnished to the first and second data lines respectively. The pixel unit includes a first sub-pixel unit and a second sub-pixel unit. The first sub-pixel unit is coupled to the first data line for receiving the first data signal. The second sub-pixel unit is coupled to the second data line for receiving the second data signal. | 04-08-2010 |
20100173489 | METHOD FOR MANUFACTURING LOWER SUBSTRATE OF LIQUID CRYSTAL DISPLAY DEVICE - A method for manufacturing a lower substrate of a liquid crystal display device is disclosed. The method comprises the steps of: (a) forming a patterned first metal layer, a first insulating layer, a patterned second metal layer and a second insulating layer on a substrate in sequence; (b) coating a transparent electrode layer and a negative photo resist layer on the second insulating layer; (c) irradiating the photo resist layer from the second surface of the substrate; (d) irradiating the photo resist layer from the first surface of the substrate, wherein part of the photo resist layer superposed over the second metal layer is covered by a mask; and (e) removing un-reacted photo resist and patterning the transparent electrode. | 07-08-2010 |
20110149225 | Liquid Crystal Display Including Neighboring Sub-Pixel Electrodes with Opposite Polarities in the Same Pixel - A liquid crystal display includes an upper substrate, a lower substrate and a liquid crystal layer interposed between the upper substrate and the lower substrate. The lower substrate includes a pixel array divided into a plurality of columns of pixel areas and a plurality of rows of pixel areas. Each pixel area includes a upper sub-pixel electrode, a lower sub-pixel electrode insulated to the upper sub-pixel electrode and a TFT switch electrically connected to the lower sub-pixel electrode. The upper sub-pixel electrode is electrically connected to a lower sub-pixel electrode of a previous column, and the lower sub-pixel electrode is electrically connected to a upper sub-pixel electrode of a next column. | 06-23-2011 |
Ming-Chi Hung, Hsin-Chu TW
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20090147029 | Multi-frame overdriving circuit and method and overdriving unit of liquid crystal display - A multi-frame overdriving circuit for use in a liquid crystal display including a counting unit and a multi-frame overdriving unit is provided. The counting unit counts a number m of frame periods for which a pixel data corresponding to a pixel keeps a first gray value, wherein m is a positive integer. When the pixel data changes to a second gray value from the first gray value in a first frame period, the multi-frame overdriving unit respectively outputs y multi-frame overdriving pixel data corresponding to the pixel within successive y frame periods starting from the first frame period. The y multi-frame overdriving pixel data are related to the first gray value, the second gray value and the number m of frame periods, wherein y is a positive integer. | 06-11-2009 |
20140333688 | DISPLAY PANEL AND DRIVING METHOD THEREOF - A display panel includes a plurality of pixels, each of the pixels including a main sub-pixel and a secondary sub-pixel; a plurality of first scan lines, each of the first scan lines being coupled to main and secondary sub-pixels of a row of pixels; a plurality of second scan lines, each of the second scan lines being coupled to secondary sub-pixels of a row of pixels; a plurality of first data lines, each of the first data lines being coupled to main and secondary sub-pixels of (N+1)th and (N+2)th rows of pixels; a plurality of second data lines, each of the second data lines being coupled to main and secondary sub-pixels of (N+3)th and (N+4)th rows of pixels; a scan driver for turning on the main and secondary sub-pixels of the pixels; and a data driver for outputting data signals; wherein N is a multiple of 4, and N≧0. | 11-13-2014 |
Ming-Chin Hung, Hsin-Chu TW
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20120132914 | OXIDE SEMICONDUCTOR THIN FILM TRANSISTOR STRUCTURE AND METHOD OF MAKING THE SAME - An oxide semiconductor thin film transistor structure includes a substrate, a gate electrode disposed on the substrate, a semiconductor insulating layer disposed on the substrate and the gate electrode, an oxide semiconductor layer disposed on the semiconductor insulating layer, a patterned semiconductor layer disposed on the oxide semiconductor layer, and a source electrode and a drain electrode respectively disposed on the patterned semiconductor layer. The source electrode and the drain electrode are made of a metal layer. | 05-31-2012 |
Ming-Lang Hung, Hsin-Chu TW
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20130312426 | DRINKING DISPENSER AND THERMOELECTRIC HEAT PUMP APPARATUS THEREOF - A drinking dispenser has a warm water container; a hot water container coupled to the warm water container; a water supplying apparatus separately coupled to the warm water container and the hot water container; and a thermoelectric heat pump apparatus, configured with a pump that is arranged coupling to the water container and a thermoelectric module in respective coupled to the water container and the pump. | 11-28-2013 |
Ming-Tsun Hung, Hsin-Chu TW
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20150323798 | SMART HELMET - A smart helmet including a projection surface, a projection unit, a processing unit, and a first pivoting unit is provided. The projection unit projects an image light into the projection surface according to a projection data. The processing unit coupled to the projection unit, and provides the projection data to the projection unit. The first pivoting unit is adapted to adjust a projection angle of the projection unit projecting on the projection surface, and has three rotational degrees of freedom. | 11-12-2015 |
Min-Ling Hung, Hsin-Chu TW
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20080230798 | ACTIVE MATRIX ORGANIC ELECTROLUMINESCENT SUBSTRATE AND METHOD OF MAKING THE SAME - An active matrix organic electroluminescent substrate includes a substrate having a controlling element region and a luminescent region, a thin film transistor, a first passivation layer, a conductive layer electrically connected to the thin film transistor, and a second passivation layer disposed on the first passivation layer and the conductive layer. The second passivation layer has an opening partially exposing the conductive layer, and a step-shaped structure located between the controlling element region and the luminescent region. | 09-25-2008 |
Ping-Fang Hung, Hsin-Chu TW
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20090014813 | Metal Gates of PMOS Devices Having High Work Functions - A semiconductor structure includes a refractory metal silicide layer; a silicon-rich refractory metal silicide layer on the refractory metal silicide layer; and a metal-rich refractory metal silicide layer on the silicon-rich refractory metal silicide layer. The refractory metal silicide layer, the silicon-rich refractory metal silicide layer and the metal-rich refractory metal silicide layer include same refractory metals. The semiconductor structure forms a portion of a gate electrode of a metal-oxide-semiconductor device. | 01-15-2009 |
20140264505 | Methods for Measuring the Full Well Capacity of CMOS Image Sensors - An integrated circuit device includes a transfer-gate transistor, and a photo diode connected to a source/drain region of the transfer-gate transistor. An electrical fuse is electrically coupled to a gate of the transfer-gate transistor. A diode is electrically coupled to the electrical fuse. | 09-18-2014 |
20150262891 | Methods for Measuring the Full Well Capacity of CMOS Image Sensors - An integrated circuit device includes a transfer-gate transistor, and a photo diode connected to a source/drain region of the transfer-gate transistor. An electrical fuse is electrically coupled to a gate of the transfer-gate transistor. A diode is electrically coupled to the electrical fuse. | 09-17-2015 |
Sen-Chuan Hung, Hsin-Chu TW
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20130321372 | SHIFT REGISTER CIRCUITRY, DISPLAY AND SHIFT REGISTER - A shift register circuitry includes plurality stages of shift registers. An Nth stage shift register of the plurality stages of shift registers includes an input unit, an output unit, a control unit, a first pull-up unit, a second pull-up unit and a compensation circuit. The output unit is used to output an unmodified Nth stage scan signal. The input unit and the first pull-up unit are used to control the voltage level of a register control end. The control unit is used to receive a low reference voltage, a high reference voltage and the voltage level of the register control end, and control the voltage level of an output end of the control unit. The second pull-up unit is used to control the voltage level of an output end of the Nth stage shift register. The modification circuit is used to generate a modified Nth stage scan signal. | 12-05-2013 |
Sheng Chiang Hung, Hsin-Chu TW
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20100315862 | Stable SRAM Cell - SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor. | 12-16-2010 |
20130250660 | Stable SRAM Cell - SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor. | 09-26-2013 |
20130320522 | Re-distribution Layer Via Structure and Method of Making Same - An embodiment is a semiconductor device comprising a contact pad over a substrate, wherein the contact pad is disposed over an integrated circuit on the substrate and a first passivation layer over the contact pad. A first via in the first passivation layer, wherein the first via has more than four sides, and wherein the first via extends to the contact pad. | 12-05-2013 |
20140254248 | Stable SRAM Cell - SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor. | 09-11-2014 |
20140254249 | Stable SRAM Cell - SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor. | 09-11-2014 |
Shih-Hsing Hung, Hsin-Chu TW
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20110235160 | PACKAGE STRUCTURE OF A FLEXIBLE DISPLAY DEVICE - A package structure of flexible display device includes a flexible opto-electronic display panel, a first barrier layer and a second barrier layer. The flexible opto-electronic display panel includes a backplane, a flexible frontplane, and a display media layer. The display media layer is disposed between the flexible frontplane and the backplane, where the display media layer is substantially corresponding to a display region of the backplane, and at least one side of the display media layer aligns with one corresponding side of the backplane. The first barrier layer is disposed on a first surface of the flexible frontplane, where the flexible frontplane, the display media layer and the first barrier layer expose a bonding region of the backplane. The second barrier layer is disposed on a second surface of the backplane. | 09-29-2011 |
20110273760 | DISPLAY DEVICE - A display device includes a display panel, a barrier layer, a protective layer, a first optical adhesive layer and a second optical adhesive layer. The barrier layer is disposed above the display panel. The protective layer is disposed above the barrier layer. The first optical adhesive layer with a first thickness is disposed between the display panel and the barrier layer. The second optical adhesive layer with a second thickness is disposed between the protective layer and the barrier layer. The first thickness is larger than the second thickness. | 11-10-2011 |
20110292492 | Electrophoretic Display - An electrophoretic display device includes a substrate, an electrophoretic component layer, a first optical adhesive, a barrier layer, a second optical adhesive, a protective layer, and a sealant. The first optical adhesive and the second optical adhesive contribute in helping to provide light exposure to the sealant. One of the first optical adhesive and the second optical adhesive is capable of absorbing the light of predetermined wavelength and is adapted to expose the sealant. | 12-01-2011 |
20120087002 | Electrophoretic Display Structure - An electrophoretic display structure includes a substrate, an activation layer, an electrophoretic display layer, a protective layer, a first sealant, and a second sealant. The activation layer is disposed on the substrate while the electrophoretic display layer is disposed on the activation layer. The electrophoretic display layer has a plurality of electrophoretic display elements and a waterproof layer disposed on the electrophoretic display elements. The protective layer is disposed on the electrophoretic display elements. The protective layer is disposed on the waterproof layer, and the first sealant is disposed between the activation layer and the protective layer to fill in the sides of the electrophoretic display layer. The second sealant covers the outer side of the first sealant and connects with the activation layer and the protective layer. The viscosity of the first sealant in liquid state is lower than the viscosity of the second sealant in liquid state. | 04-12-2012 |
20130153270 | FLEXIBLE DISPLAY - A flexible display including a flexible substrate, an array circuit layer, a protection film, and an adhesive layer is provided. The flexible substrate has a first surface and a second surface, disposed opposite to each other. The array circuit layer is disposed on the second surface of the flexible substrate. The protection film is disposed on the first surface of the flexible substrate. The adhesive layer is disposed between the protection film and the flexible substrate, and has a thickness, substantially greater than or equal to 30 micrometers. | 06-20-2013 |
20150163866 | DISPLAY PANEL AND METHOD OF FABRICATING THE SAME - A display panel includes a substrate, a luminous display array, a thin film encapsulation, an auxiliary layer, an optical film and an optical clear adhesive. The luminous display array is disposed on the substrate. The thin film encapsulation layer is disposed on the substrate, covering the luminous display array. The auxiliary layer is disposed on the then thin film encapsulation. The auxiliary layer has an even top surface, and a shore hardness ranging from D4 to D60. The optical film is disposed on the auxiliary layer. The optical clear adhesive is disposed on the even top surface of the auxiliary layer for attaching the auxiliary layer and the optical film. | 06-11-2015 |
Tsung-Liang Hung, Hsin-Chu TW
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20130114167 | SHORT PROTECTION CONTROL CIRCUITS AND RELATED CONTROL METHODS - Short protection control circuits and related control methods are disclosed. A disclosed short protection control circuit is adapted for controlling a short protection mechanism providing short protection to several LED chains. The disclosed short protection control circuit has a detection circuit, a first logic circuit and a timer. Coupled to the LED chains, the detection circuit asserts an indication signal when one of the node voltages of the LED chains is lower than an under-current reference. When the indication signal is enabled, the first logic circuit starts blocking the short protection mechanism. The timer times to provide a result when the short protection mechanism is blocked. When the result indicates that the short protection mechanism has been blocked for at least a predetermined time period, the first logic circuit resumes the short protection mechanism. | 05-09-2013 |
Wei-Lun Hung, Hsin-Chu TW
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20110273628 | OPTICAL DEVICE AND PROJECTION SYSTEM - An optical device for controlling a projector is provided. The projector projects a projection image. The optical device includes a receiving module, a mode switching module, and a transmission module. The receiving module is capable of sensing a reflected signal of the projection image. The mode switching module is capable of generating a control signal to control the projector to switch from a first mode to a second mode. The transmission module is capable of transmitting the reflected signal and the control signal to the projector. A projection system including the projector and the optical device is also provided. | 11-10-2011 |
20130153270 | FLEXIBLE DISPLAY - A flexible display including a flexible substrate, an array circuit layer, a protection film, and an adhesive layer is provided. The flexible substrate has a first surface and a second surface, disposed opposite to each other. The array circuit layer is disposed on the second surface of the flexible substrate. The protection film is disposed on the first surface of the flexible substrate. The adhesive layer is disposed between the protection film and the flexible substrate, and has a thickness, substantially greater than or equal to 30 micrometers. | 06-20-2013 |
20160133233 | DISPLAY DEVICE AND DISPLAY METHOD FOR DISPLAY DEVICE - A display device and a display method for the display device are provided. An image processing unit actively reads indicator bits stored in a receiving unit to determine whether the receiving unit receives an image signal. When it is determined that the receiving unit receives the image signal, the image processing unit enters a synchronous processing period to start receiving the image signal from the receiving unit. | 05-12-2016 |
Wensen Hung, Hsin-Chu TW
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20160049389 | 3DIC Package and Methods of Forming the Same - A package includes a first molding material, a first device die molded in the molding material, a Through Via (TV) penetrating through the first molding material, and a redistribution line over the first molding material. The redistribution line is electrically connected to the TV. A second device die is over and bonded to the first device die through flip-chip bonding. A second molding material molds the second device die therein. | 02-18-2016 |
Ying-Chieh Hung, Hsin-Chu TW
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20160126105 | System and Method for Damage Reduction in Light-Assisted Processes - A method embodiment for forming a semiconductor device includes providing a dielectric layer having a damaged surface and repairing the damaged surface of the dielectric layer. Repairing the damaged surface includes exposing the damaged surface of the dielectric layer to a precursor chemical, activating the precursor chemical using light energy, and filtering out a spectrum of the light energy while activating the precursor chemical. | 05-05-2016 |
Yi-Xuan Hung, Hsin-Chu TW
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20130127801 | DISPLAY PANEL - A display panel includes a plurality of first driving switches installed at a first side of the display panel, a plurality of second switches installed at a second side of the display panel, a plurality of first data lines, a plurality of second data lines, a plurality of scan lines, and a plurality of pixels. Each of the first driving switches includes a first input end and a plurality of first output ends. Each of the second driving switches includes a second input end and a plurality of second output ends. The first data lines are electrically connected to the first output ends. The second data lines are electrically connected to the second output ends. The plurality of pixels are electrically connected to the plurality of first data lines, second data lines and scan lines for displaying images. The first data lines and the second data lines are arranged interlacedly. | 05-23-2013 |
20130155035 | METHOD FOR DRIVING PIXEL CIRCUITS - A method for driving a pixel circuit, which is adapted to drive a first pixel circuit coupled to a first gate line and a second pixel circuit coupled to a second gate line, is disclosed. The first pixel circuit receives display data before the second pixel circuit does. The method provides only one first enable pulse to the first gate line in a frame, and provides a second enable pulse and a third enable pulse to the second gate line in the same frame. The starting time of the second enable pulse is in an enabled time period of the first enable pulse, and the enabled time period of the third enable pulse is after the enabled time periods of the first and second enable pulses. | 06-20-2013 |
20140132651 | DISPLAY AND METHOD OF GENERATING AN IMAGE WITH UNIFORM BRIGHTNESS - A display includes a plurality of pixels, a plurality of scan lines and a plurality of data lines. Each pixel includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel. The scan lines and the data lines are coupled to the pixels. Two color sub-pixels in the same row coupled to the same data line are coupled to different scan lines, and all of the second color sub-pixels in the same row are coupled to the same scan line. | 05-15-2014 |
Yu-Min Hung, Hsin-Chu TW
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20100149836 | BACKLIGHT MODULE - A holder is disposed at a side of a back light module adjacent to a light incident side of a light guide plate (LGP). A light source module is fixed on a wall of the holder that faces the light incident side. A holder engager on a side wall of the LGP engages with an LGP retainer of the holder. When the LGP expands or contracts due to changes of temperature, the holder and the light source module move with the side of the LGP, thereby a gap between the light source module and the light incident side is maintained and the luminance of the backlight module is stabilized. | 06-17-2010 |
20130056769 | LIGHT EMITTING DIODE MODULE AND DISPLAY DEVICE USING THE SAME LIGHT EMITTING DIODE MODULE - A light emitting diode (LED) module and a display device adopting the same LED module are provided. The LED module includes a circuit substrate, a LED chip, a connector and a conductive line. The LED chip has at least three pins, and the LED chip is fixed on the circuit substrate through the pins, wherein one of the pins is defined as a no connection (NC) pin. The connector includes a non-conductive housing, at least one fixing pin and a conductor. The fixing pin is connected to the non-conductive housing, and the non-conductive housing is fixed on the circuit substrate through the said at least one fixing pin. A part of the non-conductive housing is covered with the conductor. The conductive line is disposed on the circuit substrate and is electrically connected between the conductor and the NC pin. | 03-07-2013 |
Yung-Ching Hung, Hsin-Chu TW
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20130027599 | PROJECTION SYSTEM AND IMAGE PROCESSING METHOD THEREOF - A projection system and an image processing method thereof are provided. The system includes a projector module, a photography module and a processing module. The projector module projects a first image frame to an object surface. The photography module photographs the object surface to derive a second image frame including the first image frame and an indication point, wherein the indication point is formed by light projected on the object surface by an external device. The processing module analyzes the second image frame to derive coordinate of the indication point in the second image frame, derives coordinate of at least a feature point of the first image frame in the second image frame according to a linear-approximation method, and transforms the coordinates of the indication point in the second image frame to the coordinates in the first image frame by using two-dimensional coordinate transformation equations. | 01-31-2013 |
20130278620 | METHOD OF STORING VIDEOS AND PORTABLE DEVICE - The invention is directed to a method of storing videos for a portable device having a buffer memory space and a storage device The method comprises recording a plurality of video frames and storing the video frames into the buffer memory space of the portable device and detecting an event. According to the event, a portion of the video frames recorded from a first predetermined time before the event is detected until the event is detected is restored into the storage device as a plurality of pre-event video frames and, meanwhile, a plurality of post-event video frames is continuously recorded for a second predetermined time after the event is detected and the post-event video frames are stored into the storage device, wherein the storage device is coupled to the portable device. | 10-24-2013 |