Patent application number | Description | Published |
20130244145 | METHOD OF FABRICATING A POLARIZED COLOR FILTER - A method of fabricating a polarized color filter wherein a transparent substrate is provided and coated with a photoresist layer. A wave-shaped mask may then be prepared and a periodic wave-shaped surface may be placed in contact with the photoresist layer, treating the photoresist layer with a primary exposure process. An external force may be applied to the wave-shaped mask, and the transparent substrate or wave-shaped mask by be rotated by a predetermined degree. The photoresist layer may be treated with a secondary exposure process, wherein the photoresist layer is developed in order to obtain a photoresist pattern layer. A metal layer may be coated on the transparent substrate with the photoresist pattern layer. The photoresist pattern layer and the portion of the metal layer on the photoresist pattern layer may then be removed such that the remaining metal layer forms a periodic hole substrate. | 09-19-2013 |
20140131581 | GAS DETECTION SYSTEM AND RADIATION EMITTING DEVICE FOR THE GAS DETECTION SYSTEM - A gas detection system comprising a case having a hollow chamber, a gas input port, a gas output port, a radiation emitting device, and a photo detector. The gas input port may be disposed on the case for a test gas flowing into the chamber. The gas output port may be disposed on the case for the test gas flowing out of the chamber. The radiation emitting device may be disposed on the case and operated in a surface plasmonic mode or a waveguide mode for emitting a narrow bandwidth thermal radiation light source with multi-peak wavelengths into the chamber, wherein the multi-peak wavelengths may comprise a first absorption wavelength and a second absorption wavelength of the test gas. The photo detector may be disposed on the case for detecting light intensity of the light source passing through the chamber to determine the concentration of the test gas. | 05-15-2014 |
20150200348 | PHOTO DETECTOR - A photo detector is disclosed. The photo detector comprises a substrate, a flat metal layer, a dielectric layer, a patterned metal layer, and a semiconductor film. The flat metal layer is formed on the substrate. The dielectric layer is formed on the flat metal layer. The patterned metal layer is, formed on the dielectric layer. The patterned metal layer comprises a first interdigitated electrode and a second interdigitated electrode. The first interdigitated electrode is adjacent to the second interdigitated electrode. The semiconductor film is formed on the dielectric layer and covering the first interdigitated electrode and the second interdigitated electrode. When the semiconductor film receives an incident light, the flat metal layer and the patterned metal layer are operated in a localized surface plasmon mode or a waveguide mode for absorbing a certain narrow bandwidth radiation light of the incident light. Therefore, the electrical conductivity of the semiconductor film is changed and the optical energy absorbed by the photo detector is determined. | 07-16-2015 |
Patent application number | Description | Published |
20080203555 | Universal substrate and semiconductor device utilizing the substrate - A universal substrate and a semiconductor device utilizing the substrate are disclosed in the present invention. The universal substrate mainly comprises a plurality of inner pads and a plurality of outer pads. A plurality of bifurcate wirings and a plurality of fuses are formed on a surface of the substrate. The fuses are connected with the bifurcate wirings in series. By the bifurcate wirings and the fuses, each of the inner pads is electrically connected to all of the outer pads to provide optional electrical disconnections therebetween. Accordingly, the universal substrate can be utilized for connecting chips having various serial arrangements of bonding pads without replacing or manufacturing another substrate. | 08-28-2008 |
20110133327 | SEMICONDUCTOR PACKAGE OF METAL POST SOLDER-CHIP CONNECTION - A semiconductor package with MPS-C2 configuration is revealed, primarily comprising a substrate and a chip. A plurality of leads covered by a solder mask having a rectangular slot disposed on the top surface of the substrate to expose parts of the leads. A plurality of metal pillars are disposed on the active surface of the chip. A patterned plating layer is partially formed on the exposed portions of the leads located inside the slot to form a plurality of plating-defined fingers. Therefore, the soldering area of the solder on the leads can be constrained without exceeding the patterned plating layer to avoid issue of excessive solder ability. | 06-09-2011 |
20110156238 | SEMICONDUCTOR PACKAGE HAVING CHIP USING COPPER PROCESS - A semiconductor package having chip using copper process is revealed. A chip using copper process is disposed on a substrate. The substrate has a core layer, a copper circuitry with connecting pads, a patterned diffusion barrier, and a solder mask. The copper circuitry is formed on the core layer. The patterned diffusion barrier has such a pattern identical to the one of the copper circuitry that an upper surface of the copper circuitry is completely covered. The substrate further has a bonding layer formed on a portion of the patterned diffusion barrier inside the solder mask's opening. Therefore, diffusion of copper ions from the copper circuitry of the substrate to the active surface of the chip can be avoided to prevent function failure of the chip. | 06-30-2011 |
20110215466 | FLIP CHIP PACKAGE MAINTAINING ALIGNMENT DURING SOLDERING - Disclosed is a flip chip package maintaining alignment during soldering, primarily comprising a chip and a substrate. A plurality of bumps and at least an extruded alignment key are disposed on the active surface of the chip. The substrate has a plurality of bonding pads and at least an alignment base where the alignment base has a concaved alignment pattern corresponding to the extruded alignment key. When the chip is disposed on the substrate, the extruded alignment key is embedded into the concaved alignment pattern to achieve accurately align the bumps to the corresponding bonding pads. Therefore, even with the mechanical misalignment due to the accuracy of flip-chip die bonders and the transportation during reflow processes, the bumps of a chip still can accurately align to the bonding pads of the substrate to achieve accurate soldering which is especially beneficial to the mass production of MPS-C2 products. | 09-08-2011 |
20110215467 | METAL POST CHIP CONNECTING DEVICE AND METHOD FREE TO USE SOLDERING MATERIAL - A metal post chip connecting device without soldering materials is revealed, primarily comprising a chip and a substrate. A plurality of metal pillars are disposed on and extruded from a surface of the chip where each metal pillar has an end surface and two corresponding parallel sidewalls. The substrate has an upper surface and a plurality of bonding pads disposed on the upper surface where each bonding pad has a concaved bottom surface and two corresponding concaved sidewalls. The chip is bonded onto the upper surface of the substrate through heat, pressure, and ultrasonic power so that the end surfaces of the metal pillars self-solder to the concaved bottom surfaces and two parallel sidewalls of the metal pillars partially self-solder to two concaved sidewalls to form U-shape cross-sections of metal bonding between the metal pillars and the bonding pads. Therefore, there is no need for the conventional solder paste as chip connection to increase conductivity of the soldering points, especially, to save the soldering cost for MPS-C2 products and to greatly enhance the bonding strength of the soldering points. The manufacturing method of the above described metal post chip connecting device is also revealed. | 09-08-2011 |
Patent application number | Description | Published |
20080203553 | Stackable bare-die package - A stackable bare-die package primarily comprises a substrate, a chip, a plurality of bonding wires and an encapsulant. The substrate has a slot where a step is formed inside the slot where a plurality of inner fingers are disposed on the step. A plurality of outer pads are disposed on the bottom surface and a plurality of transfer pads on the top surface. The chip is disposed on the top surface and is electrically connected to the inner fingers by a plurality of bonding wires passing through the slot. An encapsulant is formed inside the slot to encapsulate the bonding wires. There is a height difference between the step and the bottom surface so that the loop height of the bonding wires will not exceed the bottom surface. Therefore, when stacking the stackable bare-die packages, the exposed back surface of the chip will not be touched nor stressed to avoid die crack issues. | 08-28-2008 |
20080265389 | Substrate for multi-chip stacking, multi-chip stack package utilizing the substrate and its applications - A substrate for multi-chip stacking and a multi-chip stack package utilizing the substrate and its applications are disclosed. The substrate comprises a first wire-bonding finger, a second wire-bonding finger, a trace configured for electrical transmission and a loop wiring on a same surface. The first wire-bonding finger and the second wire-bonding finger are adjacent each other and to a die-attaching area of the substrate. The loop wiring connects the first wire-bonding finger with the second wire-bonding finger in series and connected to the trace. The loop wiring can be selectively broken or not when at least two chips are stacked on the die-attaching area and electrically connected to the first and second wire-bonding fingers respectively. Accordingly, the chips can operate respectively and independently without mutual interference if one of the chips is fail. Moreover, there is merit to apply the multi-chip stack package utilizing the substrate because it can be repaired after molding and without removing any bonding wire during semiconductor packaging processes. | 10-30-2008 |
20100155937 | Wafer structure with conductive bumps and fabrication method thereof - A wafer structure with conductive bumps and fabrication method thereof are disclosed herein. Conductive bumps are later converted into conductive balls. A central area and a marginal area are defined on the wafer. To achieve heights among conductive balls formed on the wafer structure, the sizes (can be but not limited to one) of under bump metallurgy (UBM) layer blocks in the central area are smaller than that in the marginal area. The fabrication procedure for forming under bump metallurgy layer blocks of different size includes depositing a photoresist layer on the metallurgy layer and pattern the photoresist with a photomask of smaller opening area for the central area than for the marginal area, and removing the photoresist layer and the portion of metallurgy layer under the photoresist layer. | 06-24-2010 |
20110230012 | METHOD FOR FILLING MULTI-LAYER CHIP-STACKED GAPS - A method for filling multi-layer chip-stacked gaps is revealed, primarily comprising the steps as below. Firstly, a chip-stacked assembly is provided, comprising a substrate and a plurality of chips vertically stacked on the substrate where at least a first underfilling gap is formed between each two adjacent ones of the stacked chips with a height difference from the substrate. Then, the chip-stacked assembly is flipped and dipped into an underfilling material where the underfilling material is disposed in a storage tank in a flowing state to completely fill the first underfilling gap. Then, the chip-stacked assembly is taken out. Finally, the chip-stacked assembly is heated to cure the underfilling material filled in the first underfilling gap. Accordingly, multi-layer chip-stacked gaps with different heights can be simultaneously filled at one single step. The conventional underfilling difficulty of multi-layer chip-stacked gaps can be solved leading to higher productivity. | 09-22-2011 |
20150091154 | SUBSTRATELESS PACKAGES WITH SCRIBE DISPOSED ON HEAT SPREADER - Disclosed is a substrateless semiconductor package having a plurality of scribe lines formed on a heat spreader, primarily comprising the heat spreader, a chip disposed on the heat spreader and an encapsulant. Formed on a thermally dissipating surface of the heat spreader are a plurality of scribe line grooves with a plurality of openings formed inside to penetrate through the die-attaching surface of the heat spreader. The chip is disposed on the die-attaching surface and the encapsulant is formed on the die-attaching surface to encapsulate a first surface of the chip on which a plurality of external pads are formed Without being covered by the encapsulant. Therein, the encapsulant is filled in the scribe line grooves via the openings so that a scribe line pattern exposed from the thermally dissipating surface is formed. | 04-02-2015 |
Patent application number | Description | Published |
20090261427 | MOS P-N JUNCTION DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A MOS P-N junction diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. The method for manufacturing such diode device includes several ion-implanting steps. After the gate structure is formed by isotropic etching using a patterned photo-resist layer as a mask, an ion-implanting step is performed using the patterned photo-resist layer as a mask to form a deeper doped sub-region. Then, another ion-implanting step is performed using the gate structure as a mask to form a shallower doped sub-region between the gate structure and the deeper doped sub-region. The formed MOS P-N junction diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance. | 10-22-2009 |
20090261428 | MOS P-N JUNCTION SCHOTTKY DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A MOS P-N junction Schottky diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. An ohmic contact and a Schottky contact are formed at different sides of the gate structure. The method for manufacturing such diode device includes several ion-implanting steps to form several doped sub-regions with different implantation depths to constitute the doped regions. The formed MOS P-N junction Schottky diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance. | 10-22-2009 |
20100327288 | TRENCH SCHOTTKY DIODE AND METHOD FOR MANUFACTURING THE SAME - A trench Schottky diode and its manufacturing method are provided. The trench Schottky diode includes a semiconductor substrate having therein a plurality of trenches, a gate oxide layer, a polysilicon structure, a guard ring and an electrode. At first, the trenches are formed in the semiconductor substrate by an etching step. Then, the gate oxide layer and the polysilicon structure are formed in the trenches and protrude above a surface of the semiconductor substrate. The guard ring is formed to cover a portion of the resultant structure. At last, the electrode is formed above the guard ring and the other portion not covered by the guard ring. The protruding gate oxide layer and the protruding polysilicon structure can avoid cracks occurring in the trench structure. | 12-30-2010 |
20110084353 | TRENCH SCHOTTKY RECTIFIER DEVICE AND METHOD FOR MANUFACTURING THE SAME - A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage. | 04-14-2011 |
20140077328 | TRENCH SCHOTTKY RECTIFIER DEVICE AND METHOD FOR MANUFACTURING THE SAME - A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage. | 03-20-2014 |
20140295628 | MOS P-N JUNCTION SCHOTTKY DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A MOS P-N junction Schottky diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. An ohmic contact and a Schottky contact are formed at different sides of the gate structure. The method for manufacturing such diode device includes several ion-implanting steps to form several doped sub-regions with different implantation depths to constitute the doped regions. The formed MOS P-N junction Schottky diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance. | 10-02-2014 |
Patent application number | Description | Published |
20120261751 | RECTIFIER WITH VERTICAL MOS STRUCTURE - A method for manufacturing a rectifier with a vertical MOS structure is provided. A first trench structure and a first mask layer are formed at a first side of the semiconductor substrate. A second trench structure is formed in the second side of the semiconductor substrate. A gate oxide layer, a polysilicon structure and a metal sputtering layer are sequentially formed on the second trench structure. The rectifier further includes a wet oxide layer and a plurality of doped regions. The wet oxide layer is formed on a surface of the first multi-trench structure and in the semiconductor substrate. The doping regions are formed on a region between the semiconductor substrate and the second trench structure, and located beside the mask layer. The metal sputtering layer is formed on the first mask layer corresponding to the first trench structure. | 10-18-2012 |
20130122695 | TRENCH SCHOTTKY DIODE AND METHOD FOR MANUFACTURING THE SAME - A trench Schottky diode and its manufacturing method are provided. The trench Schottky diode includes a semiconductor substrate having therein a plurality of trenches, a gate oxide layer, a polysilicon structure, a guard ring and an electrode. At first, the trenches are formed in the semiconductor substrate by an etching step. Then, the gate oxide layer and the polysilicon structure are formed in the trenches and protrude above a surface of the semiconductor substrate. The guard ring is formed to cover a portion of the resultant structure. At last, the electrode is formed above the guard ring and the other portion not covered by the guard ring. The protruding gate oxide layer and the protruding polysilicon structure can avoid cracks occurring in the trench structure. | 05-16-2013 |
20130130459 | MOS P-N JUNCTION DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A MOS P-N junction diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. The method for manufacturing such diode device includes several ion-implanting steps. After the gate structure is formed by isotropic etching using a patterned photo-resist layer as a mask, an ion-implanting step is performed using the patterned photo-resist layer as a mask to form a deeper doped sub-region. Then, another ion-implanting step is performed using the gate structure as a mask to form a shallower doped sub-region between the gate structure and the deeper doped sub-region. The formed MOS P-N junction diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance. | 05-23-2013 |
20130168779 | MOS P-N JUNCTION DIODE WITH ENHANCED RESPONSE SPEED AND MANUFACTURING METHOD THEREOF - A MOS P-N junction diode includes a semiconductor substrate, a mask layer, a guard ring, a gate oxide layer, a polysilicon structure, a central conductive layer, a silicon nitride layer, a metal diffusion layer, a channel region, and a metal sputtering layer. For manufacturing the MOS P-N junction diode, a mask layer is formed on a semiconductor substrate. A gate oxide layer is formed on the semiconductor substrate, and a polysilicon structure is formed on the gate oxide layer. A guard ring, a central conductive layer and a channel region are formed in the semiconductor substrate. A silicon nitride layer is formed on the central conductive layer. A metal diffusion layer is formed within the guard ring and the central conductive layer. Afterwards, a metal sputtering layer is formed, and the mask layer is partially exposed. | 07-04-2013 |
20130228891 | MULTI-TRENCH TERMINATION STRUCTURE FOR SEMICONDUCTOR DEVICE AND MANUFACTURING MEHTOD THEREOF - A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device. | 09-05-2013 |
20130249043 | WIDE TRENCH TERMINATION STRUCTURE FOR SEMICONDUCTOR DEVICE - A wide trench termination structure for semiconductor device includes a wide trench structure defined on a semiconductor substrate and having a width larger than that of narrow trench structures on an active region of the semiconductor device, an oxide layer arranged on an inner face of the wide trench structure, at least one trench polysilicon layer arranged on the oxide layer and on inner sidewall of the wide trench structure, a metal layer arranged on the oxide layer not covered by the trench polysilicon layer and on the trench polysilicon layer, and a field oxide layer arranged on the semiconductor substrate and outside the wide trench structure. | 09-26-2013 |
20140004681 | TRENCH ISOLATION MOS P-N JUNCTION DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME | 01-02-2014 |
20140030882 | MANUFACTURING METHOD OF MULTI-TRENCH TERMINATION STRUCTURE FOR SEMICONDUCTOR DEVICE - A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device. | 01-30-2014 |
20140131793 | RECTIFIER WITH VERTICAL MOS STRUCTURE - A method for manufacturing a rectifier with a vertical MOS structure is provided. A first trench structure and a first mask layer are formed at a first side of the semiconductor substrate. A second trench structure is formed in the second side of the semiconductor substrate. A gate oxide layer, a polysilicon structure and a metal sputtering layer are sequentially formed on the second trench structure. The rectifier further includes a wet oxide layer and a plurality of doped regions. The wet oxide layer is formed on a surface of the first multi-trench structure and in the semiconductor substrate. The doping regions are formed on a region between the semiconductor substrate and the second trench structure, and located beside the mask layer. The metal sputtering layer is formed on the first mask layer corresponding to the first trench structure. | 05-15-2014 |
20140308799 | TRENCH ISOLATION MOS P-N JUNCTION DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time. | 10-16-2014 |
20150050791 | METHOD FOR MANUFACTURING RECTIFIER WITH VERTICAL MOS STRUCTURE - A method for manufacturing a rectifier with a vertical MOS structure is provided. A first multi-trench structure and a first mask layer are formed at a first side of the semiconductor substrate. A second multi-trench structure is formed in the second side of the semiconductor substrate. A gate oxide layer, a polysilicon structure and a metal sputtering layer are sequentially formed on the second multi-trench structure. The rectifier further includes a wet oxide layer and a plurality of doped regions. The wet oxide layer is formed on a surface of the first multi-trench structure and in the semiconductor substrate. The doping regions are formed on a region between the semiconductor substrate and the second multi-trench structure, and located beside the mask layer. The metal sputtering layer is formed on the first mask layer corresponding to the first multi-trench structure. | 02-19-2015 |
20150054115 | TRENCH SCHOTTKY RECTIFIER DEVICE AND METHOD FOR MANUFACTURING THE SAME - A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage. | 02-26-2015 |
20150084136 | MOS P-N JUNCTION DIODE WITH ENHANCED RESPONSE SPEED AND MANUFACTURING METHOD THEREOF - A MOS P-N junction diode includes a semiconductor substrate, a mask layer, a guard ring, a gate oxide layer, a polysilicon structure, a polysilicon oxide layer, a central conductive layer, ion implantation layer, a channel region, and a metallic sputtering layer. For manufacturing the MOS P-N junction diode, a mask layer is formed on a semiconductor substrate. A gate oxide layer is formed on the semiconductor substrate, and a polysilicon structure is formed on the gate oxide layer, and a polysilicon oxide layer formed on the polysilicon structure. A guard ring, a central conductive layer and a channel region are formed in the semiconductor substrate. An ion implantation layer is formed within the guard ring and the central conductive layer. Afterwards, a metallic sputtering layer is formed, and the mask layer is partially exposed. | 03-26-2015 |
20150279980 | HIGH-PERFORMANCE REVERSE-CONDUCTION FIELD-STOP (RCFS) INSULATED GATE BIPOLAR TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A high-performance reverse-conduction field-stop (RCFS) insulated gate bipolar transistor (IGBT) includes a first conductive type substrate, a plurality of trenches defined on a bottom face of the substrate, a plurality of first conductive type doping regions formed on bottom face of the trenches, a second conductive type doping region formed on bottom face of the substrate, and a first conductive type field stop doping region formed in the substrate and separated from the bottom face of the substrate by a field stop depth, where the field stop depth is larger than a depth of the trench. Due to a separation between the first conductive type doping regions and the second conductive type doping region, Zener diode can be prevented from forming on bottom side of the substrate and the performance of IGBT can be accordingly enhanced. | 10-01-2015 |
20160071950 | TRENCH SCHOTTKY RECTIFIER DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for fabricating a trench Schottky rectifier device is provided. At first, a plurality of trenched are formed in a substrate of a first conductivity type. An insulating layer is formed on sidewalls of the trenches. Then, an ion implantation procedure is performed through the trenches to form a plurality of doped regions of a second conductivity type under the trenches. Subsequently, the trenches are filled with conductive structure such as poly-silicon structure or tungsten structure. At last, an electrode overlying the conductive structure and the substrate is formed. Thus, a Schottky contact appears between the electrode and the substrate. Each doped region and the substrate will form a PN junction to pinch off current flowing toward the Schottky contact to suppress the current leakage in a reverse bias mode. | 03-10-2016 |