Patent application number | Description | Published |
20150130744 | CARRIER SIGNAL DETECTION APPARATUS, TOUCH CONTROL DETECTION APPARATUS AND DETECTION METHODS THEREOF - A carrier signal detection apparatus, a touch control apparatus and detection methods thereof are provided. The carrier signal detection apparatus includes an analog to digital converting (ADC) apparatus and a filter. The ADC apparatus receives an analog input signal and converts the analog input signal to a digital signal. The filter receives the digital signal and accumulates the digital signal according to a delay time for generating a carrier signal detection result. | 05-14-2015 |
20150309603 | PHASE COMPENSATION METHOD FOR MULTI-SCAN IN TOUCH SENSING SYSTEM AND PHASE COMPENSATION CIRCUIT THEREOF - A phase compensation method for multi-scan in touch sensing system is provided. The phase compensation method includes the following steps. A plurality of carrier signals are received, and a demodulating operation is preformed on each of the carrier signals to obtain a first component signal and a second component signal of each of the carrier signals. An inverse matrix operation is respectively preformed on the first component signal and the second component signal both demodulated by the demodulating operation. A signal mixing operation is preformed on the first component signal and the second component signal both processed by the inverse matrix operation to obtain raw data of each of the carrier signals. Furthermore, a phase compensation circuit applying afore-said phase compensation method is also provided. | 10-29-2015 |
20150338448 | NOISE DETECTION DEVICE, SYSTEM AND METHOD - A noise detection device, system, and a method of detecting noise signals are disclosed. The noise detection device includes a drive circuit, a sense circuit and a controller. The drive circuit drives a plurality of drive lines having a first polarity pattern and a second polarity pattern, wherein an operation of the first polarity pattern and the second polarity pattern substantially equals zero over a predetermined time period. The sense circuit senses a plurality of sense signals from at least one sense line during the predetermined time period. The controller derives a magnitude of a noise signal from the at least one sense line according to the sense signals. | 11-26-2015 |
20150338992 | TOUCH APPARATUS, TOUCH CONTROLLER THEREOF AND NOISE DETECTION METHOD - A noise detection method including the following steps is provided. During different time periods, plural sets of driving signals are respectively transmitted to driving lines of the touch panel to drive sensing lines of the touch panel to generate plural sets of sensing signals. The plural sets of sensing signals are respectively received and calculated to obtain plural sets of summation signals. One set of summation signals includes first summation signals, and another set of summation signals includes second summation signals. A part or all of the first summation signals is replaced by the second summation signals. A signal value of a combination of the first and the second summation signals is calculated to obtain a summation thereof. The summation of the signal value of the combination is smaller than a summation of a signal values of the first summation signals before recombination. | 11-26-2015 |
20150338993 | Method of Determining Touch Event in Touch Detection System - A method of determining a touch event in a touch detection system includes transmitting at least one driving signal to a touch panel of the touch detection system; receiving a sensing signal corresponding to the driving signal from the touch panel; determining whether the touch event occurs by performing an initial digital operation on the sensing signal; determining whether the sensing signal is interfered with by a noise signal; and performing an entire determination on the sensing signal when the touch event is determined to occur or the sensing signal is determined to be interfered with by the noise signal. | 11-26-2015 |
Patent application number | Description | Published |
20130183625 | PATTERNED GRAPHENE FABRICATION METHOD - A method for fabricating patterned graphene structures, which adopts a photolithographic etching process to fabricate patterned graphene structures, comprises steps: providing a substrate; forming a catalytic layer on the substrate; forming a carbon layer on the catalytic layer; heating the carbon layer to a synthesis temperature to form a graphene layer. A photolithographic etching process is performed on the catalytic layer before formation of the carbon layer. Alternatively, a photolithographic etching process is performed on the carbon layer before heating. Alternatively, a photolithographic etching process is performed on the graphene layer after heating. Compared with the laser etching process, the photolithographic etching process is suitable to fabricate large-area patterned graphene structures and has advantages of high productivity and low cost. | 07-18-2013 |
20130221268 | THERMALLY-CONDUCTIVE PASTE - A thermally-conductive paste comprises a carrier, at least one graphene platelet, and a plurality of packing materials. The graphene platelets and the packing materials are dispersed in the carrier. At least a portion of the packing materials contact the surface of the graphene platelet. The graphene platelet has a very high thermal conductivity coefficient and a characteristic 2D structure and thus can provide continuous and long-distance thermal conduction paths for the thermally-conductive paste. Thereby is greatly improved the thermal conduction performance of the thermally-conductive paste. | 08-29-2013 |
20140106153 | GRAPHENE PLATELET FABRICATION METHOD AND GRAPHENE PLATELET FABRICATED THEREBY - The present invention discloses a graphene platelet fabrication method, which comprises Step (A): providing a highly-graphitized graphene having a graphitization degree of 0.8-1.0; and Step (B): providing a shear force acting on the highly-graphitized graphene to separate the highly-graphitized graphene into graphene platelets, wherein the graphene platelets have a length of 10-500 μm and a width of 10-500 μm and have a single-layer or multi-layer structure. The present invention also discloses a graphene platelet fabricated according to the abovementioned method. | 04-17-2014 |
20140131757 | HEAT CONDUCTING COMPOSITE MATERIAL AND LIGHT-EMITTING DIODE HAVING THE SAME - A heat conducting composite material includes a matrix and a graphene sheet. The graphene sheet has a two-dimensional planar structure, and a basal plane of the graphene sheet has a lateral size between 0.1 nm and 100 nm such that the graphene sheet has a quantum well structure. When radiation energy passes through the heat conducting composite material, the radiation energy is converted into infrared light by the quantum well structure of the graphene sheet to achieve high radiating efficiency. A light-emitting diode (LED) having the heat conducting composite material and capable of achieving a heat dissipation effect is further disclosed. | 05-15-2014 |
Patent application number | Description | Published |
20140094009 | SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERCONNECTS - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant. | 04-03-2014 |
20140256099 | METHOD OF CONVERTING BETWEEN NON-VOLATILE MEMORY TECHNOLOGIES AND SYSTEM FOR IMPLEMENTING THE METHOD - A method of designing a charge trapping memory array including designing a floating gate memory array layout. The floating gate memory layout includes a first type of transistors, electrical connections between memory cells of the floating gate memory array layout, a first input/output (I/O) interface, a first type of charge pump, and an I/O block. The method further includes modifying the floating gate memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes determining an operating voltage difference between the I/O block and the second type of transistors. The method further includes modifying the floating gate memory array layout, using the processor, to modify the first charge pump based on the determined operating voltage difference. | 09-11-2014 |
20150095868 | METHOD OF CONVERTING BETWEEN NON-VOLATILE MEMORY TECHNOLOGIES AND SYSTEM FOR IMPLEMENTING THE METHOD - A method of designing a charge trapping memory array including designing a floating gate memory array layout. The floating gate memory layout includes a first type of transistors, electrical connections between memory cells of the floating gate memory array layout, a first input/output (I/O) interface, a first type of charge pump, and an I/O block. The method further includes modifying the floating gate memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes determining an operating voltage difference between the I/O block and the second type of transistors. The method further includes modifying the floating gate memory array layout, using the processor, to modify the first charge pump based on the determined operating voltage difference. | 04-02-2015 |
20160034629 | METHOD OF CONVERTING BETWEEN NON-VOLATILE MEMORY TECHNOLOGIES AND SYSTEM FOR IMPLEMENTING THE METHOD - A method of designing a charge trapping memory array includes designing a memory array layout. The memory array layout includes a first type of transistors; electrical connections between memory cells of the memory array layout; a first input/output (I/O) interface; and a charge pump. The method further includes modifying the memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes modifying the memory array layout, using the processor, to modify the charge pump based on an operating voltage of the second type of transistors. | 02-04-2016 |