Huang, Zhubei City
Chang-Chieh Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20150186224 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - A data storage device and a flash memory control method with a power recovery design. A microcontroller is configured to allocate a flash memory to provide a first block from the blocks to work as a run-time write block for reception of write data. During a power recovery process due to an unexpected power-off event that interrupted write operations on the first block, the microcontroller is configured to allocate the flash memory to provide a second block from the blocks for complete data recovery of the first block and to replace the first block as the run-time write block. | 07-02-2015 |
20150186225 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - A data storage device with flash memory and a flash memory control method are disclosed, in which the flash memory includes multi-level cells (MLCs) and single-level cells (SLCs). A microcontroller is configured to establish a first physical-to-logical address mapping table (F2H table) in a random access memory (RAM) for a first run-time write block containing MLCs. The microcontroller is further configured to establish a second F2H table in the RAM for a second run-time write block containing SLCs. When data that was previously stored in the first run-time write block with un-uploaded mapping information in the first F2H table is updated into the second run-time write block, the microcontroller is configured to update a logical-to-physical address mapping table (H2F table) in accordance with the first F2H table. The H2F table is provided within the flash memory. | 07-02-2015 |
20150186261 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - A data storage device with flash memory and a flash memory control method are disclosed, which upload the physical-to-logical address mapping information of one block to the flash memory section by section. A microcontroller is configured to allocate a flash memory to provide a first run-time write block. Between a first write operation and a second write operation of the first run-time write block, the microcontroller updates a logical-to-physical address mapping table in accordance with just part of a first physical-to-logical address mapping table. The logical-to-physical address mapping table is provided within the flash memory. The first physical-to-logical address mapping table is established in the random access memory to record logical addresses corresponding to physical addresses of one block. | 07-02-2015 |
20150186262 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - A data storage device with flash memory and a flash memory control method are disclosed, in which the flash memory includes multi-level cells (MLCs) and single-level cells (SLCs). A microcontroller is configured to use the random access memory to cache data issued from the host before writing the data into the flash memory. The microcontroller is further configured to allocate the blocks of the flash memory to provide a first run-time write block containing multi-level cells and a second run-time write block containing single-level cells. Under control of the microcontroller, each physical page of data uploaded from the random access memory to the first run-time write block contains sequential data, and random data cached in the random access memory to form one physical page is written into the second run-time write block. | 07-02-2015 |
20150186263 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - A data storage device and a flash memory control method with high erasing efficiency are disclosed. A microcontroller is configured to maintain a plurality of logical-to-physical address mapping tables and a link table on a flash memory to record mapping information between a host and the flash memory. The link table indicates positions of the plurality of logical-to-physical address mapping tables, and each entry in the link table corresponds to one logical-to-physical address mapping table. When erasing user data of logical addresses corresponding to N logical-to-physical address mapping tables, the microcontroller is configured to invalidate N entries corresponding to the N logical-to-physical address mapping tables in the link table, where N is an integer. | 07-02-2015 |
20150186264 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - A data storage device and a flash memory control method with high efficiency are disclosed. The random access memory of the data storage device is allocated to provide a collection and update area for logical-to-physical address mapping tables that correspond to logical addresses recorded into the physical-to-logical address mapping table. When recording a logical address corresponding to a new logical-to-physical address mapping table that has not appeared in the collection and update area into the physical-to-logical address mapping table, the microcontroller of the data storage device is configured to collect the new logical-to-physical address mapping table into the collection and update area and perform an update of the new logical-to-physical address mapping table within the collection and update area. | 07-02-2015 |
Chao-Ping Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20140176211 | SIGNAL COUPLING CIRCUIT AND ASSOCIATED METHOD - A signal coupling circuit for generating an output signal according to an input signal is provided. The signal coupling circuit includes: a coupling capacitor, configured to generate a coupling signal according to the input signal; a clock generating circuit, configured to generate a clock and determine a duty cycle of the clock by the coupling capacitor; a discharge circuit, configured to intermittently discharge the coupling capacitor according to the duty cycle of the clock; and an output circuit, coupled to the coupling capacitor, for generating the output signal according to the coupling signal. | 06-26-2014 |
Cheng-Houng Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20130136290 | EARPHONE WITH TUNABLE LOW PITCH - An earphone with tunable low pitch comprises a main member and a stirring member, wherein the main member has a chamber inside receiving a loud speaker, a low pitch room formed between the main member and the loud speaker, at least a fixing air hole provided at the rear side of the main member, a high pitch room formed between the front side of the main member and the loud speaker, at least a regulative air hole is provided at the high pitch room; the stirring member, which is pivotally joined to the pivot hole, is designed as a disk to close the regulative air hole or as airflow baffles to close corresponding airflow passages gradually such that the regulative air hole or the airflow passages can be partly or fully blocked by the stirring member to change the speed of the air entering or leaving the high pitch room and result in good low frequency resonant effect. | 05-30-2013 |
Chiao-Chi Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20110276730 | PACKET BASED DATA TRANSFER SYSTEM AND METHOD FOR HOST-SLAVE INTERFACE - In a host-slave data transfer system, the slave device receives packet based data from an external device and stores the packet content in a buffer as data segments. The slave merges a plurality of data segments into data streams and transmits the data streams to the host. The host uses direct memory access (DMA) to unpack the data stream from the slave into individual data segments without memory copy. To enable the host to set up DMA, the slave transmits information regarding sizes of the data segments to the host beforehand via an outband channel, e.g. by transmitting the size information in headers and/or tailers inserted into previous data streams. The host utilizes the data segment size information to program descriptor tables, such that each descriptor in the descriptor tables causes one data segment in the data stream to be stored in the system memory of the host. | 11-10-2011 |
Chiao-Yi Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20150335274 | PHYSIOLOGICAL SIGNALS DETECTION DEVICE - A physiological signals detection device has a light source connecting to a control unit, a light detector and a processing unit. The light detector has a pixel sensor array including multiple light sensing elements. The light source emits light through a lens to the human body to generate reflected light. The light detector receives the reflected light to generate a sensing signal. Since the light sensing elements respectively receive different reflected light from different directions, the light sensing elements receiving reflected light from the noise are easily selected and eliminated from calculating the physiology value. Therefore, the calculated physiology value is more accurate. | 11-26-2015 |
Chien-Hua Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20120123745 | Adaptive Content-aware Aging Simulations - A system and method for simulating aging parameters of a System-on-Chip (SoC) integrated circuit is disclosed. A SoC integrated circuit is first divided into a plurality of blocks in accordance with the nature or the operating conditions of each block. The simulation of a digital circuit based block is performed by a static timing analyzer. The simulation of a mixed signal based block is performed by first employing a fresh device model to obtain relevant operation conditions, such as node voltages. Based upon the operation conditions and reliability characterization data, parameters degradation calculators assess aging characteristic factors of each block. In a subsequent simulation, a circuit simulator calculates the design corners of a SoC chip based upon the characteristic factors of each block. | 05-17-2012 |
20130221534 | Through Silicon Via Layout Pattern - A semiconductor device comprises a substrate with a first side and a second side, wherein a plurality of active circuits are formed adjacent to the first side of the substrate and a plurality of through silicon vias arranged in a polygon shape and extending from the first side of to the second side, wherein the polygon shape has more than six sides, and wherein each through silicon via is placed at a corresponding apex of the polygon shape. | 08-29-2013 |
Chien-Kai Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20110285036 | OVERLAY MARK ASSISTANT FEATURE - A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector. | 11-24-2011 |
Chi-Hao Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20130210178 | LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A light-emitting device and method for manufacturing the same are described. A method for manufacturing a light-emitting device comprising the steps of: providing a substrate; forming a light-emitting structure on the substrate, wherein the light-emitting structure comprising a plurality of chip areas and a plurality of street areas; forming a conductive structure between the substrate and the light-emitting structure; removing a part of the light-emitting structure in the street areas to expose a sidewall in the chip areas; forming a first passivation layer on the light-emitting structure in the chip areas; and forming a second passivation layer in the street areas, the sidewalls of the light-emitting structure, and the sidewalls of the first passivation layer. | 08-15-2013 |
Chih-Hsiang Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20110147765 | DUMMY STRUCTURE FOR ISOLATING DEVICES IN INTEGRATED CIRCUITS - The present disclosure provides an integrated circuit. The integrated circuit includes a first operational device having a first transistor of a first composition; a second operational device having a second transistor of the first composition; and an isolation transistor disposed between the first and second transistors, the isolation transistor having a second composition different from the first composition. | 06-23-2011 |
20110193175 | LOWER PARASITIC CAPACITANCE FINFET - An integrated circuit device includes a gate region extending above a semiconductor substrate and extending in a first longitudinal direction. A first fin has a first sidewall that extends in a second longitudinal direction above the semiconductor substrate such that the first fin intersects the gate region. A second fin has a second sidewall extending in the second direction above the semiconductor substrate such that the second fin intersects the gate region. A shallow trench isolation (STI) region is formed in the semiconductor substrate between the first and second sidewalls of the first and second fins. A conductive layer disposed over the first insulating layer and over top surfaces of the first and second fins. A first insulating layer is disposed between an upper surface of the STI region and a lower surface of the conductive layer to separate the STI region from the conductive layer. | 08-11-2011 |
20120313167 | SEMICONDUCTOR DEVICE HAVING GRADIENT DOPING PROFILE - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate over a substrate. The method includes performing a first implantation process to form a first doped region in the substrate, the first doped region being adjacent to the gate. The method includes performing a second implantation process to form a second doped region in the substrate, the second doped region being formed farther away from the gate than the first doped region, the second doped region having a higher doping concentration level than the first doped region. The method includes removing portions of the first and second doped regions to form a recess in the substrate. The method includes epitaxially growing a third doped region in the recess, the third doped region having a higher doping concentration level than the second doped region. | 12-13-2012 |
20130109152 | METHOD OF MAKING LOWER PARASITIC CAPACITANCE FINFET | 05-02-2013 |
20130313642 | Semiconductor Device Having Gradient Doping Profile - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate over a substrate. The method includes performing a first implantation process to form a first doped region in the substrate, the first doped region being adjacent to the gate. The method includes performing a second implantation process to form a second doped region in the substrate, the second doped region being formed farther away from the gate than the first doped region, the second doped region having a higher doping concentration level than the first doped region. The method includes removing portions of the first and second doped regions to form a recess in the substrate. The method includes epitaxially growing a third doped region in the recess, the third doped region having a higher doping concentration level than the second doped region. | 11-28-2013 |
Chin-Wen Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20160076959 | PRESSURE SENSOR AND MANUFACTURING METHOD OF THE SAME - A pressure sensor and a manufacturing method of the same are provided. The pressure sensor includes a substrate, a dielectric oxide layer, a first electrode, a dielectric connection layer, and a second electrode. The dielectric oxide layer is formed on the substrate. The first electrode is formed on the dielectric oxide layer. The dielectric connection layer is formed on the first electrode. The second electrode is formed on the dielectric connection layer. The second electrode comprises a patterned conductive layer and a dielectric layer. The patterned conductive layer has a plurality of holes, and the dielectric layer is formed on the patterned conductive layer and covers the inner walls of the plurality of holes. The first electrode, the dielectric connection layer, and the second electrode define a first chamber between the first electrode and the second electrode. | 03-17-2016 |
Chung-Kuang Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20120169302 | METHOLOGY OF ON-CHIP SOFT-START CIRCUITS FOR SWITCHING MODE DC/DC CONVERTER - Methods of a switching mode DC/DC converter are provided in the present invention. The proposed method includes a step of causing a switching frequency of the converter to be operated at a rated value multiplied by a second predetermined value when an output voltage of the converter is not larger than a first predetermined value. | 07-05-2012 |
Chun-Ju Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20100044478 | NANOTIZATION OF MAGNESIUM-BASED HYDROGEN STORAGE MATERIAL - The invention utilizes a carbon nano material to nanotize a magnesium-based hydrogen storage material, thereby forming single or multiple crystals to enhance the surface to volume ratio and hydrogen diffusion channel of the magnesium-based hydrogen storage material. Therefore, the hydrogen storage material has higher hydrogen storage capability, higher absorption/desorption rate, and lower absorption/desorption temperature. | 02-25-2010 |
20140070138 | HYDROGEN STORAGE COMPOSITE MATERIALS AND METHODS OF FORMING THE SAME - A hydrogen storage composite and a method of forming the same are provided. The hydrogen storage composite includes a catalyst mixed with a hydrogen storage base material and a transition metal for catalyzing hydrogen desorption embedded on the surfaces of the hydrogen storage base material and the catalyst. The method includes providing at least one active metal and performing a lengthy time ball mill process to form a catalyst, providing a hydrogen storage base material to mix with the catalyst and performing a lengthy time ball mill process to form a hydrogen storage alloy material, and providing a transition metal for catalyzing hydrogen desorption to mix with the hydrogen storage alloy material and performing a shortened time ball mill process to form a hydrogen storage composite. | 03-13-2014 |
Chun-Yen Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20100165665 | Power supply control circuit and method for sensing voltage in the power supply control circuit - The present invention discloses a power supply control circuit, the power supply providing an output voltage to an output terminal from an input terminal through a transformer having a primary winding and a secondary winding, the power supply control circuit comprising: a power switch electrically connected with the primary winding; a switch control circuit controlling the power switch; and a sensing circuit supplying an output signal to the switch control circuit according to voltage signals obtained from two sides of the primary winding, wherein the sensing circuit includes a setting circuit for deciding the output voltage according to a reference signal. The present invention also relates to a voltage sensing method in the power supply control circuit. | 07-01-2010 |
20130114310 | Power Supply Control Circuit and method for sensing voltage in the power supply control circuit - The present invention discloses a power supply control circuit, the power supply providing an output voltage to an output terminal from an input terminal through a transformer having a primary winding and a secondary winding, the power supply control circuit comprising: a power switch electrically connected with the primary winding; a switch control circuit controlling the power switch; and a sensing circuit supplying an output signal to the switch control circuit according to voltage signals obtained from two sides of the primary winding, wherein the sensing circuit includes a setting circuit for deciding the output voltage according to a reference signal. The present invention also relates to a voltage sensing method in the power supply control circuit. | 05-09-2013 |
Dau-Chen Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20150102792 | VOLTAGE REGULATOR AND CONTROL METHOD THEREOF - A voltage regulator and a control method thereof are provided to dynamically adjust an output voltage. The voltage regulator comprises a plurality of switching transistors and a control circuit. The first end of each switching transistor receives a driving voltage, and the second end of each switching transistor is electrically connected to the end which outputs the output voltage. The input end and the feedback end of the control circuit respectively receive a reference voltage and the output voltage. A plurality of output ends of the control circuit are electrically connected to the control ends of the switching transistors respectively. Switching transistors adjust the output voltage. The control circuit compares the output voltage with the reference voltage, and selectively turns the switching transistors on or off according to the comparison between the output voltage and the reference voltage, to control the output voltage to approach the reference voltage. | 04-16-2015 |
Dong-Liang Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20140043780 | HYBRID PORTABLE POWER SUPPLY - The present invention provides a hybrid portable power supply. In addition to providing emergency power to vehicles, the portable power supply of this invention integrates multiple functions, including lighting, warning, self-test and circuit protection. Moreover, the design of the power supply's housing is compact and aesthetically pleasing, making this power supply highly portable and easy for organizing cables. | 02-13-2014 |
Gang-Le Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20130026381 | DYNAMIC, REAL TIME ULTRAVIOLET RADIATION INTENSITY MONITOR - An apparatus and method for detecting an intensity of radiation in a process chamber, such as an ultraviolet curing process chamber, is disclosed. An exemplary apparatus includes a process chamber having a radiation source therein, wherein the radiation source is configured to emit radiation within the process chamber; a radiation sensor attached to the process chamber; and an optical fiber coupled with the radiation source and the radiation sensor, wherein the optical fiber is configured to transmit a portion of the emitted radiation to the radiation sensor, and the radiation sensor is configured to detect an intensity of the portion of the emitted radiation via the optical fiber. | 01-31-2013 |
Hou-Ju Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20150162258 | Underfill Pattern with Gap - An embodiment is a structure comprising a package, a substrate, and external electrical connectors mechanically and electrically coupling the package to the substrate. The package contains a die. The external electrical connectors are between the package and the substrate. An underfill material is around a periphery region of the package and between the periphery region and the substrate. A gap is between a central region of the package and the substrate, and does not contain the underfill material. The underfill material may seal the gap. The gap may be an air gap. In some embodiments, the underfill material may fill greater than or equal to 10 percent and no more than 70 percent of a volume between the package and the substrate. | 06-11-2015 |
Hui-Chi Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20150140818 | METHODS AND SYSTEMS FOR CHEMICAL MECHANICAL POLISH CLEANING - The present disclosure provides a cleaning unit for a chemical mechanical polishing (CMP) process. The cleaning unit comprises a cleaning solution; a brush configured to scrub a wafer during the CMP process; and a spray nozzle configured to apply the cleaning solution to the wafer when the brush scrubs the wafer during the CMP process. In some embodiments, the spray nozzle includes an inlet where the cleaning solution enters the spray nozzle and an outlet where the cleaning solution exits the spray nozzle. In some embodiments, an inlet area (A | 05-21-2015 |
20150147883 | Post-CMP Cleaning and Apparatus for Performing the Same - A method of performing a post Chemical Mechanical Polish (CMP) cleaning includes picking up the wafer, spinning a cleaning solution contained in a cleaning tank, and submerging the wafer into the cleaning solution, with the cleaning solution being spun when the wafer is in the cleaning solution. After the submerging the wafer into the cleaning solution, the wafer is retrieved out of the cleaning solution. | 05-28-2015 |
Jin-Lin Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20120242411 | OPERATIONAL AMPLIFIER - An operational amplifier providing an output voltage signal to drive a load in response to an input voltage signal is provided. The operational amplifier includes a first input stage and a second input stage, a second stage and an output enable switch. The first input stage provides a first intermediate signal according to the voltages of an input and an output voltage signals in a transitional state. The second input stage provides a second intermediate signal according to the input and the output voltage signals in a steady state. The second stage provides the output voltage signal to an output node according to the first and the second intermediate signals in the transitional and the steady states respectively. The output enable switch is enabled in an output enable period to drive the load with the output voltage signal. | 09-27-2012 |
Juinn-Dar Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20080198784 | Dynamical sequentially-controlled low-power multiplexer device - Multiplexers are basic components widely used in VLSI designs. Switching activities of a multiplexer are one of the most important factors of power consumption. A multiplexer may have some sub-multiplexers. An extra dynamic controller is applied in the present invention to reconfigure control signals for decreasing switching activities of the composed sub-multiplexers. Thus, the power consumption of the multiplexer is reduced to achieve higher power efficiency. | 08-21-2008 |
20110153709 | DELAY OPTIMAL COMPRESSOR TREE SYNTHESIS FOR LUT-BASED FPGAS - A compressor tree synthesis algorithm, named DOCT, which guarantees the delay optimal implementation in LUT-based FPGAs. Given a targeted K-input LUT architecture, DOCT firstly derives a finite set of prime patterns as essential building blocks. Then, it shows that a delay optimal compressor tree can always be constructed by those derived prime patterns via integer linear programming (ILP). Without loss of delay optimality, a post-processing procedure is invoked to reduce the number of demanded LUTs for the generated compressor tree design. DOCT has been evaluated over a broad set of benchmark circuits. The DOCT reduces the depth of the compressor tree and the number of LUTs based on the modern 8-input LUT-based FPGA architecture. | 06-23-2011 |
Jun-Cheng Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20140264742 | Integrated Capacitor - A structure includes first, second, and third conductive leaf structures. The first conductive leaf structure includes a first conductive midrib and conductive veins. The second conductive leaf structure is electrically connected to the first conductive leaf structure, and includes a second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending away from the first conductive midrib. The third conductive leaf structure includes a third conductive midrib between the first conductive midrib and the second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending toward the second conductive midrib. | 09-18-2014 |
Ling-Hsuan Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20150109535 | CONTROL MODULE OF MULTIMEDIA DEVICE AND METHOD FOR CONTROLLING MULTIMEDIA DEVICE TO GENERATE IMAGE DATA REQUIRED BY DISPLAY MODULE - A control module of a multimedia device for generating display data required by a display module is provided. The control module includes: a signal receiving and analyzing unit, configured to receive a first signal to accordingly generate a pre-boot command, and to receive a second signal to accordingly generate a boot command; and a processor, configured to perform a pre-boot process according to the pre-boot signal to generate the image data, to enter a waiting mode when the pre-boot process is complete, and to exit the waiting mode according to the boot command. The image data is not used to display an image by the display module when the processor remains in the waiting mode. | 04-23-2015 |
Li-Ren Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20140126313 | CHIP WITH EMBEDDED NON-VOLATILE MEMORY AND TESTING METHOD THEREFOR - A testing method for a chip with an embedded non-volatile memory and the chip is provided. A remapping circuit and the non-volatile memory are connected to a processor. The non-volatile memory has a test area and an area under test. The test area stores a test program, and the area under test stores data under test. When the processor tests the chip, the processor outputs an original instruction address, and the remapping circuit remaps the original instruction address to generate a remapped instruction address. The processor reads the test program in the test area, and executes the test program to read the data under test in the area under test and to perform a test of toggling the logic circuit. | 05-08-2014 |
20150048853 | Device and Method for Impedance Analysis - An impedance analysis device adapted to an object under test (OUT) includes a signal generator, a signal analysis unit and a processing unit. The signal generator outputs a pulse signal to the OUT. The signal analysis unit acquires a response signal which the OUT responds to the pulse signal, and analyzes the response signal to obtain an analysis parameter. The processing unit coupled to the signal analysis unit receives the analysis parameter, so as to obtain an impedance variation characteristic of the OUT. | 02-19-2015 |
Lung-Yin Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20140119638 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT TO EVALUATE A SEMICONDUCTOR WAFER FABRICATION PROCESS - Systems, methods and computer program products for computerized evaluation of a semiconductor wafer fabrication process are described. An exemplary method comprises receiving an SEM image of a printed semiconductor wafer area and a reference image reflecting a circuit design pattern, enhancing the SEM image to produce a feature image, and comparing the feature image to the reference image to determine whether the positions of the images are the same. Based upon this analysis, evaluation of the fabrication process used to print the circuit on the SEM image can be conducted in an efficient and uniform manner. | 05-01-2014 |
Ming-Chuan Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20110019489 | Apparatus and method for data strobe and timing variation detection of an SDRAM interface - An apparatus for data strobe and timing variation detection of an SDRAM interface includes a differential-signal to single-end signal converter, a first phase delay circuit, a data latch circuit. The differential-signal to single-end signal converter receives a differential data strobe signal from the SDRAM interface and converts the signal into a single-end data strobe signal. The first phase delay circuit is connected to the differential-signal to single-end signal converter to delay the phase of the single-end data strobe signal for producing a delayed data strobe signal. The data latch circuit is connected to the phase delay circuit to latch synchronous data from the SDRAM interface according to the delayed single-end data strobe signal. | 01-27-2011 |
20110302467 | Memory test system with advance features for completed memory system - In a memory test system with advance features for completed memory system, the hardware components are independently configured to generate versatile test patterns for performing a programmable-loading test, a real case test, and a write-feedback test. The write-feedback test is employed to independently test a memory controller which is embedded in an integrated circuit without communicating with the external SDRAM. In the integrated circuit verification stage, the memory test system supports for analyzing and distinguishing the problems inside or outside of the integrated circuit, and testing individual write and read commands. | 12-08-2011 |
20120239873 | Memory access system and method for optimizing SDRAM bandwidth - A memory access system for optimizing SDRAM bandwidth includes a memory command processor, and an SDRAM interface and protocol controller. The memory command processor is connected to a memory bus arbiter and data switch circuit for receiving memory access commands outputted by the memory bus arbiter and data switch circuit and converting the memory access commands into reordered SDRAM commands. The SDRAM interface and protocol controller is connected to the memory command processor for receiving and executing the reordered SDRAM commands based on protocol and timing of SDRAM. The memory command processor decodes the memory access commands into general SDRAM commands or alternative SDRAM commands. The memory access commands decoded into alternative SDRAM commands are generated by a specific bus master. | 09-20-2012 |
Ming-Tsung Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20100278020 | Recording Method and Apparatus for Optical Disk Drive - A recording apparatus for an optical disk drive is provided. The recording apparatus includes a driver, a servo signal generator, a filter, and a counter. The driver controls a recording speed of the optical disk drive. The servo signal generator generates at least a servo signal. The filter with a specific bandwidth filters the servo signal to generate a filtered servo signal. The counter generate a count value according to the filtered servo signal and instructs the driver to decrease the recording speed of the optical disk drive when the count value exceeds a trigger value, so as to record with the decreased recording speed. | 11-04-2010 |
Nan-Shiung Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20160103156 | SYSTEM AND METHOD FOR MEASURING LOAD IMPEDANCE - According to one embodiment of a system for measuring a load impedance, comprising: a switch module, a first reference impedance, a second reference impedance, and a control module, wherein the switch module connects the first reference impedance, the second reference impedance, and the load impedance, respectively; the control module connects the switch module; the control module connects the first reference impedance via controlling the switch module to obtain a first voltage value; the control module connects the second reference impedance via controlling the switch module to obtain a second voltage value; the control module connects the load impedance via controlling the switch module to obtain a load voltage value; and the control module calculates the measured value of the load impedance according to the first voltage value, the second voltage value, and the load voltage value. | 04-14-2016 |
Pei-Cheng Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20100079208 | Minimum pulse generation in a class-D amplifier - For minimum pulse generation in a class-D amplifier, a trapezoid switching waveform shape is used to replace the tradition triangle type to generate PWM pulses. Two voltages are compared with a sawtooth wave signal to generate the trapezoid waveform signal and a constant pulse width signal. An audio input signal is compared with the trapezoid waveform signal to generate a pulse width modulation signal, and either the pulse width modulation signal or the constant pulse width signal is used for driving a load at an output of the class-D amplifier. Flexible minimum pulse width could be obtained by offsetting one of the two voltages in generation of the constant pulse width signal. | 04-01-2010 |
Pei-Chung Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20110043283 | VARIABLE FREQUENCY CLASS-D AMPLIFIER, CONTROL METHOD THEREOF, AND RAMP GENERATOR THEREFOR - A class-D amplifier includes a ramp generator to provide a ramp signal having a frequency varying with an audio input signal, and a modulator to convert the audio input signal to a pulse width modulation signal according to the ramp signal for a driver to drive a load device. The varying frequency of the ramp signal will cause the frequency of the pulse width modulation signal unfixed and consequently improves EMI issue. | 02-24-2011 |
Po-Han Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20120151192 | Very Long Instruction Word (VLIW) Processor with Power Management, and Apparatus and Method of Power Management Therefor - A very long instruction word (VLIW) processor and an apparatus with power management and a method of power management therefor are provided in consistent with the exemplary embodiments of the disclosure. The power management method includes the following steps. Valid instruction(s) and no operation (NOP) instruction(s) of an input instruction package are rearranged to output a transcoded instruction package, wherein the transcoded instruction package by the rearrangement has its NOP instruction(s) corresponding to at least one execution unit, which is to be placed in power reduction state, of a VLIW processor. Power reduction control is selectively performed on at least one execution unit corresponding to at least one NOP instruction of the transcoded instruction package according to the transcoded instruction package. | 06-14-2012 |
20150108963 | VOLTAGE COMPENSATION CIRCUIT AND CONTROL METHOD THEREOF - A voltage compensation circuit and a control method thereof dynamically compensate a voltage drop caused by supplying power from a first power line to a function circuit. The voltage compensation circuit includes an amplifier, a detection module and a boosting module. The amplifier has an inverse input end coupled to the first power line and the function circuit to be supplied with a load voltage supplying to the function circuit, a non-inverse input end for being supplied with a reference voltage, and an output end coupled to the detection module to output a comparison signal. The boosting module is coupled between the detection module and the inverse input end of the amplifier. The detection module generates compensation voltage information according to the comparison signal. The boosting module outputs the compensation voltage to the inverse input end of the amplifier according to the compensation voltage information. | 04-23-2015 |
Qian-Zhi Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20130286877 | Method and Apparatus Reporting Channel Quality Indicator of Communication System - The present invention provides a method and apparatus reporting a channel quality indicator (CQI) of a communication system, including: detecting a first measurement reflecting a first communication quality of the communication system, providing first reference(s) respectively corresponding to indicator level(s), providing CQI according to the indicator level(s) and a relation between the first measurement and the first reference(s), and updating one (or more) first reference according to a second measurement reflecting a second communication quality of the communication system. For example, the first measurement can represent signal to interference ratio or mutual information, and the second measurement can represent data error rate or throughput. First reference(s) can be further adjusted according to a third measurement, e.g., a power scheduling of base station, such that CQI can be updated if base station schedules additional transmission power. | 10-31-2013 |
Shen-Jui Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20160092399 | FOLDED BUTTERFLY MODULE, PIPELINED FFT PROCESSOR USING THE SAME, AND CONTROL METHOD OF THE SAME - A folded butterfly module performs a radix-2 | 03-31-2016 |
Shih-Hung Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20120299904 | APPARATUS AND METHOD FOR DRIVING DISPLAY - An apparatus for driving a display includes a shift register, a first latch unit, a second latch unit, a data comparison unit and a level select unit. The shift register generates multiple latch signals according to a sync signal. The first latch unit latches a data signal in response to the latch signals to obtain multiple first data corresponding to multiple channels. The second latch unit is coupled to the first latch unit and latches the first data of the channels as multiple second data in response to a latch data signal. The data comparison unit responds to the latch data signal to respectively compare the first data and the second data corresponding to the same channel to output multiple third data corresponding to the channels. The level select unit selects multiple voltage levels corresponding to the channels according to the third data. | 11-29-2012 |
20140002435 | DATA DRIVER FOR ELECTROPHORETIC DISPLAY | 01-02-2014 |
Tai-Hsiang Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20120236274 | LIQUID CRYSTAL PANEL MANUFACTURING APPARATUS AND METHOD FOR MANUFACTURING THE LIQUID CRYSTAL PANEL - According to one embodiment, a liquid crystal panel manufacturing apparatus includes a treatment bath, a light transmissive window, a liquid flowing unit, and a light irradiation unit. The treatment bath is configured to contain a liquid and to treat a panel in the liquid, wherein the panel includes a liquid crystal layer having a photo-polymerizable material and a liquid crystal composition. The light transmissive window is provided in the treatment bath. The liquid flowing unit is configured to cause the liquid to flow along a major surface of the panel. A light irradiation unit is configured to irradiate the panel with a light to polymerize the photo-polymerizable material via the light transmissive window. | 09-20-2012 |
Tsai-Ming Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20150017571 | PHOTOLITHOGRPAHY SCATTERING BAR STRUCTURE AND METHOD - Provided is an integrated circuit (IC) photo mask. The IC photo mask includes a main feature of the IC, the main feature having a plurality of sides, and a plurality of assist features, the assist features being spaced from each other and spaced from the main feature, wherein each one of the assist features is adjacent to one of the sides, each one of the assist features has an elongated shape along a direction, whereby extending the shape in the direction would intersect at least another one of the assist features and the assist features are sub-resolution correction features for correcting for optical proximity effect in a photolithography process. | 01-15-2015 |
20150106771 | METHOD OF LITHOGRAPHIC PROCESS EVALUATION - Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding process model. The method further comprises randomly varying the value of each parameter of the first lithography condition within a range of values defined by the corresponding process model of the parameter, to create a second lithography condition. Formation of a layout pattern is then re-simulated under the second lithography condition. Random variation of the value of each parameter is repeated to create additional lithography conditions. And, each lithography condition is re-simulated until the value of each parameter has been substantially varied across a range of its respective process model. | 04-16-2015 |
Tsai Yu Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20120126394 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR PREPARING THE SAME - An integrated circuit device includes a bottom wafer, at least one stacking wafer positioned on the bottom wafer, and at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein the bottom wafer and the stacking wafer are bonded by an intervening adhesive layer, and no bump pad is positioned between the bottom wafer and the stacking wafer. A method for preparing an integrated circuit device includes the steps of forming a bottom wafer, forming at least one stacking wafer, bonding the at least one stacking wafer to the bottom wafer by an intervening adhesive layer, and forming at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein no bump pad is positioned between the bottom wafer and the stacking wafer. | 05-24-2012 |
20120168935 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR PREPARING THE SAME - An integrated circuit device includes a bottom wafer having a first annular dielectric block, at least one stacking wafer having a second annular dielectric block positioned on the bottom wafer, and a conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner. In one embodiment of the present invention, the bottom wafer and the stacking wafer are bonded by an intervening adhesive layer, no bump pad is positioned between the bottom wafer and the stacking wafer, and the conductive via is positioned within the first annular dielectric block and the second annular dielectric block. | 07-05-2012 |
20140191234 | Three Dimensional Stacked Structure for Chips - A 3-D chip stacked structure is disclosed. Each chip layer is provided with plural single-layered conductive members where among the same chip layer the two adjacent conductive members are structurally formed in minor symmetric way with each other along a chip longitudinal direction and the arrangements of the single-layered conductive members of the two adjacent chip layers are shifted by a test pad distance. The single-layered conductive members of the two adjacent chip layers are communicated through a vertical TSV (through silicon via). Therefore, a selection signal or an enabling signal might be transferred through this specific metal layer and related TSV to reach targeting chip layer and targeting circuit. | 07-10-2014 |
Tseng-Hsuan Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20150224626 | Multiple Nozzle Slurry Dispense Scheme - An apparatus includes a slurry dispensing arm, multiple nozzles formed on the slurry dispensing arm, and a slurry supply module connected to the slurry dispensing arm. The slurry supply module is configured to provide slurry to the multiple nozzles and the multiple nozzles are configured to dispense the slurry. | 08-13-2015 |
Tsung-Yi Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20120181653 | SEMICONDUCTOR PN JUNCTION STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention discloses a semiconductor PN junction structure and a manufacturing method thereof. From top view, the PN junction includes a staggered comb-teeth structure. The PN junction forms a depletion region with enhanced breakdown voltage, hence broadening the applications of a semiconductor device having such PN junction. | 07-19-2012 |
Tzu-Hao Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20130295769 | METHODS OF PATTERNING SMALL VIA PITCH DIMENSIONS - Integrated circuit methods are described. The methods include providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (OPC) feature linking the two main features; forming a hard mask layer on a substrate, the hard mask layer including two trench openings; forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask. | 11-07-2013 |
Tzu-Wei Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20140001590 | IMAGE SENSOR DEVICES AND METHODS FOR MANUFACTURING THE SAME | 01-02-2014 |
20160099280 | IMAGE SENSORS AND METHODS OF FORMING THE SAME - An image sensor is provided. The image sensor includes a red (R) pixel, a green (G) pixel, a blue (B) pixel and an infrared (IR) pixel, and R, G and B filters respectively disposed at the R, G and B pixels. The image sensor also includes an IR pass filter disposed at the IR pixel and an IR filter stacked with the R, G and B filters, wherein the IR filter cuts off at least IR light with a specific wavelength. Furthermore, a method of forming an image sensor is also provided. | 04-07-2016 |
Wen-Yu Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20140075774 | SEMICONDUCTOR APPARATUS WITH INNER WAFER CARRIER BUFFER AND METHOD - The present disclosure provides one embodiment of a semiconductor processing apparatus. The semiconductor processing apparatus includes a load lock designed to receive a wafer carrier; an inner wafer carrier buffer configured to hold the wafer carrier received from the load lock and to perform a nitrogen purge to the wafer carrier; and a processing module designed to perform a semiconductor process to wafers from the wafer. | 03-20-2014 |
Ya-Chuang Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20150185491 | Optical Imaging Apparatus - An optical imaging apparatus is provided. The optical imaging apparatus includes a micro reflective mirror assembly and at least one imaging source. The micro reflective mirror assembly is mainly comprised of multiple micro reflective mirrors, and each micro reflective mirror has a first focus. The first focus of each micro reflective mirror is different from the first focus of other micro reflective mirror, and all the first focuses constitute a first focus group. A plurality of light emitted from the imaging source is reflected by the micro reflective mirror assembly so as to form an image in a first region that the first focus group defines. | 07-02-2015 |
Yen-Chieh Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20120057423 | ELECTRICAL FUSE MEMORY ARRAYS - Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column. | 03-08-2012 |
20150260783 | SPLIT GATE STRUCTURE AND METHOD OF USING SAME - A method comprises providing first and second semiconductor devices. Each device comprises a transistor having a split gate electrode including first and second gate portions. Each device has a respective ratio between an area of its first gate portion and a sum of areas of its first and second gate portions. For each device, a stress voltage is applied to the first gate portion, but not to the second gate portion. For each device, the first and second gate portions are biased with a common voltage, and data are collected indicating a respective degradation for each device due to the stress voltage. The degradation has a component due to time dependent dielectric breakdown (TDDB) and a component due to bias temperature instability. From the collected data extrapolation determines the degradation component due to TDDB. | 09-17-2015 |
Yen Lin Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20160126892 | MODULATION CIRCUIT AND OPERATING METHOD THEREOF - A modulation circuit includes a phase locked loop (PLL) circuit, a scalar circuit and a sigma-delta modulator. The PLL circuit is for generating an output oscillating signal in response to a reference signal, a first control signal and a second control signal. The scalar circuit is for generating the first control signal in response to modulating data to control frequency deviation of the output oscillating signal, wherein the first control signal is in a digital form. The sigma-delta modulator is for generating the second control signal according to the modulating data to modulate a divider value of a frequency divider of the PLL circuit. | 05-05-2016 |
Yi-Chin Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20140181669 | ELECTRONIC DEVICE AND METHOD FOR CONTROLLING THE SAME - A method for controlling an electronic device is provided. The method includes detecting a first tilt angle between the electronic device and a reference plane, and controlling the electronic device to perform an operating according to the first tilt angle. The operation is associated with a user interface operation or an audio/video playback operation. | 06-26-2014 |
Yi-Lii Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20150221737 | SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHOD - Embodiments of the disclosure provide semiconductor device structures and methods of forming the same. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate. | 08-06-2015 |
20160093736 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes an isolation structure positioned in the semiconductor substrate and adjacent to a first active region of the semiconductor substrate. The semiconductor device structure includes a gate stack disposed over the first active region. The semiconductor device structure includes a first contact structure disposed over the first active region and positioned between the isolation structure and the gate stack. The semiconductor device structure includes a dummy gate stack disposed over the isolation structure and adjacent to the gate stack. The dummy gate stack is not positioned over a portion of the isolation structure next to the first contact structure. | 03-31-2016 |
Yin Chin Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20120263002 | TEST METHOD FOR SCREENING LOCAL BIT-LINE DEFECTS IN A MEMORY ARRAY - A method of detecting manufacturing defects at a memory array may include utilizing test circuitry to provide a selected voltage as drain bias on a bit-line of the memory array where the memory array is configured to employ a first voltage as the drain bias for a read operation and the selected voltage is higher than the first voltage, and determining whether a leakage current indicative of a manufacturing defect between the bit-line and another component of the memory array is present responsive to providing the selected voltage as the drain bias. A corresponding test device is also provided. | 10-18-2012 |
Ying-Jui Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20140363966 | Pillar Bumps and Process for Making Same - Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular, or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art. | 12-11-2014 |
20150333033 | Pick-and-Place Tool for Packaging Process - A method includes moving a first bond head along a first guide apparatus for a first loop. The first guide apparatus is configured in a ring shape. The method also includes picking up a first die using the first bond head during the first loop, and aligning the first die with a first package substrate. The aligning the first die with the first package substrate includes moving the first package substrate in a first direction and a second direction. The first direction and the second direction are contained in a first plane parallel to the first loop. The method further includes placing the first die over the first package substrate during the first loop. | 11-19-2015 |
20160064355 | CHIP PACKAGES AND METHODS OF MANUFACTURE THEREOF - A chip package may include: a first die; at least one second die disposed over the first die; and a lid disposed over lateral portions of the first die and at least partially surrounding the at least one second die, the lid having inclined sidewalls spaced apart from and facing the at least one second die. | 03-03-2016 |
Yi-Ti Huang, Zhubei City TW
Patent application number | Description | Published |
---|---|---|
20100022211 | Low noise, highly linear amplifying stage and signal receiver using the same - The invention provides a signal amplifying stage, used in a signal receiver. The signal amplifying stage has: a fixed-gain low noise amplifier (LNA), amplifying an input signal; a variable-gain LNA (VG-LNA) array, amplifying the input signal, including a plurality of parallel VG-LNAs, the VG-LNA array being parallel with the fixed-gain LNA; a variable-gain amplifier (VGA), being in series with the fixed-gain LNA and the VG-LNA array, for amplifying output signals from the fixed-gain LNA and the VG-LNA array to generate an output signal; an attenuator, being in parallel with a combination of the fixed-gain LNA, the VG-LNA array and the VGA, for attenuating the input signal to generate the output signal; and a control loop, coupled to the VGA and the attenuator, for detecting power levels of the output signal to enable and control the fixed-gain LNA, the VG-LNA array, the VGA and the attenuator. | 01-28-2010 |