Patent application number | Description | Published |
20090212410 | STACK DIE PACKAGES - An integrated circuit package includes a substrate comprising a first contact. A first integrated circuit mechanically attached to the substrate. The first integrated circuit comprising a second contact. A first redistribution layer arranged on the first integrated circuit. The first redistribution layer includes a trace coupled to the second contact. A first wire connects the first contact to the second contact. A flip-chip integrated circuit comprises a third contact connected to the trace by a conductive bump. A second integrated circuit mechanically coupled to the flip-chip integrated circuit. The second integrated circuit comprises a fourth contact. A second wire connects the fourth contact to at least the second contact or the first contact. | 08-27-2009 |
20110049710 | INTERCONNECT LAYOUTS FOR ELECTRONIC ASSEMBLIES - Embodiments of the present disclosure provide an apparatus including an electronic device and a substrate to receive the electronic device, the electronic device being electrically coupled to the substrate using a plurality of interconnect structures, the interconnect structures being arranged on the electronic device based at least in part on a layout of the substrate. Other embodiments may be described and/or claimed. | 03-03-2011 |
20110298117 | PAD CONFIGURATIONS FOR AN ELECTRONIC PACKAGE ASSEMBLY - Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die. Other embodiments may be described and/or claimed. | 12-08-2011 |
20120196407 | SINGLE LAYER BGA SUBSTRATE PROCESS - Embodiments of the present disclosure provide semiconductor packaging techniques that form a substrate using metal and insulating materials. The substrate includes a first surface that is bonded to a semiconductor device and a second surface that is bonded to a printed circuit board. The substrate is formed using several techniques that minimize the amount of mask levels used to form the substrate. For example, a metal substrate is patterned to form a three dimensional pattern on the surface. A dielectric material is deposited on the three dimensional pattern. Using several patterning and polishing embodiments described herein, the metal/dielectric substrate is patterned and polished to form a substantially flush surface that is bonded to the semiconductor device. In one embodiment, the top surface of the metal/dielectric substrate is patterned to expose the underlying metal substrate and the bottom surface of the metal substrate is polished to be substantially flush with the dielectric material. | 08-02-2012 |
20130043587 | PACKAGE-ON-PACKAGE STRUCTURES - Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls. | 02-21-2013 |
20140151880 | PACKAGE-ON-PACKAGE STRUCTURES - Embodiments of the present disclosure provide a package on package arrangement comprising a first package including a substrate layer including a top side, and a bottom side that is opposite to the top side, wherein the top side of the substrate layer defines a substantially flat surface, and a first die coupled to the bottom side of the substrate layer. The arrangement also comprises a second package including a plurality of rows of solder balls and at least one of one or both of an active component or a passive component. The second package is attached, via the plurality of rows of solder balls, to the substantially flat surface of the top side of the substrate layer of the first package. The active component and/or a passive component is attached to the substantially flat surface of the top side of the substrate layer of the first package. | 06-05-2014 |
20140206152 | SINGLE LAYER BGA SUBSTRATE PROCESS - The present disclosure provides semiconductor packaging techniques that form a substrate using metal and insulating materials. The substrate includes a first surface that is bonded to a semiconductor device and a second surface that is bonded to a printed circuit board. The substrate is formed using several techniques that minimize the amount of mask levels used to form the substrate. For example, a metal substrate is patterned to form a three dimensional pattern on the surface. A dielectric material is deposited on the three dimensional pattern. Using several patterning and polishing embodiments described herein, the metal/dielectric substrate is patterned and polished to form a substantially flush surface that is bonded to the semiconductor device. In one embodiment, the top surface of the metal/dielectric substrate is patterned to expose the underlying metal substrate and the bottom surface of the metal substrate is polished to be substantially flush with the dielectric material. | 07-24-2014 |
20140231993 | PACKAGE-ON-PACKAGE STRUCTURES - Embodiments of the present disclosure provide a first package configured to be coupled to a second package, wherein the first package comprises: a ball grid array substrate; a die coupled to the ball grid array substrate; two rows of ball pads arranged around a periphery of the ball grid array substrate, wherein the ball pads of the two rows of ball pads are configured to receive solder balls to couple the first package to the second package, wherein an outer row of the two rows of ball pads comprises at least some ball pads configured as a first type of ball pad, wherein an inner row of the two rows of ball pads comprises at least some ball pads configured as a second type of ball pad, wherein the first type of ball pad is different than the second type of ball pad. | 08-21-2014 |
20150035160 | PAD CONFIGURATIONS FOR AN ELECTRONIC PACKAGE ASSEMBLY - Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die. | 02-05-2015 |