| Patent application number | Description | Published |
|---|
| 20080217719 | Method For Reducing Crosstalk In Image Sensors Using Implant Technology - The present disclosure provides an image sensor semiconductor device. A semiconductor substrate having a first-type conductivity is provided. A plurality of sensor elements is formed in the semiconductor substrate. An isolation feature is formed between the plurality of sensor elements. An ion implantation process is performed to form a doped region having the first-type conductivity substantially underlying the isolation feature using at least two different implant energy. | 09-11-2008 |
| 20100207230 | METHOD TO OPTIMIZE SUBSTRATE THICKNESS FOR IMAGE SENSOR DEVICE - Provided is a method for fabricating an image sensor device that includes providing a substrate having a front side and a back side; patterning a photoresist on the front side of the substrate to define an opening having a first width, the photoresist having a first thickness correlated to the first width; performing an implantation process through the opening using an implantation energy correlated to the first thickness thereby forming a first doped isolation feature; forming a light sensing feature adjacent to the first doped isolation feature, the light sensing feature having a second width; and thinning the substrate from the back side so that the substrate has a second thickness that does not exceed twice a depth of the first doped isolation feature. A pixel size is substantially equal to the first and second widths. | 08-19-2010 |
| 20100244287 | METHOD OF MEASUREMENT IN SEMICONDUCTOR FABRICATION - Provided is a method of fabricating a semiconductor device. The method includes providing a device substrate having a front side and a back side, the device substrate having a first refractive index, forming an embedded target over the front side of the device substrate, forming a reflective layer over the embedded target, forming a media layer over the back side of the device substrate, the media layer having a second refractive index less than the first refractive index, and projecting radiation through the media layer and the device substrate from the back side so that the embedded target is detected for a semiconductor process. | 09-30-2010 |
| 20100248414 | METHOD OF WAFER BONDING - Provided is a method of fabricating a semiconductor device. The method includes providing a device substrate having a front side, a back side, and a first edge portion, forming a material layer over a portion of the front side of the device substrate, trimming the first edge portion, removing the material layer, bonding the front side of the device substrate to a carrier substrate, thinning the device substrate from the back side, and trimming a second edge portion of the thinned device substrate. | 09-30-2010 |
| 20110031542 | METHOD TO OPTIMIZE SUBSTRATE THICKNESS FOR IMAGE SENSOR DEVICE - Provided is a method for fabricating an image sensor device that includes providing a substrate having a front side and a back side; patterning a photoresist on the front side of the substrate to define an opening having a first width, the photoresist having a first thickness correlated to the first width; performing an implantation process through the opening using an implantation energy correlated to the first thickness thereby forming a first doped isolation feature; forming a light sensing feature adjacent to the first doped isolation feature, the light sensing feature having a second width; and thinning the substrate from the back side so that the substrate has a second thickness that does not exceed twice a depth of the first doped isolation feature. A pixel size is substantially equal to the first and second widths. | 02-10-2011 |
| 20120007204 | METHOD TO OPTIMIZE SUBSTRATE THICKNESS FOR IMAGE SENSOR DEVICE - Provided is a method for fabricating an image sensor device that includes providing a substrate having a front side and a back side; patterning a photoresist on the front side of the substrate to define an opening having a first width, the photoresist having a first thickness correlated to the first width; performing an implantation process through the opening using an implantation energy correlated to the first thickness thereby forming a first doped isolation feature; forming a light sensing feature adjacent to the first doped isolation feature, the light sensing feature having a second width; and thinning the substrate from the back side so that the substrate has a second thickness that does not exceed twice a depth of the first doped isolation feature. A pixel size is substantially equal to the first and second widths. | 01-12-2012 |
| Patent application number | Description | Published |
|---|
| 20090086540 | METHOD OF OPERATING NON-VOLATILE MEMORY ARRAY - A method of operating a non-volatile memory array is provided. The non-volatile memory array includes a substrate, a number of rows of memory cells, a number of control gate lines, a number of select gate lines, a number of source lines, and a number of drain lines. The operating method includes applying 5V voltage to a selected source line, 1.5V voltage to a selected select gate line, 8V voltage to non-selected select gate lines, 10-12V voltage to a selected control gate line and 0-−2V voltage to non-selected control gate lines and the substrate. The drain lines are grounded so that source-side injection (SSI) is triggered to inject electrons into a floating gate of the selected memory cell in a programming operation. | 04-02-2009 |
| 20120261736 | NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A non-volatile memory device includes a substrate, a gate stack, a selecting gate, an erasing gate, a source region, and a drain region. The gate stack on the substrate includes from bottom to top a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer, a control gate, and a spacer that is located between sidewalls of the control gate and the inter-gate dielectric layer. A side of the floating gate adjacent to the erasing gate has a warp-around profile and a sharp corner protruding from a vertical surface of the spacer. The selecting and erasing gates are respectively located at first and second sides of the substrate of the gate stack. The source region is located in the substrate under the erasing gate. The drain region is located in the substrate at a side of the selecting gate. | 10-18-2012 |
| 20130203228 | METHOD OF FABRICATING NON-VOLATILE MEMORY DEVICE - A method of fabricating a non-volatile memory is provided. A tunneling dielectric layer and a first patterned conductive layer are sequentially formed on a substrate. A patterned inter-gate dielectric layer and a second patterned conductive layer are stacked on a first surface of the first patterned conductive layer, and a second surface of the first patterned conductive layer is exposed. The second surface is adjacent to the first surface. The substrate is covered by a passivation layer, and a first sidewall of the first patterned conductive layer is exposed. A recess is formed on the first sidewall of the first patterned conductive layer, such that the first sidewall has a sharp corner. A portion of the passivation layer on the second surface is removed, such that the sharp corner of the first patterned conductive layer is exposed. | 08-08-2013 |
| 20140015029 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes two floating gates, a control gate and a first dielectric layer. The floating gates are disposed on a semiconductor substrate. The control gate partially overlaps each of the floating gates, and a part of the control gate is disposed between the two floating gates. Furthermore, the first dielectric layer disposed between the two floating gates and the control gate has a fixed thickness. | 01-16-2014 |
| 20140183614 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, at least a first gate, a shallow trench isolation (STI) and a third gate. The first gate is disposed on the semiconductor substrate, and the first gate partially overlaps the third gate and the shallow trench isolation. Furthermore, the third gate is disposed in a shallow trench isolation, and the third gate includes at least a protrusion. | 07-03-2014 |
| 20140377945 | FLOATING GATE FORMING PROCESS - A floating gate forming process includes the following steps. A substrate containing active areas isolated from each other by isolation structures protruding from the substrate is provided. A first conductive material is formed to conformally cover the active areas and the isolation structure. An etch back process is performed on the first conductive material to respectively form floating gates separated from each other in the active areas. | 12-25-2014 |
| 20150014761 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor device includes the following steps. At first, two gate stack layers are formed on a semiconductor substrate, wherein each of the gate stack layers includes a top surface and two side surfaces. A conductive material layer is deposited to conformally cover the top surface and the two side surfaces of each of the gate stack layers. Then, a cap layer is deposited to conformally cover the conductive material layer. Finally, the cap layer and the conductive material layer above the top surface of each of the gate stack layers are removed to leave the cap layer adjacent to the two side surfaces of each of the gate stack layers and covering a portion of the conductive material layer. | 01-15-2015 |
| 20150056768 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is disclosed. The method includes the steps of: sequentially forming agate dielectric layer and a first gate layer on a semiconductor substrate, wherein the gate dielectric layer is between the first gate layer and the semiconductor substrate; forming at least an opening in the first gate layer; forming a first dielectric layer conformally on the semiconductor substrate wherein the first dielectric layer covers the first gate layer; and forming a second gate layer filling the opening and overlapping the first gate layer. | 02-26-2015 |
| Patent application number | Description | Published |
|---|
| 20080222385 | PARAMETER SETTING METHOD AND APPARATUS FOR NETWORK CONTROLLER - A method for setting at least one of parameters of a peripheral device coupled to a host includes: executing a program code stored in a first storage unit of a host to obtain setting data corresponding to the at least one of the parameters; storing the setting data into a second storage unit of the host; generating an indication signal to the peripheral device to indicate that the setting data has been stored in the second storage unit; transferring the setting data from the second storage unit of the host to the peripheral device; and performing a function of the peripheral device according to the setting data. | 09-11-2008 |
| 20090245152 | POWER MANAGING METHOD APPLIED TO A WIRELESS NETWORK APPARATUS AND POWER MANAGEMENT THEREOF - A power managing method applied to a wireless network apparatus includes the steps of periodically detecting whether the wireless network apparatus is operated in a non-link status to determine whether to enter a first power-saving mode when the wireless network apparatus powered on; and determining the wireless network apparatus whether to enter a second power-saving mode according to an information of a beacon received by the wireless network apparatus when the wireless network apparatus is operated in a link status. When the wireless network apparatus is detected to be operated in the non-link status, control the wireless network apparatus to enter the first power-saving mode by a power mode controlling circuit. The first power-saving mode is an inactive power-saving mode, and the second power-saving mode is a linked power-saving mode. | 10-01-2009 |
| 20090292836 | DATA ACCESS DEVICE AND METHOD FOR COMMUNICATION SYSTEM - A data access device for a communication system includes: a write controller controlled by the host and outputting a write pointer; a read controller controlled by the write pointer and outputting a read pointer; a download timing controller comparing the write and read pointers to determine a timing of downloading data from the host, and including a pointer difference calculator and a comparator, the pointer difference calculator calculating a distance between the write and read pointers to obtain a pointer difference, the comparator outputting a download status indication according to the pointer difference and a first predetermined length to provide a basis for changing the write pointer; and a transmit buffer downloading data from the host according to the write pointer and transmitting data to the network interface according to the read pointer. A data access device for a network interface controller and a data access method are also disclosed. | 11-26-2009 |
| 20110302434 | METHOD AND DEVICE OF POWER SAVING FOR TRANSMITTING SIGNALS - A method and device of the power saving for transmitting a signal is provided. The method comprises the steps of: transmitting a test signal with a first test amplitude from a local terminal, wherein the first test amplitude is selected from a plurality of preset amplitudes; acknowledging that the test signal with the first test amplitude has been received by a remote terminal if an acknowledgement signal is transmitted from the remote terminal for a response to the test signal; and transmitting a data signal having a data amplitude based on the first test amplitude. The device can transmit the data signal with a small data signal amplitude by the method to achieve the saving power. | 12-08-2011 |
| Patent application number | Description | Published |
|---|
| 20110108879 | LIGHT-EMITTING DEVICE - A light-emitting device comprising a semiconductor light-emitting stack, comprising a light emitting area; an electrode formed on the semiconductor light-emitting stack, wherein the electrode comprises a current injected portion and an extension portion; a current blocking structure formed between the current injected portion and the semiconductor light-emitting stack, and formed between a first part of the extension portion and the semiconductor light-emitting stack; and an electrical contact structure formed between a second part of the extension portion and the semiconductor light-emitting stack. | 05-12-2011 |
| 20110121291 | LIGHT-EMITTING ELEMENT AND THE MANUFACTURING METHOD THEREOF - A light-emitting element includes a light-emitting stack for emitting light and a substrate structure including: a first substrate disposed under the light-emitting stack and having a first surface facing the light-emitting stack; and a second substrate disposed under the light-emitting stack and having a second surface facing the light-emitting stack; and a reflective layer formed between the first substrate and the second substrate and having an inclined angle not perpendicular to the first surface. | 05-26-2011 |
| 20130001624 | LIGHT-EMITTING DEVICE - A light-emitting device includes a semiconductor light-emitting stack; a current injected portion formed on the semiconductor light-emitting stack; an extension portion having a first branch radiating from the current injected portion and having a first width, and a first length greater than the first width, and a second branch extending from the first branch and having a second width larger than the first width, and a second length greater than the second width; and an electrical contact structure between the second branch and the semiconductor light-emitting stack. | 01-03-2013 |
| 20130270599 | LIGHT-EMITTING DEVICE - The present application is related to a light-emitting device. The present application illustrates a vertical light-emitting device in one embodiment, comprising: a conductive substrate includes a through-hole, a patterned semiconductor structure disposed on a first surface of the substrate, a first bonding pad and a second bonding pad disposed on a second surface of the substrate, a conductive line passing through the through-hole connecting electrically the semiconductor structure layer, and an insulation layer on at least one sidewall of the through-hole insulates the conductive line form the substrate. | 10-17-2013 |
| 20130341667 | LIGHT-EMITTING DEVICE - A light-emitting device includes a semiconductor light-emitting stack; a current injected portion formed on the semiconductor light-emitting stack; an extension portion having a first branch radiating from the current injected portion and a second branch extending from the first branch; an electrical contact structure between the second branch and the semiconductor light-emitting stack and having a first width; and a current blocking structure located right beneath the electrical contact structure and having a second width larger than the first width. | 12-26-2013 |
| 20140346544 | Light-Emitting Element Having a Reflective Structure with High Efficiency - A light-emitting element includes a reflective layer; a first transparent layer on the reflective layer; a light-emitting stack having an active layer on the first transparent layer; and a cavity formed in the first transparent layer. | 11-27-2014 |
| Patent application number | Description | Published |
|---|
| 20110031619 | SYSTEM-IN-PACKAGE WITH FAN-OUT WLCSP - A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier; a second semiconductor die mounted alongside of the first semiconductor die; a rewiring laminate structure comprising a re-routed metal layer between the first semiconductor die and the package carrier. At least a portion of the re-routed metal layer projects beyond the die edge. A plurality of bumps are arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier. | 02-10-2011 |
| 20120032314 | PACKAGE-ON-PACKAGE WITH FAN-OUT WLCSP - A package-on-package includes a package carrier; a semiconductor die assembled face-down to a chip side of the package carrier; a rewiring laminate structure between the semiconductor die and the package carrier; a plurality of bumps arranged on the rewiring laminate structure for electrically connecting the semiconductor die with the package carrier; and an IC package mounted on the package carrier. The IC package and the semiconductor die are at least partially overlapped. | 02-09-2012 |
| 20120140427 | PRINTED CIRCUIT BOARD (PCB) ASSEMBLY WITH ADVANCED QUAD FLAT NO-LEAD (A-QFN) PACKAGE - A printed circuit board assembly (PCB) assembly is provided, including a printed circuit board (PCB) comprising a plurality of conductive pads and an advanced quad pack no-lead chip (a-QFN) package soldered to the printed circuit board. In one embodiment, the conductive pads have a first surface area and the QFN package includes a plurality of leads facing the conductive pads, having a second surface area, wherein a ratio between the second surface area and the first surface area is about 20% to 85% to ensure a physical connection between the PCB and the a-QFN package. | 06-07-2012 |
| 20130133193 | SURFACE MOUNT TECHNOLOGY PROCESS FOR ADVANCED QUAD FLAT NO-LEAD PACKAGE PROCESS AND STENCIL USED THEREWITH - The invention provides a surface mount technology process for an advanced quad flat no-lead package process and a stencil used therewith. The surface mount technology process for an advanced quad flat no-lead package includes providing a printed circuit board. A stencil with first openings is mounted over the printed circuit board. A solder paste is printed passing the first openings to form first solder paste patterns. The stencil is taken off. A component placement process is performed to place the advanced quad flat no-lead package comprising a die pad on the printed circuit board, wherein the first solder paste patterns contact a lower surface of the die pad, and an area ratio of the first openings to the lower surface of the die pad is between 1:2 and 1:10. A reflow process is performed to melt the first solder paste patterns to surround a sidewall of the die pad. | 05-30-2013 |
| Patent application number | Description | Published |
|---|
| 20090189569 | CHARGING SYSTEMS AND RELATED METHODS THEREOF - Disclosed is a method for controlling charging current to a battery of a charging system, performed by a control unit of the charging system. The method includes: (a) detecting that a device is coupled to the charging system; (b) adjusting the charging current to a level. The charging current is generated by the coupled device. | 07-30-2009 |
| 20130038297 | BATTERY CHARGING CONTROL DEVICE AND METHOD OF IMPLEMENTING THE SAME - The invention discloses a charging control method for adjusting a charging current of a charging device, including monitoring a working voltage of the charging device, wherein the working voltage includes a voltage difference between a charging voltage and a battery voltage; adjusting the charging current of the charging device dynamically according to the working voltage of the charging device to maintain a working power of the charging device within a predetermined power range. | 02-14-2013 |
| 20130113415 | METHOD AND APPARATUS FOR PERFORMING SYSTEM POWER MANAGEMENT - A method and an apparatus for performing charging port detection control are provided, where the method is applied to an electronic device, a communication port of the electronic device has a functionality of obtaining power from an external power source for the electronic device, and a power path switching unit of the electronic device is arranged to control electrical connection between a system within the electronic device and a battery of the electronic device. The method may include the steps of: performing charging port detection; and control operation(s) according to the charging port detection. For example, the method may include: controlling the power path switching unit to have different configuration according to the charging port detection in order to charge the battery with different charging profiles; and detecting the system voltage level during charging for switching from the constant current mode to the constant voltage mode. | 05-09-2013 |
| Patent application number | Description | Published |
|---|
| 20110013705 | TRANSMITTING DEVICE - The invention discloses a transmitting apparatus. The transmitting apparatus uses the same transmission medium to transmit two signals that are within different frequency ranges at the same time. The transmitting apparatus increases the transmitting paths of the transmission medium so as to enhance the use of the transmission medium and save the production costs. | 01-20-2011 |
| 20140258699 | BOOT FAULT TOLERANT DEVICE AND METHOD THEREOF - An auto firmware update device and method for fault-tolerance is provided. According to an embodiment of the invention, the auto firmware update device includes a serial port, a processor, a timer, a memory and a control unit. The serial port is used for coupling to an external device and updating firmware. The processor fetches instructions to boot. The timer is configured to start counting when the processor boots or restart each time, wherein the timer generates an alarm signal if the timer expires before the processor successfully boots. The memory stores a copy of firmware for booting. The control unit receives the alarm signal to stop the processor, downloads another copy of firmware for booting through the serial port to write to the memory, and restarts the processor. | 09-11-2014 |
| 20140344431 | BASEBOARD MANAGEMENT SYSTEM ARCHITECTURE - A baseboard management system suitable for use in a high density server system is provided. The baseboard management system comprises: a plurality of baseboard management controller (BMC) node respectively located on the servers; and, a main BMC coupled to a network and to the BMC nodes through a communication link for executing a management software; wherein each BMC node is connected with a corresponding host processor and with server board peripherals individually on a corresponding server; and wherein the main BMC in cooperation with the BMC nodes is used to manage the servers remotely. | 11-20-2014 |
| Patent application number | Description | Published |
|---|
| 20110043090 | LAMP STRUCTURE IMPROVEMENT IN THE TWO-LAMPS TYPED DECORATION LAMP STRING - The present invention is to provide a lamp structure improvement in the two-lamps typed decoration lamp string. Each lamp body of the said lamp string is composed of a single soft head, a single soft core and a LED single body of the ordinary half-shaped type separately package-covered with a single lighting crystalline grain then leaned against each other to form a lamp of ordinary shape-and-sized single-piece LED such that the mutually assembled and formed single-piece-shaped LED can have two lighting crystalline grains and form a two-lamps typed lamp body. It thus can effectively lower the manufacturing cost of lamp body in the two-lamps typed decoration lamp string. | 02-24-2011 |
| 20110074300 | STRUCTURE OF AN LED DECORATION LAMP - A dual colored LED decoration lamp which includes a lamp string combined of multiple dual colored LED lights and a controller connected between the power supply and the lamp string. The lamp string includes lamp groups combined of multiple LED lights with two different colors and with their anodes and cathodes cross-linked. The multiple lamp groups are then connected in series, and each LED light in every lamp group is connected in same direction with the same colored LED light in the next lamp group. The controller controls the variation of the direction of current in aforementioned lamp strings. Thus, the lamp string is able to emit light with different colors by varying the current direction in the same lamp string through the usage of controller, and there is no need to set with multiple lamp strings. | 03-31-2011 |
| 20110122613 | LED DECORATIVE LAMP - The LED decorative lamp contains a three-terminal LED device, a flexible core for the plugging of the three-terminal LED device, and a seat for the configuration of the flexible core. The seat contains three terminal plates for the electrical contact with the three terminals of the LED device. A lamp string formed by connecting multiple such LED decorative lamps enjoys accurate flash timing, thereby achieving appealing lighting effect. | 05-26-2011 |
| 20120119664 | POWER-SAVING LIGHT STRING - A power-saving light string, particularly a battery-powered light string, includes a timing controller mounted to an electrical wire of the light string. The light string is operated to intermittently supply power to bulbs of the light string in an alternate ON/OFF switching fashion that complies with visual persistency of human eyes so as to reduce power consumption. | 05-17-2012 |
| Patent application number | Description | Published |
|---|
| 20100289946 | Adaptive de-flicker device and method for adaptive de-flicker - The present invention discloses an adaptive de-flicker device and a method for adaptive de-flicker. The device comprises: a light sensor for sensing ambient light and generating a corresponding electric signal; and a signal processor coupled to the light sensor, for obtaining a flicker frequency of the ambient light according to the electric signal generated by the light sensor. Preferably, the adaptive de-flicker device further comprises a clock generator coupled to the signal processor, for generating a clock signal relating to the flicker frequency of the ambient light according to an output signal of the signal processor. | 11-18-2010 |
| 20110186714 | Adaptive De-Flicker Device and Method For Adaptive De-Flicker - The present invention discloses an adaptive de-flicker device and a method for adaptive de-flicker. The device includes: a light sensor for sensing ambient light and generating a corresponding sensed signal; a signal processor coupled to the light sensor, for generating a signal related to a frequency of the ambient light and a feedback signal according to the sensed signal generated by the light sensor; and an automatic gain control circuit coupled to the signal processor, for generating a control signal according to the feedback signal, to adjust the sensed signal by feedback controlling the light sensor, or to adjust the signal related to the frequency of the ambient light by feedback controlling the signal processor. | 08-04-2011 |
| 20120293557 | Object tracking apparatus, interactive image display system using object tracking apparatus, and methods thereof - The present invention discloses an object tracking apparatus, an interactive image display system using the object tracking apparatus, and methods thereof. The object tracking apparatus generates a control signal inputted to an image display apparatus to display an image in response to an action of an object. The object tracking apparatus includes: an image sensor device, which detects a predetermined pattern displayed by the image display apparatus to generate a sensed image; a coordinate information generation circuit, which generates coordinate information according to the sensed image; and a processing circuit, which generates a predetermined image data based on which the predetermined pattern is generated, wherein the processing circuit compares the coordinate information with the predetermined image data to generate a correction value. | 11-22-2012 |
| 20130093675 | Remote controllable image display system, controller, and processing method therefor - The present invention discloses a remote controllable image display system, and a controller and a motion detection method for use in the system. The system includes: an image display showing images generated by a program; a light source generating at least a light beam; a controller controlling a current image according to its displacement or rotation and including at least one image sensor sensing the light beam to obtain a first frame having at least two light spots; a processor obtaining a first angle between a main operation surface of the controller and a basis plane according to the differences between the coordinates of the two light spots in the first frame. | 04-18-2013 |
| Patent application number | Description | Published |
|---|
| 20090088094 | TRANSMITTER CAPABLE OF REDUCING LOCAL OSCILLATION LEAKAGE AND IN-PHASE/QUADRATURE-PHASE (I/Q) MISMATCH AND ADJUSTING METHODS THEREOF - An adjusting method for reducing local oscillation leakage or I/Q mismatch in a transmitter includes the steps of: (a) detecting a current extent of local oscillation leakage or I/Q mismatch; (b) determining if an adjusting direction is correct with reference to the current extent of local oscillation leakage or I/Q mismatch thus detected, maintaining the adjusting direction if correct, and reversing the adjusting direction upon determining that the adjusting direction is incorrect; and (c) adjusting a control signal according to the adjusting direction. | 04-02-2009 |
| 20090088117 | Receiver capable of reducing local oscillation leakage and in-phase/quadrature-phase (I/Q) mismatch and an adjusting method thereof - An adjusting method for reducing local oscillation leakage or I/Q mismatch in a receiver includes the steps of: (a) detecting a current extent of local oscillation leakage or I/Q mismatch; (b) determining if an adjusting direction is correct with reference to the current extent of local oscillation leakage or I/Q mismatch thus detected, maintaining the adjusting direction if correct, and reversing the adjusting direction upon determining that the adjusting direction is incorrect; and (c) adjusting a control signal according to the adjusting direction. | 04-02-2009 |
| 20090310711 | Transmitter and receiver capable of reducing in-phase/quadrature-phase (I/Q) mismatch and an adjusting method thereof - An adjusting method for reducing in-phase/quadrature-phase (I/Q) mismatch in a transmitter includes the steps of: a) receiving a first in-phase signal and a first quadrature-phase signal; b) adjusting a set of parameters such that an extent of I/Q mismatch related to the first in-phase signal and the first quadrature-phase signal is reduced; c) receiving a second in-phase signal and a second quadrature-phase signal, the second in-phase signal differing from the first in-phase signal in one of frequency and phase; d) adjusting the set of parameters such that an extent of I/Q mismatch related to the second in-phase signal and the second quadrature-phase signal is reduced; and e) determining final values for the set of parameters based on adjustment results of steps b) and d) such that extents of I/Q mismatch related to different frequencies are reduced. | 12-17-2009 |
| 20110261911 | RECEIVER CAPABLE OF REDUCING LOCAL OSCILLATION LEAKAGE AND IN-PHASE/QUADRATURE-PHASE (I/Q) MISMATCH AND AN ADJUSTING METHOD THEREOF - An adjusting method for reducing local oscillation leakage or I/Q mismatch in a receiver includes the steps of: (a) detecting a current extent of local oscillation leakage or I/Q mismatch; (b) determining if an adjusting direction is correct with reference to the current extent of local oscillation leakage or I/Q mismatch thus detected, maintaining the adjusting direction if correct, and reversing the adjusting direction upon determining that the adjusting direction is incorrect; and (c) adjusting a control signal according to the adjusting direction. | 10-27-2011 |
| 20120213266 | METHODS AND APPARATUSES OF CALIBRATING I/Q MISMATCH IN COMMUNICATION CIRCUIT - A method and apparatus of calibrating I/Q mismatch of a communication circuit is disclosed. The disclosure employs I/Q test signals respectively including different frequency components to calibrate the frequency-dependent I/Q mismatch existing in the communication system. | 08-23-2012 |
| 20120213317 | Receiver for Compensating I/Q Mismatch, Compensation Device, Compensation Module and Compensation Parameter Calculating Module - A receiver for compensating I/Q mismatch includes an analog down-conversion unit for receiving a radio frequency signal and down-converting the RF signal into a set of digital low intermediate frequency (IF) signals, a digital down-conversion unit receiving the set of digital low IF signals and down-converting the set of digital low IF signals into first and second baseband signals, and a compensation unit. The compensation unit receives the first and second baseband signals, calculates a compensation parameter based thereon, and compensates I/Q mismatch effect according to the first and second baseband signals and the compensation parameter so as to output a target signal. | 08-23-2012 |
| 20130215999 | METHOD FOR COMPENSATING MISMATCH OF IN-PHASE SIGNAL AND QUADRATURE SIGNAL OF TRANSMITTER/RECEIVER - A method for compensating mismatches of an in-phase signal and a quadrature signal of a transmitter/receiver is provided. The method includes: receiving a plurality of test signals to generate two groups of factors, respectively, where each group of factors is applied to two multipliers utilized for compensating a gain mismatch and a phase mismatch of the in-phase signal and the quadrature signal of the transmitter/receiver; then calculating a delay mismatch of the in-phase signal and the quadrature signal according to the two groups of factors. | 08-22-2013 |
| 20130303100 | RECEIVER CAPABLE OF REDUCING LOCAL OSCILLATION LEAKAGE AND IN-PHASE/QUADRATURE-PHASE (I/Q) MISMATCH AND AN ADJUSTING METHOD THEREOF - A receiver having a mixer for mixing a radio frequency signal and a local oscillator signal so as to generate a base band signal, a detecting unit for generating from the base band signal a detection signal that represents an extent of local oscillation leakage, and an adjusting unit coupled electrically to said mixer for outputting a control signal thereto to control a current operating state of said mixer, said adjusting unit being further coupled electrically to said detecting unit, and determining whether there is a reduction in the extent of local oscillation leakage based on the detection signal from said detecting unit. In operation, the adjusting unit maintains an adjusting direction for the control signal upon determining that the extent of local oscillation leakage is reduced, reverses the adjusting direction upon determining that the extent of local oscillation leakage is not reduced, and adjusts the control signal according to the adjusting direction. | 11-14-2013 |
| 20140368364 | METHOD AND APPARATUS FOR ESTIMATING SAMPLING DELAY ERROR BETWEEN FIRST AND SECOND ANALOG-TO-DIGITAL CONVERTERS OF TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER - A method for estimating a sampling delay error between a first analog-to-digital converter (ADC) and a second ADC in a time-interleaved ADC includes: receiving a first digital output signal and a second digital output signal generated from the first ADC and the second ADC based on a same analog input signal, respectively; determining a delay amount according to a predetermined sampling delay between the first ADC and the second ADC and a delay adjusting value, and applying the delay amount delay to the second digital output signal to generate a delayed digital output signal, wherein the delay adjusting value Td is used to estimate the sampling delay error Te; calculating a difference between the first digital output signal and the delayed digital output signal; and feeding back the difference for adjusting the delay adjusting value Td according to the difference. | 12-18-2014 |
| Patent application number | Description | Published |
|---|
| 20090175097 | Method for detecting erroneous word lines of a memory array and device thereof - A method detects if a word line of a memory array is broken. The method includes writing a first datum to a memory cell when coupling a corresponding word line to a voltage source, writing a second datum different from the first datum to the memory cell when the coupling between the corresponding word line and the voltage source is decoupled, reading the stored data of the memory cell, and determining if the word line is broken according to the read data, the first datum, and the second datum. | 07-09-2009 |
| 20090268530 | Trigger Circuit of a Column Redundant Circuit and Related Column Redundant Device - A trigger circuit for triggering corresponding memory cells of a column redundant circuit includes a determining circuit for generating a determining signal according to an accessed row address, and a plurality of comparing circuits jointly electrically connected to the column redundant circuit for receiving the determining signal, each of the comparing circuits selectively generating a trigger signal to the column redundant circuit according to the determining signal and an accessed column address. | 10-29-2009 |
| 20090273996 | Memory testing system and memory module thereof - A testing system with data compressing function includes a third data end, a first encoder, and a second encoder. The testing system receives testing data and testing address for testing if any memory cell fails in a memory. The memory includes a first data end, a second end, and an address end. The first encoder encodes the testing data to the data type of the first data end according to the testing address. The second encoder encodes the testing data to the data type of the second data end according to the testing address. In this way, the corresponding memory cells of the first data and second ends store same testing data. | 11-05-2009 |
| 20120286838 | DELAY LINE CIRCUIT AND PHASE INTERPOLATION MODULE THEREOF - A phase interpolation module comprising a first, second, and third phase interpolation units is proposed. Each of the first, second, and third phase interpolation units comprises a first through third inverters, a first and second resistors, wherein the first resistor is coupled between an output end of the first inverter and an input end of the third inverter, and the second resistor is coupled between an output end of the second inverter and the input end of the third inverter. The first and second inverters of the first phase interpolation unit receive a first signal, the first and second inverters of the third phase interpolation unit receive a second signal, and the first and second inverters of the second phase interpolation unit respectively receive the first and second signals. | 11-15-2012 |
| 20120287737 | REPAIRING CIRCUIT FOR MEMORY CIRCUIT AND METHOD THEREOF AND MEMORY CIRCUIT USING THE SAME - A novelty repairing method and circuit are provided by the embodiments of the present invention, wherein the input/output (IO) compression manner can be used therein to reduce the access time during the chip probing 1 (CP1) test, and each redundant column selected line (RCSL) can be divided into several partial redundant column selected lines (P-RCSLs) which are respectively responsible for repairing the defects of the corresponding regions. Based upon the repairing method, the memory circuit can reduce the number of the RCSLs. Furthermore, a variable region dividing manner is applied therein, so as to increase the probability for repairing the defect of the memory circuit. | 11-15-2012 |
| Patent application number | Description | Published |
|---|
| 20090145754 | BIOCHEMICAL TEST SYSTEM, MEASUREMENT DEVICE, BIOCHEMICAL TEST STRIP AND METHOD OF MAKING THE SAME - A biochemical test system, a measurement device, a biochemical test strip and a method of making the same are provided. The biochemical test system includes a biochemical test strip and a measurement device. The biochemical test strip includes an insulating substrate, an electrode system disposed on the insulating substrate, and a pattern code disposed on one side of the insulating substrate. The pattern code includes N components and at least one of the N components penetrates the insulating substrate. The measurement device includes a microprocessor and a connector. The connector is coupled to the pattern code and the electrode system for receiving signals corresponding to the pattern code. The microprocessor is coupled to the connector for receiving signals from the connector. | 06-11-2009 |
| 20100206728 | BIOCHEMICAL TEST SYSTEM, MEASUREMENT DEVICE, AND BIOCHEMICAL TEST STRIP - A biochemical test system, a measurement device, and a biochemical test strip are provided. The biochemical test strip includes an insulating substrate, a conductive layer, and at least one open-circuit part. The conductive layer is disposed on the insulating substrate and includes a plurality of electronic elements, wherein one end of the conductive layer is formed as a connection region. The at least one open-circuit part is disposed on at least one of the plurality of the electronic elements within the connection region. The type of the biochemical test strip is determined by the number and location of the at least one open-circuit part(s). | 08-19-2010 |
| 20100319170 | HOLDING DEVICE FOR MEDICAL TEST STRIP - A device for holding a medical test strip is provided. The device comprises a receiving casing having an opening for receiving the medical test strip and a first stopping portion protruding from an upper surface of the receiving casing; an ejection base having a cover and a pusher beneath the cover, the cover downwardly extending a second stopping portion for sliding against the upper surface of the receiving casing; and an elastic member located between the receiving casing and the ejection base. When the pusher moves toward the opening by an external force to eject the test strip from the opening, the elastic member is compressed and the second stopping portion slides away from the first stopping portion. When the external force disappears, the second stopping portion slides toward the first stopping portion by a resilient force of the elastic member until the first stopping portion and the second stopping portion are engaged. | 12-23-2010 |
| 20130121875 | HOLDING DEVICE - A holding device disposed in a bio-detecting instrument for holding a test strip is provided, wherein the holding device comprises a first casing, a second casing, an ejecting member, and an elastic member. The second casing is assembled with the first casing to form an accommodating space, wherein the sensing terminals are extended into the accommodating space. The ejecting member comprises a push rod configured to be reciprocated in the accommodating space. The elastic member is configured to be compressed by driving the ejecting member to an ejecting position, where the push rod enters the accommodating space and is adapted to push the test strip outward without being contact with the sensing terminals, and the elastic member is configured to be released by drawing the push rod back from the accommodating space to an initial position. | 05-16-2013 |
| Patent application number | Description | Published |
|---|
| 20090243752 | Compact Diplexer - A diplexer for receiving and transmitting a first bandwidth signal corresponding to a first central frequency and a second bandwidth signal corresponding to a second central frequency includes a first signal end, a second signal end, a third signal end, a first impedance unit, a second impedance unit and a third impedance unit. The first impedance unit forms an impedance match with the third impedance unit when the third signal end receives or transmits the first bandwidth signal, and forms a high impedance unit when the third signal end receives or transmits the second bandwidth signal. The second impedance unit forms an impedance match with the third impedance unit when the third signal end receives or transmits the second bandwidth signal, and forms a high impedance unit when the third signal end receives or transmits the first bandwidth signal. | 10-01-2009 |
| 20090243760 | Second-Order Band-Pass Filter and Wireless Apparatus Using the Same - A second-order band-pass filter for generating at least two transmission zeros includes a first signal terminal, a second signal terminal, a first transmission line resonator, a second transmission line resonator and an impedance inverter. The first transmission line resonator and the second transmission line resonator are symmetric to each other and coupled to the first signal terminal and the second signal terminal, which are formed by bending two quarter-wavelength open stubs and have an open circuit gap between the two terminals. The impedance inverter includes an inductor, a first micro strip line and a second micro strip line. The first micro strip line and the second micro strip line are symmetric to each other, and are coupled to the first signal terminal and the second signal terminal and coupled to a ground through the inductor, respectively. | 10-01-2009 |
| 20090262027 | Dual-Band Antenna - A dual-band antenna is disclosed and used for receiving or transmitting a first frequency band signal corresponding to a first central frequency and a second frequency band signal corresponding to a second central frequency. The dual-band antenna includes a first radiator, a feed line, a second radiator, and two parallel substrates each of which a grounding plane is installed on. The first and second radiators are respectively installed on the substrates and spatially overlap to each other in part. The first radiator receives and transmits the first and second frequency band signals and includes a first metal strip, having a plurality of bends, and a second metal strip. The second metal strip and the feed line are coupled to the first metal strip. The second radiator is used for enhancing the efficiency of receiving the second frequency band signal for the first radiator. | 10-22-2009 |
| 20110159823 | RF Front-end Circuit and Wireless Communication Device Using the Same - The present invention discloses an RF front-end circuit for a wireless communication device, which includes an RF terminal coupled to an antenna of the wireless communication device, for receiving or transmitting wireless signals; and a switch for connecting a plurality of processing modules to the RF terminal according to operations of the wireless communication device. | 06-30-2011 |
| Patent application number | Description | Published |
|---|
| 20100153344 | INFORMATION EXTRACTION METHOD, EXTRACTOR REBUILDING METHOD, AND SYSTEM AND COMPUTER PROGRAM PRODUCT THEREOF - An information extraction method for extracting dynamic information is provided. The method includes using a plurality of information extractors extracting reference values corresponding to the dynamic information from a plurality of information sources, and determining a most reliable value corresponding to the dynamic information based on the reference values. The method further includes determining whether each of the information extractors is abnormal according to the most reliable value and removing the information extractors determined as abnormal. The method further includes rebuilding new information extractors for replacing the removed information extractors. In such a way, reliable dynamic information can be extracted and the information extractors can be maintained for normal operation. | 06-17-2010 |
| 20100153355 | INFORMATION EXTRACTION METHOD, EXTRACTOR REBUILDING METHOD, AND SYSTEM AND COMPUTER PROGRAM PRODUCT THEREOF - An information extraction method for extracting dynamic information is provided. The method includes using a plurality of information extractors extracting reference values corresponding to the dynamic information from a plurality of information sources, and determining a most reliable value corresponding to the dynamic information based on the reference values. The method further includes determining whether each of the information extractors is abnormal according to the most reliable value and removing the information extractors determined as abnormal. The method further includes rebuilding new information extractors for replacing the removed information extractors. In such a way, reliable dynamic information can be extracted and the information extractors can be maintained for normal operation. | 06-17-2010 |
| 20130162041 | LOAD CONTROL SYSTEM AND LOAD CONTROL METHOD - An exemplary embodiment provides a load management system, including a detecting module and a determining module. The detecting module creates at least one activated one of a plurality of loads located in a predetermined space as an activation set, and creates a group set including a plurality of sub-groups according to locations and activation times of the activated ones of the plurality of loads. The detecting module creates the activated ones of the plurality of loads which have been activated within a predetermined time period as one of the sub-groups. The determining module determines whether each of the activated ones of the plurality of loads is an essential load or a non-essential load according to the group set and the activation set to produce a determining result. | 06-27-2013 |
| Patent application number | Description | Published |
|---|
| 20110030811 | PREHEATING BACKWATER DEVICE - The utility model provides a preheating backwater device, comprising: a tank body, a pump, a control module, a Y-pipe, a first joint pipe, a second joint pipe, a third joint pipe and fourth joint pipe. The device is installed with a hot-water heater and existing hot water tubes and water supply tubes in a building. Users can press wire linked buttons or use wireless remote control first before the hot water is used to turn on the preheating backwater device and pump out the possibly cooled or low temperature water in the hot water tubes by the device so that the water re-circulates to the hot-water heater for heating. It lasts for a recirculation of about several tens of seconds to several minutes and till the time set-up in advance. Users only need to turn the faucet to the hot water mark and hot water will be available. At this moment, preheating of the water stops. | 02-10-2011 |
| 20110073195 | PREHEATING BACKWATER DEVICE - A preheating backwater device comprises a tank body fabricated with a pump, a control module, a Y-pipe and a plurality of pipes inside. The device is assembled with a general hot-water heater and existing hot water and water supply pipes in a building. Users can activate the device either by pressing wire-linked buttons or using a wireless remote control. Lower temperature water in the hot water pipes can be pumped out and recirculated to the hot-water heater of the backwater device for a preset amount of time. If the automatic control module fails and preheating is not stopped automatically, an overheat protection device activates to guide the hot water to a cold water pipe via a backwater gate. A pressure control device installed in one end of a three-port connector of the overheat protection device stabilizes the pressure in the pipes. The design can prevent dangerous overheating situations. | 03-31-2011 |
| Patent application number | Description | Published |
|---|
| 20080297710 | SYSTEM FOR DISPLAYING IMAGES INCLUDING A LIQUID CRYSTAL DISPLAY PANEL - A system for displaying images is provided including a liquid crystal display panel. The liquid crystal display panel has a plurality of sub-pixels, each defined between two adjacent data lines extending along a vertical direction and two adjacent scan lines extending along a horizontal direction. The liquid crystal display panel comprises a transparent bottom electrode on the data lines, and a transparent top electrode on the transparent bottom electrode, wherein the transparent top electrode has an extended portion at a corner of the sub-pixel, extending along the horizontal direction to overlap at least a portion of the data line. | 12-04-2008 |
| 20100165268 | SYSTEM FOR DISPLAYING IMAGES - A system for displaying images is provided and includes a liquid crystal display pane. The liquid crystal display panel includes a first substrate having a plurality of orthogonal data lines and scan lines thereon. A first transparent electrode layer is disposed over the data lines and a second transparent electrode layer is disposed over the first transparent electrode layer. A second substrate is disposed opposite to the first substrate and has an inner surface. A conductive layer is disposed over the inner surface of the second substrate. A liquid crystal layer is disposed between the first substrate and the second substrate. | 07-01-2010 |
| 20100245220 | SYSTEM FOR DISPLAYING IMAGES - Systems for displaying images are provided. The system includes a display device. The display device includes an array substrate, and a transparent electrode stack overlaying the array substrate. The transparent electrode stack includes a first electrode having a first slit, a second electrode having an outer edge disposed corresponding to the interior of the first slit, and a dielectric layer disposed between the first and second electrodes. The dielectric layer electrically isolates the first and second electrodes. | 09-30-2010 |
| Patent application number | Description | Published |
|---|
| 20100213474 | ARRAY-TYPE LIGHT-EMITTING DEVICE AND APPARATUS THEREOF - The application discloses an array-type light-emitting device comprising a substrate, a semiconductor light-emitting array formed on the substrate and emitting a first light with a first spectrum, wherein the semiconductor light-emitting array comprises a first light-emitting unit and a second light-emitting units, a first wavelength conversion layer formed on the first light-emitting unit for converting the first light into a third light with a third spectrum, and a circuit layer connecting the first light-emitting unit and the second light-emitting unit in a connection form to make the first light-emitting and the second light-emitting unit light alternately in accordance with a predetermined clock when driving by a power supply. | 08-26-2010 |
| 20100214511 | DISPLAY APPARATUS HAVING AN ARRAY-TYPE LIGHT-EMITTING DEVICE - The application discloses an array-type light-emitting device comprising a substrate, a semiconductor light-emitting array formed on the substrate and emitting a first light with a first spectrum, wherein the semiconductor light-emitting array comprises a first light-emitting unit and a second light-emitting units, a first wavelength conversion layer formed on the first light-emitting unit for converting the first light into a third light with a third spectrum, and a circuit layer connecting the first light-emitting unit and the second light-emitting unit in a connection form to make the first light-emitting and the second light-emitting unit light alternately in accordance with a predetermined clock when driving by a power supply. | 08-26-2010 |
| 20130222731 | ARRAY-TYPE LIGHT-EMITTING DEVICE AND APPARATUS THEREOF - The application discloses an array-type light-emitting device comprising a substrate, a semiconductor light-emitting array formed on the substrate and emitting a first light with a first spectrum, wherein the semiconductor light-emitting array comprises a first light-emitting unit and a second light-emitting units, a first wavelength conversion layer formed on the first light-emitting unit for converting the first light into a third light with a third spectrum, and a circuit layer connecting the first light-emitting unit and the second light-emitting unit in a connection form to make the first light-emitting and the second light-emitting unit light alternately in accordance with a predetermined clock when driving by a power supply. | 08-29-2013 |
| Patent application number | Description | Published |
|---|
| 20090087236 | PAPER ROUTE SWITCHING APPARATUS - A disk having one or more indentations is configured at one end of a driving shaft and has interaction with an extension arm configured at a corresponding end of a switch shaft for switching the medium conveying route in an image system. When the driving shaft drives the disk to rotate along different directions, the indentation on the disk provides the extension arm room for the disk to guide the extension arm to switch its position between a first position and a second position. A plurality of switch gates on the switch shaft also switch to different positions corresponding to the extension arm such that the conveying route of a medium can be switched between a first route and a second route. | 04-02-2009 |
| 20090102117 | DE-SKEW MECHANISM - A de-skew mechanism, in an image forming device, with a correcting member disposed in a rotatable manner to the rotary shaft and turning with driving roller by a spring between them. A torque spring suppresses the turning of the correcting member to correct the skew of the medium. When conveyed, the medium will butt against the correcting member to be stopped and corrected. The medium conveying force and the force that the spring brings to the driving roller are sufficient for turning the correcting member and passing therethrough. At one time, the force that the correcting member brings to the medium will reduce to zero. As such, the medium will not be damaged by the correcting member while being conveyed. | 04-23-2009 |
| 20090189338 | DE-SKEW MECHANISM - A de-skew mechanism includes a driving shaft installed on a frame of an image forming device and driven by a motor, an active roller installed on the driving shaft and driven by the driving shaft, and an idle roller driven by the active roller for driving a medium with the active roller. A nip is formed between the active roller and the idle roller. The de-skew mechanism further includes a correcting member installed on the driving shaft in a rotatable manner and located upstream of the nip for correcting skew of the medium in a correcting position, and a restoring member connected to the correcting member for loading torque to the correcting member so as to drive the connecting member from the correcting position to a releasing position where the medium pass therethrough. | 07-30-2009 |
| 20090189343 | PAPER-FEEDING MECHANISM - The paper-feeding mechanism includes a duplex drive roller disposed on a terminal end of a feeding path of an image-forming device for feeding paper and on a side of an output tray, a first idle roller for conveying the paper back to the output tray with the duplex drive roller after a single side of the paper is printed, a second idle roller for conveying the paper back to the output tray with the duplex drive roller after double sides of the paper are printed, and a stop means installed between the terminal end of the feeding path and the output tray for switching to a shut position to stop the paper when the paper is driven back to the feeding path and for switching to an open position when the paper is driven to the output tray after the double sides of the paper are printed. | 07-30-2009 |
| Patent application number | Description | Published |
|---|
| 20080201528 | MEMORY ACCESS SYSTEMS FOR CONFIGURING WAYS AS CACHE OR DIRECTLY ADDRESSABLE MEMORY - A memory system is provided. A processor provides a data access address. A memory device includes a predetermined number of ways. The processor selectively configures a selected number less than or equal to the predetermined number of the ways as cache memory belonging to a cacheable region, and configures remaining ways as directly addressable memory belonging to a directly addressable region by memory configuration information. A memory controller determines the data access address corresponding to the cacheable region or the directly addressable region, selects only the way in the directly addressable region corresponding to the data access address when the data access address corresponds to the directly addressable region, and selects only the way(s) belonging to the cacheable region when the data access address corresponds to the cacheable region. A configuration controller monitors the status of the ways and adjusting the memory configuration information according to the status of the ways. | 08-21-2008 |
| 20090271593 | PATCHING DEVICE FOR PATCHING ROM CODE, METHOD FOR PATCHING ROM CODE, AND ELECTRONIC DEVICE UTILIZING THE SAME - An electronic device comprising a ROM, a reprogrammable memory, a processor, and a patching device. The ROM stores a first function starting from a first address, the reprogrammable memory stores a second function starting from a second address, the patching device couples to the ROM and the reprogrammable memory, and the processor couples to the patching device. The patching device receives directive information from the processor and determines whether the processor is going to fetch the first function, and generates and returns a branch instruction to the processor when the processor is going to fetch the first function. After receiving the branch instruction, the processor executes the branch instruction to cause an unconditional jump to the second address and subsequently fetches the second function. | 10-29-2009 |
| 20100107149 | PATCHING DEVICES AND METHODS THEREOF FOR PATCHING FIRMWARE FUNCTIONS - A patching device and method thereof for patching a firmware function by a patch function. When a fetch address from a processor does not correspond to the firmware function, the patching device outputs an instruction of the fetch address to respond to the processor. When the fetch address corresponds to the replaced firmware function, the patching device outputs an artificial instruction to respond to the processor. The artificial instruction is one of series of machine codes corresponding to a plurality of patch intermediary instructions utilized to direct the processor to jump to the beginning address of the patch function. | 04-29-2010 |
| Patent application number | Description | Published |
|---|
| 20090258159 | NOVEL TREATMENT FOR MASK SURFACE CHEMICAL REDUCTION - A method includes forming an absorption material layer on a mask; applying a plasma treatment to the mask to reduce chemical contaminants after the forming of the absorption material layer; performing a chemical cleaning process of the mask; and performing a gas injection to the mask. | 10-15-2009 |
| 20130157177 | EUV MASK AND METHOD FOR FORMING THE SAME - An extreme ultraviolet (EUV) mask can be used in lithography, such as is used in the fabrication of a semiconductor wafer. The EUV mask includes a low thermal expansion material (LTEM) substrate and a reflective multilayer (ML) disposed thereon. A capping layer is disposed on the reflective ML and a patterned absorption layer disposed on the capping layer. The pattern includes an antireflection (ARC) type pattern. | 06-20-2013 |
| 20130287287 | METHOD AND APPARATUS FOR DEFECT IDENTIFICATION - A method of identifying defects including producing, with an imaging system, an original image of a fabricated article having a feature thereon, the feature having an intended height and extracting a contour image from the original image, the contour image having an outline of those portions of the feature having a height approximate to the intended height. The method also includes producing a simulated image of the article based upon the contour and creating a defect image based on the differences between the simulated image and the original image, the defect image including any portions of the feature having a height less than the intended height. | 10-31-2013 |
| 20130298088 | System and Method for Combined Intraoverlay and Defect Inspection - A method and system for measuring layer overlay and for inspecting a mask for defects unrelated to overlay utilizing a singe comprehensive tool is disclosed. An exemplary method includes receiving a mask design database that corresponds to a mask and has a die area with a mask database feature. A mask image of the mask is received, and a comprehensive inspection system compares the mask image to the mask design database in order to detect mask defects that are not related to layer alignment. The system produces mask defect information corresponding to the mask defects. The comprehensive inspection system also compares the mask image to the mask design database to determine a database-to-mask offset. From the database-to-mask offset, a mask overlay characteristic is determined. | 11-07-2013 |
| 20130322736 | METHOD AND APPARATUS FOR EFFICIENT DEFECT INSPECTION - A method of inspecting fabricated articles includes receiving a fabricated article to be inspected for defects, the fabricated article having a pattern thereon, and the pattern being based on a pattern design and creating a rule set for defining critical regions of the pattern as represented in the pattern design, the critical regions being regions in which defects are more likely to be found during inspection. The method also includes applying the rule set to the pattern design to identify a critical region of the pattern on the fabricated article and a non-critical region of the pattern on the fabricated article. Further, the method includes inspecting the non-critical region of the pattern on the fabricated article for defects at first resolution and inspecting the critical region of the pattern on the fabricated article for defects at a second resolution higher than the first resolution. | 12-05-2013 |
| 20130323931 | DEVICE MANUFACTURING AND CLEANING METHOD - A method of manufacturing is disclosed. An exemplary method includes providing a substrate and forming one or more layers over the substrate. The method further includes forming a surface layer over the one or more layers. The method further includes performing a patterning process on the surface layer thereby forming a pattern on the surface layer. The method further includes performing a cleaning process using a cleaning solution to clean a top surface of the substrate. The cleaning solution includes tetra methyl ammonium hydroxide (TMAH), hydrogen peroxide (H | 12-05-2013 |
| 20140051252 | DEVICE MANUFACTURING AND CLEANING METHOD - A method of manufacturing is disclosed. An exemplary method includes providing a substrate and forming one or more layers over the substrate. The method further includes forming a surface layer over the one or more layers. The method further includes performing a patterning process on the surface layer thereby forming a pattern on the surface layer. The method further includes performing a cleaning process using a cleaning solution to clean a top surface of the substrate. The cleaning solution includes tetra methyl ammonium hydroxide (TMAH), hydrogen peroxide (H | 02-20-2014 |
| 20140205938 | EUV Mask and Method for Forming the Same - An extreme ultraviolet (EUV) mask can be used in lithography, such as is used in the fabrication of a semiconductor wafer. The EUV mask includes a low thermal expansion material (LTEM) substrate and a reflective multilayer (ML) disposed thereon. A capping layer is disposed on the reflective ML and a patterned absorption layer disposed on the capping layer. The pattern includes an antireflection (ARC) type pattern. | 07-24-2014 |
| Patent application number | Description | Published |
|---|
| 20100213493 | LIGHT-EMITTING DEVICE - A light-emitting device including: a light-emitting stacked layer having first conductivity type semiconductor layer, a light-emitting layer formed on the first conductivity type semiconductor layer, and a second conductivity type semiconductor layer formed on the light-emitting layer, wherein the upper surface of the second conductivity type semiconductor layer is a textured surface; a first planarization layer formed on a first partial of the upper surface of the second conductivity type semiconductor layer; a first transparent conductive oxide layer formed on the first planarization layer and a second partial of the second conductivity type semiconductor layer, including a first portion in contact with the first planarization layer and a second portion having a first plurality of cavities in contact with the second conductivity type semiconductor layer; and a first electrode formed on the first portion of the first transparent conductive oxide layer. | 08-26-2010 |
| 20110001155 | LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A method of fabricating a light emitting device comprising: providing a substrate, wherein the substrate comprises a first major surface and a second major surface opposite to the first major surface, forming a plurality of light emitting stack layers on the first major surface, forming an etching protection layer on the plurality of light emitting stack layers, forming a plurality of discontinuous holes or continuous lines on the substrate by a laser beam with the depth of 10˜150 μm, cleaving the substrate through the plurality of discontinuous holes or continuous lines, providing a adhesion layer on the second major surface of the substrate, and expanding the adhesion layer to form a plurality of separated light emitting device. | 01-06-2011 |
| 20110121291 | LIGHT-EMITTING ELEMENT AND THE MANUFACTURING METHOD THEREOF - A light-emitting element includes a light-emitting stack for emitting light and a substrate structure including: a first substrate disposed under the light-emitting stack and having a first surface facing the light-emitting stack; and a second substrate disposed under the light-emitting stack and having a second surface facing the light-emitting stack; and a reflective layer formed between the first substrate and the second substrate and having an inclined angle not perpendicular to the first surface. | 05-26-2011 |
| 20130181245 | LIGHT-EMITTING DEVICE - A light-emitting device including: a light-emitting stacked layer having first conductivity type semiconductor layer, a light-emitting layer formed on the first conductivity type semiconductor layer, and a second conductivity type semiconductor layer formed on the light-emitting layer, wherein the upper surface of the second conductivity type semiconductor layer is a textured surface; a first planarization layer formed on a first part of the upper surface of the second conductivity type semiconductor layer; a first transparent conductive oxide layer formed on the first planarization layer and a second part of the second conductivity type semiconductor layer, including a first portion in contact with the first planarization layer and a second portion having a first plurality of cavities in contact with the second conductivity type semiconductor layer;; and a first electrode formed on the first portion of the first transparent conductive oxide layer. | 07-18-2013 |
| 20140145224 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method of fabricating an optoelectronic device, comprising: providing a first substrate; forming an epitaxial stack on the first substrate wherein the epitaxial stack comprising a first conductive-type semiconductor layer, an active layer and a second conductive-type semiconductor layer; etching an upper surface of the second conductive-type semiconductor layer and forming a first texture profile on the upper surface of the second conductive-type semiconductor layer; forming a passivation layer on the upper surface of the second conductive-type semiconductor layer; and etching an upper surface of the passivation layer forming a second texture profile on the upper surface of the passivation layer wherein the first texture profile is different from the second texture profile. | 05-29-2014 |
| Patent application number | Description | Published |
|---|
| 20110040563 | Voice Control Device and Voice Control Method and Display Device - A voice control device for a display device includes a voice receiver for receiving a voice signal, a voice recognition unit coupled to the voice receiver for recognizing the voice signal to generate a recognition result, a function decision unit coupled to the voice recognition unit for selecting an operating function from a plurality of operating functions according to the recognition result, and an execution unit coupled to the function decision unit for controlling the display device to perform the operating function. | 02-17-2011 |
| 20110063520 | Multimedia System and Remote Control Searching Method - A multimedia system includes a multimedia device and a remote control device. The multimedia device includes a trigger element, a detection unit and a wireless transmitter. The trigger element is utilized for generating a trigger signal. The detection unit is coupled to the trigger element, and is utilized for generating a searching signal when the trigger signal is detected. The wireless transmitter is coupled to the detection unit, and is utilized for wirelessly transmitting the searching signal. The remote control device is utilized for wirelessly transmitting a remote control signal to control operations of the multimedia device. The remote control device includes a wireless receiver and an alarm unit. The wireless receiver is utilized for receiving the searching signal. The alarm unit is coupled to the wireless receiver, and is utilized for generating an alarm effect according to the searching signal. | 03-17-2011 |
| 20110181336 | Output Buffer Circuit and Method for Avoiding Voltage Overshoot - An output buffer circuit for avoiding voltage overshoot includes an input stage, an output bias circuit, an output stage, a clamp circuit, and a control unit. The input stage includes a positive input terminal, for receiving an input voltage, and a negative input terminal. The input stage generates a current signal according to the input voltage. The output bias circuit is coupled to the input stage, for generating a dynamic bias according to the current signal. The output stage is coupled to the input stage and the output bias circuit, including an output terminal, reversely coupled to the positive input terminal, and at least one output transistor, coupled to the output bias circuit and the output terminal, for providing a driving current to the output terminal according to the dynamic bias to generate an output voltage. | 07-28-2011 |
| 20110187457 | Output Buffer Circuit Capable of Enhancing Stability - An output buffer circuit capable of enhancing stability includes an operational amplifier, a capacitive load and an output control unit. The operational amplifier has a positive input terminal, a negative input terminal and an output terminal, and generates an output voltage to the output terminal according to an input voltage received by the positive input terminal. The output control unit is coupled between the output terminal of the operational amplifier and the capacitive load, and is utilized for controlling electrical connection between the output terminal of the operational amplifier and the capacitive load to forma signal output path and for adjusting impedance of the signal output path when the signal output path is formed. | 08-04-2011 |
| 20120133632 | OPERATIONAL AMPLIFIER AND DISPLAY DRIVING CIRCUIT USING THE SAME - An operation amplifier, coupled to a control unit, includes: a differential input pair, coupled to an input signal and an output signal; a bias current source, couple to the differential input pair; an output stage, coupled to the bias current source; and a clamp circuit, coupled to the output stage. In discharge, when the control circuit is temporarily short circuit, an internal charge share inside the operational amplifier transiently lowers a first node voltage of the output stage and the clamp circuit pulls high the first node voltage of the output stage. In charge, when the control circuit is temporarily short circuit, an internal charge share inside the operational amplifier transiently pulls high a second node voltage of the output stage and the clamp circuit pulls low the second node voltage of the output stage. | 05-31-2012 |
| 20120146720 | ADAPTIVE AMPLIFICATION CIRCUIT - An adaptive amplification circuit is disclosed, which includes an operational amplifier including a variable bias current source for providing a variable bias current for the operational amplifier, a simulation unit for simulating operational characteristics of the operational amplifier and transforming a simulation input voltage to a simulation output voltage, and a bias control unit for generating a bias control signal to the variable bias current source according to the simulation output voltage so as to adjust the variable bias current. | 06-14-2012 |
| 20120223975 | Method and Apparatus for Driving a Display Device - The present invention discloses a driving device of a display device. The driving device comprises a gamma voltage generator, for generating a gamma voltage according to a control signal to a source driver of the display device, and a logic unit, for generating the control signal to the gamma voltage generator according to a difference among image properties of a plurality of frames to be displayed, to adjust the gamma voltage. | 09-06-2012 |
| 20120319770 | Output Buffer Circuit Capable of Enhancing Stability - An output buffer circuit capable of enhancing stability includes an operational amplifier, a capacitive load and an output control unit. The operational amplifier has a positive input terminal, a negative input terminal and an output terminal, and generates an output voltage to the output terminal according to an input voltage received by the positive input terminal. The output control unit is coupled between the output terminal of the operational amplifier and the capacitive load, and is utilized for controlling electrical connection between the output terminal of the operational amplifier and the capacitive load to form a signal output path and for adjusting impedance of the signal output path when the signal output path is formed. The output control unit comprises a plurality of output switches for individually turning on or off the electrical connection between the output terminal and the capacitive load of the operational amplifier. | 12-20-2012 |
| 20130328631 | ADAPTIVE AMPLIFICATION CIRCUIT - An adaptive amplification circuit is provided, which includes an operational amplifier comprising a variable bias current source for providing a variable bias current for the operational amplifier, an equivalent circuit of the operational amplifier for receiving an input voltage and generating an output voltage according to the input voltage, and a bias control unit for generating a bias control signal to the variable bias current source according to the output voltage so as to adjust the variable bias current. | 12-12-2013 |
| 20140285260 | Output Buffer Circuit Capable of Enhancing Stability - An output buffer circuit of a source driver includes an operational amplifier, having a first terminal as an output of the operational amplifier, and an output control unit, coupled between the output terminal of the operational amplifier and a second terminal for driving a load, to generate a variable impedance of a signal output path between the first terminal and the second terminal, wherein when the operational amplifier charges or discharges the second terminal to reach a predetermined level, the output control unit change a value of the variable impedance of the signal output path. | 09-25-2014 |
| Patent application number | Description | Published |
|---|
| 20100244891 | INTEGRATED CIRCUITS AND METHODS FOR PROVIDING IMPEDANCE OF DRIVER TO DRIVE DATA - An integrated circuit includes a pad coupled with a driver. The driver is capable of driving data to the pad. The driver is capable of providing a first set of resistance data substantially fitting to a first curve and a second set of resistance data substantially fitting to a second curve. A portion of at least one of the first set of resistance data and the second set of resistance data is an impedance of the driver to drive data | 09-30-2010 |
| 20130187677 | SYSTEM AND METHOD FOR CALIBRATING CHIPS IN A 3D CHIP STACK ARCHITECTURE - A system and method is disclosed for adaptively adjusting a driving strength of a signal between a first and second chip in a 3D architecture/stack. This may be used to adaptively calibrate a chip in a 3D architecture/stack. The system may include a transmission circuit on one chip and a receiver circuit on another chip. Alternatively, the system may include a transmission and receiver circuit on just one chip. | 07-25-2013 |
| 20130207694 | HIGH SPEED COMMUNICATION INTERFACE WITH AN ADAPTIVE SWING DRIVER TO REDUCE POWER CONSUMPTION - A high-speed bus interface with an adaptive swing driver. A high speed interface includes a transmitter and a receiver coupled via a bus. The transmitter has an adaptive swing driver and a voltage-regulating-module (VRM). The adaptive swing driver includes a post-driver and a pre-driver. The post-driver provides an adaptive swing output with a dedicated adaptive voltage power supply (VDDQ) and transition emphasis driving capacity with an internal logic voltage supply (VDD). The pre-driver provides the transition emphasis driving capacity with a pull-up and a pull-down signal path to the post-driver. The voltage-regulating-module is configured to supply signal to the adaptive swing driver. The receiver includes a comparator and a bit-error-rate detector. The comparator amplifies the adaptive swing output received from the transmitter via a bus, while the bit-error-rate detector diagnoses the amplified adaptive swing output received from the comparator. | 08-15-2013 |
| 20140006883 | SYSTEM AND METHOD FOR ALIGNING DATA BITS | 01-02-2014 |
| 20140195728 | DATA SAMPLING ALIGNMENT METHOD FOR MEMORY INFERFACE - The present disclosure relates to an interface comprising a memory controller and a memory unit coupled to the memory controller and configured to communicate with the memory controller through a first signal and a second signal. The interface further comprises a determination unit comprising judgment logic configured to send a control signal configured to align the first signal with the second signal. The memory controller further comprises a digitally-controlled delay line (DCDL) coupled to the determination unit and configured to receive the control signal, wherein the determination unit instructs the DCDL to adjust a delay of the first signal to align the first signal with the second signal. The memory controller further comprises a value register configured to store a signal delay value corresponding to alignment between the first signal with the second signal which is contained within the control signal. Other devices and methods are disclosed. | 07-10-2014 |
| 20140266152 | ON-CHIP EYE DIAGRAM CAPTURE - An eye diagram capture device includes a delay line arranged to receive a digital signal and output time delayed version of the digital signal. An edge detection circuit is arranged to receive the digital signal and the time delayed version of the digital signal, the edge detection circuit operating to output a signal corresponding to a logical value of the digital signal received coincident with an edge of the time delay version of the digital signal. A voltage comparator is arranged to receive the digital signal and a reference voltage. The voltage comparator operates to output a first signal when the a voltage of the digital signal and the reference voltage are equal to each other. | 09-18-2014 |
| 20150061110 | STACKED CHIP LAYOUT AND METHOD OF MAKING THE SAME - A stacked chip layout includes a central processing chip has a first area and a first active circuit block over the central processing chip, the first active circuit block has a second area. The stacked chip layout further includes a second active circuit block over the first active circuit block, the second active circuit block has a third area, the second active circuit block partially overlaps the first active circuit block and exposes a portion of the first active circuit block. The stacked chip layout further includes a third active circuit block over the second active circuit block, the third active circuit block has a fourth area, the third active circuit block partially overlaps at least one of the first active circuit block or the second active circuit block, and the third active circuit block exposes a portion of the first active circuit block and the second active circuit block. | 03-05-2015 |
