Patent application number | Description | Published |
20130093048 | Deposited Material and Method of Formation - A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period. | 04-18-2013 |
20140291745 | Deposited Material and Method of Formation - A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period. | 10-02-2014 |
20150034957 | NORMALLY-OFF ENHANCEMENT-MODE MISFET - The present disclosure relates to an enhancement mode MISFET device. In some embodiments, the MISFET device has an electron supply layer located on top of a layer of semiconductor material. A multi-dielectric layer, having two or more stacked dielectric materials sharing an interface having negative fixed charges, is disposed above the electron supply layer. A metal gate structure is disposed above the multi-dielectric layer, such that the metal gate structure is separated from the electron supply layer by the multi-dielectric layer. The multi-dielectric layer provides fixed charges at interfaces between the separate dielectric materials, which cause the transistor device to achieve a normally off disposition. | 02-05-2015 |
20150041874 | MIM Capacitors with Improved Reliability - A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer. | 02-12-2015 |
20150060773 | Organic Photosensitive Device with an Electron-Blocking and Hold-Transport Layer - The present disclosure provides a photosensitive device. The photosensitive device includes a donor-intermix-acceptor (PIN) structure. The PIN structure includes an organic hole transport layer; an organic electron transport layer; and an intermix layer sandwiched between the hole transport organic material layer and the electron transport organic material layer. The intermix layer includes a mixture of an n-type organic material and a p-type organic material. | 03-05-2015 |
20150060873 | Crystalline Layer for Passivation of III-N Surface - Some embodiments of the present disclosure relates to a crystalline passivation layer for effectively passivating III-N surfaces. Surface passivation of HEMTs reduces or eliminates the surface effects that can otherwise degrade device performance. The crystalline passivation layer reduces the degrading effects of surface traps and provides a good interface between a III-nitride surface and an insulator (e.g., gate dielectric formed over the passivation layer). | 03-05-2015 |
20150279922 | METHOD TO IMPROVE MIM DEVICE PERFORMANCE - The present disclosure relates to a method of forming a MIM capacitor using a post capacitor bottom metal treatment process to reduce a roughness of a top surface of a capacitor bottom metal layer, and an associated apparatus. In some embodiments, the method is performed by forming a capacitor bottom metal layer having a first metal material over a semiconductor substrate. A top surface of the capacitor bottom metal layer is exposed to one or more post capacitor bottom metal (CBM) treatment agents having oxygen. The one or more post CBM treatment agent reduce a roughness of the top surface and form an interface layer having the first metal material and oxygen onto and in direct contract with the top surface of the capacitor bottom metal layer. A capacitor dielectric layer is formed over the interface layer and a capacitor top metal layer is formed over the capacitor dielectric layer. | 10-01-2015 |
20150287917 | HIGH YIELD RRAM CELL WITH OPTIMIZED FILM SCHEME - The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a good yield, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer, and forming a variable resistance dielectric data storage layer having a first thickness onto the bottom electrode. A capping layer is formed onto the dielectric data storage layer. The capping layer has a second thickness that is in a range of between approximately 2 to approximately 3 times thicker than the first thickness. A top electrode is formed over the capping layer, and an upper metal interconnect layer is formed over the top electrode. | 10-08-2015 |
20150287918 | RRAM CELL BOTTOM ELECTRODE FORMATION - The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer using an atomic layer deposition (ALD) process to form at least a top portion of the bottom electrode. A dielectric data storage layer is formed onto the top portion of the bottom electrode in-situ with forming the top portion of the bottom electrode. A top electrode is formed over the dielectric data storage layer, and an upper metal interconnect layer is formed over the top electrode. By forming the top portion of the bottom electrode using an ALD process that is in-situ with the formation of the overlying dielectric data storage layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved. | 10-08-2015 |