Patent application number | Description | Published |
20080316660 | ELECTROSTATIC DISCHARGE AVOIDING CIRCUIT - An electrostatic discharge (ESD) avoiding circuit comprises an ESD detecting unit and a switch unit. The ESD detecting unit is coupled to a first conductive path for detecting whether the ESD happened or not. The switch unit is coupled between the first conductive path and a core circuit for switching whether the first conductive path is conducted to the core circuit or not according to a detection result of the ESD detecting unit. The ESD avoiding circuit can avoid an electrostatic current transmitting to the core circuit when the ESD is happened, and the ESD avoiding circuit can make the normal signal/voltage providing to the core circuit for operating when the ESD isn't happened. | 12-25-2008 |
20090168280 | ELECTROSTATIC DISCHARGE AVOIDING CIRCUIT - An ESD avoiding circuit includes a first ESD protection unit, an ESD detection unit, a switch unit, and an RC filter unit. The first ESD protection unit transmits an ESD current between a first conducting path and a second conducting path. The ESD detection unit is coupled to the first conducting path. The ESD detection unit includes an input terminal, and an output terminal coupled to the first ESD protection unit for detecting an ESD and controlling the first ESD protection unit to conduct the ESD current according to a detection result. The switch unit is coupled between the first conducting path and a core circuit and conducts the first conducting path to the core circuit according to signals of the input terminal and the output terminal of the ESD detection unit. The RC filter unit couples a first voltage to the input terminal of the ESD detection unit. | 07-02-2009 |
20090244985 | METHOD FOR ERASING A P-CHANNEL NON-VOLATILE MEMORY - A present invention relates to a method of erasing a P-channel non-volatile memory is provided. This P-channel non-volatile memory includes a select transistor and a memory cell connected in series and disposed on a substrate. In the method of erasing the P-channel non-volatile memory, holes are injected into a charge storage structure by substrate hole injection effect. Hence, the applied operational voltage is low, so the power consumption is lowered, and the efficiency of erasing is enhanced. As a result, an operational speed of the memory is accelerated, and the reliability of the memory is improved. | 10-01-2009 |
20100006924 | ONE-TIME PROGRAMMABLE READ-ONLY MEMORY - A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a third doped region, a first dielectric layer, a select gate, a second dielectric layer, a first channel, a second channel and a silicide layer is provided. The first doped region, the second doped region and the third doped region are disposed apart in a substrate. The first dielectric layer is disposed on the substrate between the first doped region and the second doped region. The select gate is disposed on the first dielectric layer. The second dielectric layer is disposed on the substrate between the second doped region and the third doped region. The silicide layer is disposed on the first doped region, the second doped region and the third doped region. The OTP-ROM stores data by a punch-through effect occurring between the second doped region and the third doped region. | 01-14-2010 |
20100014359 | OPERATING METHOD OF NON-VOLATILE MEMORY - An operating method of a non-volatile memory adapted for a non-volatile memory disposed on an SOI substrate including a first conductive type silicon body layer is provided. The non-volatile memory includes a gate, a charge storage structure, a second conductive type drain region, and a second conductive type source region. In operating such a non-volatile memory, voltages are applied to the gate, the second conductive type drain region, the second conductive type source region and the first conductive type silicon body layer beneath the gate, to inject electrons or holes in to the charge storage structure or evacuate the electrons from the charge storage structure by a method selected from a group consisting of channel hot carrier injection, source side injection, band-to-band tunnelling hot carrier injection and Fowler-Nordheim (F-N) tunnelling. | 01-21-2010 |
20110057243 | NON-VOLATILE MEMORY WITH A STABLE THRESHOLD VOLTAGE ON SOI SUBSTRATE - A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate. | 03-10-2011 |
20110242893 | NON-VOLATILE MEMORY UNIT CELL WITH IMPROVED SENSING MARGIN AND RELIABILITY - A non-volatile memory unit cell includes a first transistor pair and first and second control gates. The first transistor pair includes first and second transistors that are connected in series and of the same type. The first and second transistors have a first floating polysilicon gate and a second floating polysilicon gate, respectively. The first control gate is coupled to the first floating polysilicon gate through a tunneling junction and the second control gate is coupled to the second floating polysilicon gate through another tunneling junction. | 10-06-2011 |
20120273860 | NON-VOLATILE MEMORY UNIT CELL WITH IMPROVED SENSING MARGIN AND RELIABILITY - An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. | 11-01-2012 |
Patent application number | Description | Published |
20110299336 | SINGLE-POLYSILICON LAYER NON-VOLATILE MEMORY AND OPERATING METHOD THEREOF - A single-polysilicon layer non-volatile memory having a floating gate transistor, a program gate and a control gate is provided. The floating gate transistor has a floating gate and a tunneling dielectric layer. The floating gate is disposed on a substrate. The tunneling dielectric layer is disposed between the floating gate and the substrate. The program gate, the control gate and the erase gate are respectively disposed in the substrate under the floating gate separated by the tunneling dielectric layer. Therefore, during a program operation and an erase operation, charges are injected in and expelled out through different regions of the tunneling dielectric layer, so as to increase reliability of the non-volatile memory. | 12-08-2011 |
20120007161 | Semiconductor Non-volatile Memory - A method of forming a charge-storing layer in a non-volatile memory cell in a logic process includes forming a select gate over an active region of a substrate, forming long polysilicon gates partially overlapping the active region of the substrate, and filling the charge-storing layer between the long polysilicon gates. | 01-12-2012 |
20120087170 | Single Polysilicon Non-Volatile Memory - A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit comprises a plurality of local voltage boost circuits. Each local voltage boost circuit is shared by a corresponding memory cell of the plurality of memory cells. The programming verification circuit is coupled to the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming. Each local boost circuit isolates leakage current of a corresponding programmed memory cell, and prevents programming voltage failure due to current overloading at a corresponding voltage pumping circuit. | 04-12-2012 |
20120099361 | SEMICONDUCTOR CAPACITOR, ONE TIME PROGRAMMABLE MEMORY CELL AND FABRICATING METHOD AND OPERATING METHOD THEREOF - A one time programmable memory cell having a gate, a gate dielectric layer, a source region, a drain region, a capacitor dielectric layer and a conductive plug is provided herein. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The source region and the drain region are disposed in the substrate at the sides of the gate, respectively. The capacitor dielectric layer is disposed on the source region. The capacitor dielectric layer is a resistive protection oxide layer or a self-aligned silicide block layer. The conductive plug is disposed on the capacitor dielectric layer. The conductive plug is served as a first electrode of a capacitor and the source region is served as a second electrode of the capacitor. The one time programmable memory (OTP) cell is programmed by making the capacitor dielectric layer breakdown. | 04-26-2012 |
20120134205 | OPERATING METHOD FOR MEMORY UNIT - An operating method for a memory unit is provided, wherein the memory unit includes a well region, a select gate, a first gate, a second gate, an oxide nitride spacer, a first diffusion region, and a second diffusion region. The operating method for the memory unit comprises the following steps. During a programming operation, a breakdown voltage is coupled to the second diffusion region through a first channel region formed under the select gate. A programming voltage is sequentially or simultaneously applied to the first gate and the second gate to rupture a first oxide layer and a second oxide layer, wherein the first oxide layer is disposed between the first gate and the well region, and the second oxide layer is disposed between the second gate and the well region. | 05-31-2012 |
20120163072 | NON-VOLATILE SEMICONDUCTOR MEMORY CELL WITH DUAL FUNCTIONS - A non-volatile semiconductor memory cell with dual functions includes a substrate, a first gate, a second gate, a third gate, a charge storage layer, a first diffusion region, a second diffusion region, and a third diffusion region. The second gate and the third gate are used for receiving a first voltage corresponding to a one-time programming function of the dual function and a second voltage corresponding to a multi-time programming function of the dual function. The first diffusion region is used for receiving a third voltage corresponding to the one-time programming function and a fourth voltage corresponding to the multi-time programming function. The second diffusion region is used for receiving a fifth voltage corresponding to the multi-time programming function. | 06-28-2012 |
20120223381 | Non-volatile memory structure and method for manufacturing the same - A non-volatile memory structure is disclosed. LDD regions may be optionally formed through an ion implantation using a mask for protection of a gate channel region of an active area. Two gates are apart from each other and disposed on an isolation structure on two sides of a middle region of the active area, respectively. The two gates may be each entirely disposed on the isolation structure or partially to overlap a side portion of the middle region of the active area. A charge-trapping layer and a dielectric layer are formed between the two gates and on the active area to serve for a storage node function. They may be further formed onto all sidewalls of the two gates to serve as spacers. Source/drain regions are formed through ion implantation using a mask for protection of the gates and the charge-trapping layer. | 09-06-2012 |
20120314474 | NON-VOLATILE MEMORY CELL STRUCTURE AND METHOD FOR PROGRAMMING AND READING THE SAME - The present invention provides a non-volatile memory cell structure. A first isolation structure is disposed on a substrate and a semiconductor layer is disposed on the first isolation structure to form a silicon on insulator device. A first doping region is made of a portion of the semiconductor layer. A gate is disposed on the first doping region. A gate oxide layer is sandwiched between the first doping region and the gate. A second doping region is disposed within the semiconductor layer and outside the first doping region. A second doping region is in direct contact with the first doping region. A second isolation structure is disposed on the first isolation structure. Further, the second isolation structure surrounds the first doping region and the second doping region. The second isolation structure is also in direct contact with the first doping region and the second doping region. | 12-13-2012 |
20130010518 | ANTI-FUSE MEMORY ULTILIZING A COUPLING CHANNEL AND OPERATING METHOD THEREOF - An anti-fuse memory with coupling channel is provided. The anti-fuse memory includes a substrate of a first conductive type, a doped region of a second conductive type, a coupling gate, a gate dielectric layer, an anti-fuse gate, and an anti-fuse layer. The substrate has an isolation structure. The doped region is disposed in the substrate. A channel region is defined between the doped region and the isolation structure. The coupling gate is disposed on the substrate between the doped region and the isolation structure. The coupling gate is adjacent to the doped region. The gate dielectric layer is disposed between the coupling gate and the substrate. The anti-fuse gate is disposed on the substrate between the coupling gate and the isolation structure. The anti-fuse gate and the coupling gate have a space therebetween. The anti-fuse layer is disposed between the anti-fuse gate and the substrate. | 01-10-2013 |
20130176793 | FLASH MEMORY APPARATUS - A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cells and a plurality of programming voltage control generators. Each of the memory cells receives a programming control voltage through a control end thereof, and executes data programming operation according to the programming control voltages. Each of the programming voltage control generators includes a pre-charge voltage transmitter and a pumping capacitor. The pre-charge voltage transmitter provides pre-charge voltage to the end of each of the corresponding memory cells according to pre-charge enable signal during a first period. A pumping voltage is provided to the pumping capacitor during a second period, and the programming control voltage is generated at the control end of each of the memory cells. | 07-11-2013 |
20130234227 | ERASABLE PROGRAMMABLE SINGLE-PLOY NONVOLATILE MEMORY - An erasable programmable single-poly nonvolatile memory includes a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region is connected to an erase line voltage. | 09-12-2013 |
20130234228 | ERASABLE PROGRAMMABLE SINGLE-PLOY NONVOLATILE MEMORY - An erasable programmable single-poly nonvolatile memory includes a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer. | 09-12-2013 |
20130237048 | METHOD OF FABRICATING ERASABLE PROGRAMMABLE SINGLE-PLOY NONVOLATILE MEMORY - The present invention provides method of fabricating an erasable programmable single-poly nonvolatile memory, comprising steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covered on a surface of the first area, wherein the second gate oxide layer is extended to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covered on the first and the second gate oxide layers; and defining a second type doped region in the DDD region and a first type doped regions in the second type well region. | 09-12-2013 |
20130242663 | PROGRAMMING INHIBIT METHOD OF NONVOLATILE MEMORY APPARATUS FOR REDUCING LEAKAGE CURRENT - The invention provides a nonvolatile memory apparatus. The nonvolatile memory apparatus comprises a plurality of memory cells and a signal generator. The memory cells are arranged in an array, and each of the memory cells has a control gate terminal, a floating gate, a source line terminal, a bit-line terminal, a selected gate terminal and a word-line terminal. The signal generator is coupled to the memory cells. When the nonvolatile memory apparatus executes a programming operation, the signal generator provides a programming signal to the control gate terminals of a plurality of inhibited memory cells among the memory cells. Wherein, the programming signal is a pulse signal with a direct-current (DC) offset voltage. | 09-19-2013 |
20130302977 | METHOD OF FABRICATING ERASABLE PROGRAMMABLE SINGLE-PLOY NONVOLATILE MEMORY - The present invention provides method of fabricating an erasable programmable single-poly nonvolatile memory, comprising steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covered on a surface of the first area, wherein the second gate oxide layer is extended to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covered on the first and the second gate oxide layers; and defining a second type doped region in the DDD region and a first type doped regions in the second type well region. | 11-14-2013 |
20140056051 | ONE-BIT MEMORY CELL FOR NONVOLATILE MEMORY AND ASSOCIATED CONTROLLING METHOD - A one-bit memory cell for a nonvolatile memory includes a bit line and a plurality of serially-connected storage units. The bit line is connected to the serially-connected storage units. Each storage unit includes a first doped region, a second doped region and a third doped region, which are formed in a surface of a substrate. A first gate structure is disposed over a first channel region between the first doped region and the second doped region. The first gate structure is connected to a control signal line. A second gate structure is disposed over a second channel region between the second doped region and the third doped region. The second gate structure is connected to an anti-fuse signal line. | 02-27-2014 |
20140098591 | ANTIFUSE OTP MEMORY CELL WITH PERFORMANCE IMPROVEMENT PREVENTION AND OPERATING METHOD OF MEMORY - Provided is an OTP memory cell including a first antifuse unit, a second antifuse unit, a select transistor, and a well region. The first and the second antifuse unit respectively include an antifuse layer and an antifuse gate disposed on a substrate in sequence. The select transistor includes a select gate, a gate dielectric layer, a first doped region, and a second doped region. The select gate is disposed on the substrate. The gate dielectric layer is disposed between the select gate and the substrate. The first and the second doped region are respectively disposed in the substrate at two sides of the select gate, wherein the second doped region is disposed in the substrate at the periphery of the first and the second antifuse unit. The well region is disposed in the substrate below the first and the second antifuse unit and is connected to the second doped region. | 04-10-2014 |
20140101352 | INTERRUPT CONTROLLER, APPARATUS INCLUDING INTERRUPT CONTROLLER, AND CORRESPONDING METHODS FOR PROCESSING INTERRUPT REQUEST EVENT(S) IN SYSTEM INCLUDING PROCESSOR(S) - An interrupt controller coupled to a plurality of processors is provided to rout at least one interrupt request event to at least one of the processors. The interrupt controller includes a receiving circuit and a controlling circuit. The receiving circuit receives at least one interrupt input, and the controlling circuit, generates the at least one interrupt request event based on the received at least one interrupt input and routes the at least one interrupt request event generated to the at least one of the processors. The plurality of processors including at least a first processor and a second processor, the first and second processors arranged to process interrupt request event(s), and the controlling circuit is arranged to withdraw/cancel assertion of an interrupt request event that has been transmitted to the first processor. | 04-10-2014 |
20140293673 | NONVOLATILE MEMORY CELL STRUCTURE AND METHOD FOR PROGRAMMING AND READING THE SAME - A nonvolatile memory cell structure includes a doping well disposed in a substrate, an antifuse gate disposed on the doping well, a drain disposed in the substrate, an optional select gate disposed on the doping well and an optional shallow trench isolation disposed inside the doping well. | 10-02-2014 |
20140340955 | ONE TIME PROGRAMABLE MEMORY CELL AND METHOD FOR PROGRAMING AND READING A MEMORY ARRAY COMPRISING THE SAME - The present invention provides a one time programmable (OTP) memory cell including a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal, a first source terminal, and two first source/drain extension areas respectively coupled to the first drain terminal and the first source terminal. The following gate transistor has a second gate terminal, a second drain terminal, a second source terminal coupled to the first drain terminal, and two second source/drain extension areas respectively coupled to the second drain terminal and the second source terminal. The antifuse varactor has a third gate terminal, a third drain terminal, a third source terminal coupled to the second drain terminal, and a third source/drain extension area coupled with the third drain terminal and the third source terminal for shorting the third drain terminal and the third source terminal. | 11-20-2014 |