Patent application number | Description | Published |
20100038523 | IMAGE SENSOR WITH BURIED SELF ALIGNED FOCUSING ELEMENT - An image sensor includes an optical sensor region, a stack of dielectric and metal layers, and an embedded layer. The optical sensor is disposed within a semiconductor substrate. The stack of dielectric and metal layers are disposed on the front side of the semiconductor substrate above the optical sensor region. The embedded focusing layer is disposed on the backside of the semiconductor substrate in a Backside Illuminated (BSI) image sensor, supported by a support grid, or a support grid composed of the semiconductor substrate. | 02-18-2010 |
20100323470 | BACKSIDE ILLUMINATED IMAGE SENSOR HAVING DEEP LIGHT REFLECTIVE TRENCHES - An array of pixels is formed using a semiconductor layer having a frontside and a backside through which incident light is received. Each pixel typically includes a photosensitive region formed in the semiconductor layer and a trench formed adjacent to the photosensitive region. The trench causes the incident light to be directed away from the trench and towards the photosensitive region. | 12-23-2010 |
20110068429 | IMAGE SENSOR WITH CONTACT DUMMY PIXELS - An image sensor array includes a substrate layer, a metal layer, an epitaxial layer, a plurality of imaging pixels, and a contact dummy pixel. The metal layer is disposed above the substrate layer. The epitaxial layer is disposed between the substrate layer and the metal layer. The imaging pixels are disposed within the epitaxial layer and each include a photosensitive element for collecting an image signal. The contact dummy pixel is dispose within the epitaxial layer and includes an electrical conducting path through the epitaxial layer. The electrical conducting path couples to the metal layer above the epitaxial layer. | 03-24-2011 |
20110085067 | MULTILAYER IMAGE SENSOR PIXEL STRUCTURE FOR REDUCING CROSSTALK - An image sensor pixel includes a substrate, a first epitaxial layer, a collector layer, a second epitaxial layer and a light collection region. The substrate is doped to have a first conductivity type. The first epitaxial layer is disposed over the substrate and doped to have the first conductivity type as well. The collector layer is selectively disposed over at least a portion of the first epitaxial layer and doped to have a second conductivity type. The second epitaxial layer is disposed over the collector layer and doped to have the first conductivity type. The light collection region collects photo-generated charge carriers and is disposed within the second epitaxial layer. The light collection region is also doped to have the second conductivity type. | 04-14-2011 |
20110089311 | TRENCH TRANSFER GATE FOR INCREASED PIXEL FILL FACTOR - An image sensor provides high scalability and reduced image lag. The sensor includes a first imaging pixel that has a first photodiode region formed in a substrate of the image sensor. The sensor also includes a first vertical transfer transistor coupled to the first photodiode region. The first vertical transfer transistor can be used to establish an active channel. The active channel typically extends along the length of the first vertical transfer transistor and couples the first photodiode region to a floating diffusion. | 04-21-2011 |
20110089517 | CMOS IMAGE SENSOR WITH HEAT MANAGEMENT STRUCTURES - An image sensor includes a device wafer substrate of a device wafer, a device layer of the device wafer, and optionally a heat control structure and/or a heat sink. The device layer is disposed on a frontside of the device wafer substrate and includes a plurality of photosensitive elements disposed within a pixel array region and peripheral circuitry disposed within a peripheral circuits region. The photosensitive elements are sensitive to light incident on a backside of the device wafer substrate. The heat control structure is disposed within the device wafer substrate and thermally isolates the pixel array region from the peripheral circuits region to reduce heat transfer between the peripheral circuits region and the pixel array region. The heat sink conducts heat away from the device layer. | 04-21-2011 |
20110115002 | BACKSIDE ILLUMINATED IMAGING SENSOR WITH REINFORCED PAD STRUCTURE - A backside illuminated imaging sensor with reinforced pad structure includes a device layer, a metal stack, an opening and a frame. The device layer has an imaging array formed in a front side of the device layer and the imaging array is adapted to receive light from a back side of the device layer. The metal stack is coupled to the front side of the device layer where the metal stack includes at least one metal interconnect layer having a metal pad. The opening extends from the back side of the device layer to the metal pad to expose the metal pad for wire bonding. The frame is disposed within the opening to structurally reinforce the metal pad. | 05-19-2011 |
20110140221 | IMAGE SENSOR HAVING CURVED MICRO-MIRRORS OVER THE SENSING PHOTODIODE AND METHOD FOR FABRICATING - The invention involves the integration of curved micro-mirrors over a photodiode active area (collection area) in a CMOS image sensor (CIS) process. The curved micro-mirrors reflect light that has passed through the collection area back into the photo diode. The curved micro-mirrors are best implemented in a backside illuminated device (BSI). | 06-16-2011 |
20110169991 | IMAGE SENSOR WITH EPITAXIALLY SELF-ALIGNED PHOTO SENSORS - An image sensor pixel includes a substrate doped to have a first conductivity type. A first epitaxial layer is disposed over the substrate and doped to also have the first conductivity type. A transfer transistor gate is formed on the first epitaxial layer. An epitaxially grown photo-sensor region is disposed in the first epitaxial layer and has a second conductivity type. The epitaxially grown photo-sensor region includes an extension region that extends under a portion of the transfer transistor gate. | 07-14-2011 |
20110177650 | CMOS IMAGE SENSOR WITH SELF-ALIGNED PHOTODIODE IMPLANTS - An example method of forming a pinned photodiode includes applying a photoresist mask to a semiconductor layer at a location where a transfer gate will subsequently be formed. First dopant ions are then implanted at a first angle to form a first dopant region under an edge of the photoresist mask. Next, a photoresist mask is etched such that a thickness of the photoresist mask is reduced to form a trimmed photoresist mask. Second dopant ions are then implanted at a second angle to form a second dopant region, wherein the second dopant ions are shadowed by the trimmed photoresist mask to exclude the second dopant ions from a region partially above the first dopant region and adjacent to an edge of the trimmed photoresist mask. | 07-21-2011 |
20110199518 | IMAGE SENSOR WITH IMPROVED BLACK LEVEL CALIBRATION - An imaging system capable of black level calibration includes an imaging pixel array, at least one black reference pixel, and peripheral circuitry. The imaging pixel array includes a plurality of active pixels each coupled to capture image data. The black reference pixel is coupled to generate a black reference signal for calibrating the image data. Light transmitting layers are disposed on a first side of a pixel array die including the imaging system and cover at least the imaging pixel array and the black reference pixel. A light shielding layer is disposed on the first side of the pixel array die and covers a portion of the light transmitting layers and the black reference pixel without covering the imaging pixel array. | 08-18-2011 |
20110241090 | HIGH FULL-WELL CAPACITY PIXEL WITH GRADED PHOTODETECTOR IMPLANT - Embodiments of a process for forming a photodetector region in a CMOS pixel by dopant implantation, the process comprising masking a photodetector area of a surface of a substrate for formation of the photodetector region, positioning the substrate at a plurality of twist angles, and at each of the plurality of twist angles, directing dopants at the photodetector area at a selected tilt angle. Embodiments of a CMOS pixel comprising a photodetector region formed in a substrate, the photodetector region comprising overlapping first and second dopant implants, wherein the overlap region has a different dopant concentration than the non-overlapping parts of the first and second implants, a floating diffusion formed in the substrate, and a transfer gate formed on the substrate between the photodetector and the transfer gate. Other embodiments are disclosed and claimed. | 10-06-2011 |
20110260221 | LASER ANNEAL FOR IMAGE SENSORS - A technique for fabricating an image sensor including a pixel circuitry region and a peripheral circuitry region includes fabricating front side components on a front side of the image sensor. A dopant layer is implanted on a backside of the image sensor. A anti-reflection layer is formed on the backside and covers a first portion of the dopant layer under the pixel circuitry region while exposing a second portion of the dopant layer under the peripheral circuitry region. The first portion of the dopant layer is laser annealed from the backside of the image sensor through the anti-reflection layer. The anti-reflection layer increases a temperature of the first portion of the dopant layer during the laser annealing. | 10-27-2011 |
20120013777 | CMOS IMAGE SENSOR WITH IMPROVED PHOTODIODE AREA ALLOCATION - Embodiments of an apparatus comprising a pixel array comprising a plurality of macropixels. Each macropixel includes a pair of first pixels each including a color filter for a first color, the first color being one to which pixels are most sensitive, a second pixel including a color filter for a second color, the second color being one to which the pixels are least sensitive and a third pixel including a color filter for a third color, the third color being one to which pixels have a sensitivity between the least sensitive and the most sensitive, wherein the first pixels each occupy a greater proportion of the light-collection area of the macropixel than either the second pixel or the third pixel. Corresponding process and system embodiments are disclosed and claimed. | 01-19-2012 |
20120018620 | BACKSIDE ILLUMINATED IMAGING SENSOR WITH VERTICAL PIXEL SENSOR - A backside illuminated imaging sensor includes a vertical stacked sensor that reduces cross talk by using different silicon layers to form photodiodes at separate levels within a stack (or separate stacks) to detect different colors. Blue light-, green light-, and red light-detection silicon layers are formed, with the blue light detection layer positioned closest to the backside of the sensor and the red light detection layer positioned farthest from the backside of the sensor. An anti-reflective coating (ARC) layer can be inserted in between the red and green light detection layers to reduce the optical cross talk captured by the red light detection layer. Amorphous polysilicon can be used to form the red light detection layer to boost the efficiency of detecting red light. | 01-26-2012 |
20120019695 | IMAGE SENSOR HAVING DARK SIDEWALLS BETWEEN COLOR FILTERS TO REDUCE OPTICAL CROSSTALK - An apparatus and technique for fabricating an image sensor including the dark sidewall films disposed between adjacent color filters. The image sensor further includes an array of photosensitive elements disposed in a substrate layer, a color filter array (“CFA”) including CFA elements having at least two different colors disposed on a light incident side of the substrate layer, and an array of microlenses disposed over the CFA. Each microlens is aligned to direct light incident on the light incident side of the image sensor through a corresponding CFA element to a corresponding photosensitive element. The dark sidewall films are disposed on sides of the CFA elements and separate adjacent ones of the CFA elements having different colors. | 01-26-2012 |
20120019696 | IMAGE SENSOR WITH DUAL ELEMENT COLOR FILTER ARRAY AND THREE CHANNEL COLOR OUTPUT - A color image sensor is disclosed. The color image sensor includes a pixel array including a color filter array (“CFA”) overlaying an array of photo-sensors for acquiring a color image. The CFA includes first color filter elements of a first color overlaying a first group of the photo-sensors and second color filter elements of a second color overlaying a second group of the photo-sensors. The first color filter elements contribute to a first color channel of the color image and the second color filter elements contribute to a second color channel of the color image. The color image sensor further includes a color combiner unit coupled to combine the first color channel with the second color channel to generate a third color channel of the color image based on the first and second color channels. An output port is coupled to the pixel array to output the color image having three color channels including the first, second, and third color channels. | 01-26-2012 |
20120038014 | BACKSIDE ILLUMINATED IMAGE SENSOR WITH STRESSED FILM - A backside illuminated (“BSI”) complementary metal-oxide semiconductor (“CMOS”) image sensor includes a photosensitive region disposed within a semiconductor layer and a stress adjusting layer. The photosensitive region is sensitive to light incident on a backside of the BSI CMOS image sensor to collect an image charge. The stress adjusting layer is disposed on a backside of the semiconductor layer to establish a stress characteristic that encourages photo-generated charge carriers to migrate towards the photosensitive region. | 02-16-2012 |
20120080765 | METHOD OF DAMAGE-FREE IMPURITY DOPING FOR CMOS IMAGE SENSORS - A method of fabricating a backside-illuminated pixel. The method includes forming frontside components of the pixel on or in a front side of a substrate, the frontside components including a photosensitive region of a first polarity. The method further includes forming a pure dopant region of a second polarity on a back side of the substrate, applying a laser pulse to the backside of the substrate to melt the pure dopant region, and recrystallizing the pure dopant region to form a backside doped layer. Corresponding apparatus embodiments are disclosed and claimed. | 04-05-2012 |
20120086844 | CIRCUIT AND PHOTO SENSOR OVERLAP FOR BACKSIDE ILLUMINATION IMAGE SENSOR - A method of operation of a backside illuminated (BSI) pixel array includes acquiring an image signal with a first photosensitive region of a first pixel within the BSI pixel array. The image signal is generated in response to light incident upon a backside of the first pixel. The image signal acquired by the first photosensitive region is transferred to pixel circuitry of the first pixel disposed on a frontside of the first pixel opposite the backside. The pixel circuitry at least partially overlaps the first photosensitive region of the first pixel and extends over die real estate above a second photosensitive region of a second pixel adjacent to the first pixel such that the second pixel donates die real estate unused by the second pixel to the first pixel to accommodate larger pixel circuitry than would fit within the first pixel. | 04-12-2012 |
20120104525 | IMAGE SENSOR WITH COLOR PIXELS HAVING UNIFORM LIGHT ABSORPTION DEPTHS - An example image sensor includes first, second, and third micro-lenses. The first micro-lens is in a first color pixel and has a first curvature and a first height. The second micro-lens is in a second color pixel and has a second curvature and a second height. The third micro-lens is in a third color pixel and has a third curvature and a third height. The first curvature is the same as both the second curvature and the third curvature and the first height is greater than the second height and the second height is greater than the third height, such that light absorption depths for the first, second, and third color pixels are the same. | 05-03-2012 |
20120153123 | IMAGE SENSOR HAVING SUPPLEMENTAL CAPACITIVE COUPLING NODE - An image sensor includes a pixel array, a bit line, supplemental capacitance node line, and a supplemental capacitance circuit. The pixel array includes a plurality of pixel cells each including a floating diffusion (“FD”) node and a photosensitive element coupled to selectively transfer image charge to the FD node. The bit line is coupled to selectively conduct image data output from a first group of the pixel cells. The supplemental capacitance node line is coupled to the FD node of a second group of the pixel cells to selectively couple a supplemental capacitance to the FD nodes of the second group in response to a control signal. In various embodiments, the first and second group of pixel cells may be the same group or a different group of the pixel cells and may add a capacitive boost feature or a multi conversion gain feature. | 06-21-2012 |
20120175722 | SEAL RING SUPPORT FOR BACKSIDE ILLUMINATED IMAGE SENSOR - A backside illuminated imaging sensor with a seal ring support includes an epitaxial layer having an imaging array formed in a front side of the epitaxial layer. A metal stack is coupled to the front side of the epitaxial layer, wherein the metal stack includes a seal ring formed in an edge region of the imaging sensor. An opening is included that extends from the back side of the epitaxial layer to a metal pad of the seal ring to expose the metal pad. The seal ring support is disposed on the metal pad and within the opening to structurally support the seal ring. | 07-12-2012 |
20120235212 | BACKSIDE-ILLUMINATED (BSI) IMAGE SENSOR WITH REDUCED BLOOMING AND ELECTRICAL SHUTTER - Embodiments of a pixel including a photosensitive region formed in a surface of a substrate and an overflow drain formed in the surface of the substrate at a distance from the photosensitive area, an electrical bias of the overflow drain being variable and controllable. Embodiments of a pixel including a photosensitive region formed in a surface of a substrate, a source-follower transistor coupled to the photosensitive region, the source-follower transistor including a drain, and a doped bridge coupling the photosensitive region to the drain of the source-follower transistor. | 09-20-2012 |
20120249845 | IMAGE SENSOR WITH IMPROVED BLACK LEVEL CALIBRATION - An imaging system capable of black level calibration includes an imaging pixel array, at least one black reference pixel, and peripheral circuitry. The imaging pixel array includes a plurality of active pixels each coupled to capture image data. The black reference pixel is coupled to generate a black reference signal for calibrating the image data. Light transmitting layers are disposed on a first side of a pixel array die including the imaging system and cover at least the imaging pixel array and the black reference pixel. A light shielding layer is disposed on the first side of the pixel array die and covers a portion of the light transmitting layers and the black reference pixel without covering the imaging pixel array. | 10-04-2012 |
20120261730 | FLOATING DIFFUSION STRUCTURE FOR AN IMAGE SENSOR - An image sensor including a pixel array having a floating diffusion region of a pixel which is disposed in a substrate, the floating diffusion region to receive a charge from a photosensitive region. In an embodiment, a transfer gate disposed on the substrate, wherein a portion of the transfer gate forms a cavity extending through the transfer gate. In another embodiment, a cavity extending through a transfer gate exposes a floating diffusion region. | 10-18-2012 |
20120280109 | METHOD, APPARATUS AND SYSTEM TO PROVIDE CONDUCTIVITY FOR A SUBSTRATE OF AN IMAGE SENSING PIXEL - Techniques for promoting conductivity in a substrate for a pixel array. In an embodiment, an isolation region and a dopant well are disposed within an epitaxial layer adjoining the substrate, where a portion of the dopant well is between the substrate and a portion of the isolation well. In another embodiment, a contact is further disposed within the epitaxial layer, where a portion of the isolation region surrounds a portion of the contact. | 11-08-2012 |
20120282728 | BACKSIDE ILLUMINATED IMAGING SENSOR WITH REINFORCED PAD STRUCTURE - A method of fabricating a backside illuminated imaging sensor that includes a device layer, a metal stack, and an opening is disclosed. The device layer has an imaging array formed in a front side of the device layer, where the imaging array is adapted to receive light from a back side of the device layer. The metal stack is coupled to the front side of the device layer and includes at least one metal interconnect layer having a metal pad. The opening extends from the back side of the device layer to the metal pad to expose the metal pad for wire bonding. The method includes depositing a film on the back side of the device layer and within the opening, then etching the film to form a frame within the opening to structurally reinforce the metal pad. | 11-08-2012 |
20120302000 | LASER ANNEAL FOR IMAGE SENSORS - A technique for fabricating an image sensor including a pixel circuitry region and a peripheral circuitry region includes fabricating front side components on a front side of the image sensor. A dopant layer is implanted on a backside of the image sensor. A anti-reflection layer is formed on the backside and covers a first portion of the dopant layer under the pixel circuitry region while exposing a second portion of the dopant layer under the peripheral circuitry region. The first portion of the dopant layer is laser annealed from the backside of the image sensor through the anti-reflection layer. The anti-reflection layer increases a temperature of the first portion of the dopant layer during the laser annealing. | 11-29-2012 |
20120313197 | IN-PIXEL HIGH DYNAMIC RANGE IMAGING - Embodiments of the invention describe providing high dynamic range imaging (HDRI or simply HDR) to an imaging pixel by coupling a floating diffusion node of the imaging pixel to a plurality of metal-oxide semiconductor (MOS) capacitance regions. It is understood that a MOS capacitance region only turns “on” (i.e., changes the overall capacitance of the floating diffusion node) when the voltage at the floating diffusion node (or a voltage difference between a gate node and the floating diffusion node) is greater than its threshold voltage; before the MOS capacitance region is “on” it does not contribute to the overall capacitance or conversion gain of the floating diffusion node. | 12-13-2012 |
20130001661 | HIGH FULL-WELL CAPACITY PIXEL WITH GRADED PHOTODETECTOR IMPLANT - Embodiments of a process for forming a photodetector region in a CMOS pixel by dopant implantation, the process comprising masking a photodetector area of a surface of a substrate for formation of the photodetector region, positioning the substrate at a plurality of twist angles, and at each of the plurality of twist angles, directing dopants at the photodetector area at a selected tilt angle. Embodiments of a CMOS pixel comprising a photodetector region formed in a substrate, the photodetector region comprising overlapping first and second dopant implants, wherein the overlap region has a different dopant concentration than the non-overlapping parts of the first and second implants, a floating diffusion formed in the substrate, and a transfer gate formed on the substrate between the photodetector and the transfer gate. Other embodiments are disclosed and claimed. | 01-03-2013 |
20130009043 | IMAGE SENSOR HAVING SUPPLEMENTAL CAPACITIVE COUPLING NODE - An image sensor includes a pixel array, a bit line, a supplemental capacitance node line, and a control circuit. The pixel array includes a plurality of pixel cells each including a floating diffusion (“FD”) node and a photosensitive element coupled to selectively transfer image charge to the FD node. The bit line is coupled to selectively conduct image data output from a first group of the pixel cells. The supplemental capacitance node line is coupled to the FD node of a second group of the pixel cells different from the first group. The control circuit is coupled to the supplemental capacitance node line to selectively increase the potential at the FD node of each of the pixel cells of the second group by selectively asserting a FD boost signal on the supplemental capacitance node line. | 01-10-2013 |
20130032921 | BACKSIDE ILLUMINATED IMAGE SENSOR WITH STRESSED FILM - An image sensor includes a photosensitive region disposed within a semiconductor layer and a stress adjusting layer. The photosensitive region is sensitive to light incident through a first side of the image sensor to collect an image charge. The stress adjusting layer is disposed over the first side of the semiconductor layer to establish a stress characteristic that encourages photo-generated charge carriers to migrate towards the photosensitive region. | 02-07-2013 |
20130033627 | COLOR FILTER PATTERNING USING HARD MASK - Embodiments are disclosed of an apparatus comprising a color filter arrangement including a set of color filters. The set of color filters includes a pair of first color filters, each having first and second hard mask layers formed thereon, a second color filter having the first hard mask layer formed thereon, and a third color filter having no hard mask layer formed thereon. Other embodiments are disclosed and claimed. | 02-07-2013 |
20130033629 | IMAGE SENSOR WITH IMPROVED BLACK LEVEL CALIBRATION - An imaging system capable of black level calibration includes an imaging pixel array, at least one black reference pixel, and peripheral circuitry. The imaging pixel array includes a plurality of active pixels each coupled to capture image data. The black reference pixel is coupled to generate a black reference signal for calibrating the image data. Light transmitting layers are disposed on a first side of a pixel array die including the imaging system and cover at least the imaging pixel array and the black reference pixel. A light shielding layer is disposed on the first side of the pixel array die and covers a portion of the light transmitting layers and the black reference pixel without covering the imaging pixel array. | 02-07-2013 |
20130056808 | Isolation Area Between Semiconductor Devices Having Additional Active Area - An isolation area that provides additional active area between semiconductor devices on an integrated circuit is described. In one embodiment, the invention includes a complementary metal oxide semiconductor transistor of an image sensor having a source, a drain, and a gate between the source and the drain, the transistor having a channel to couple the source and the drain under the influence of the gate, and an isolation barrier surrounding a periphery of the source and the drain to isolate the source and the drain from other devices, wherein the isolation barrier is distanced from the central portion of the channel. | 03-07-2013 |
20130063641 | DUAL-SIDED IMAGE SENSOR - An apparatus for a dual-sided image sensor is described. The dual-sided image sensor captures frontside image data incident upon a frontside of the dual-sided image sensor within an array of photosensitive regions integrated into a semiconductor layer of the dual-sided image sensor. Backside image data incident upon a backside of the dual-sided image sensor is also captured within the same array of photosensitive regions. | 03-14-2013 |
20130069188 | DUAL-FACING CAMERA ASSEMBLY - Embodiments of the invention relate to a camera assembly including a rear-facing camera and a front-facing camera operatively coupled together (e.g., bonded, stacked on a common substrate). | 03-21-2013 |
20130082163 | IMAGE SENSOR WITH MICRO-LENS COATING - Techniques and architectures for providing a coating for one or more micro-lenses of a pixel array. In an embodiment, a pixel element includes a micro-lens and a coating portion extending over a surface of the micro-lens, where a profile of the coating portion is super-conformal to, or at least conformal to, a profile of the micro-lens. In another embodiment, the coating portion is formed at least in part by orienting the surface of the micro-lens to face generally downward with the direction of gravity, the orienting to allow a fluid coating material to flow for formation of the coating portion. | 04-04-2013 |
20130083223 | IMAGE SENSOR WITH DUAL ELEMENT COLOR FILTER ARRAY AND THREE CHANNEL COLOR OUTPUT - A color image sensor includes a pixel array including CFA overlaying an array of photo-sensors for acquiring color image data. The CFA includes first color filter elements of a first color overlaying a first group of the photo-sensors and second color filter elements of a second color overlaying a second group of the photo-sensors. The first group of photo-sensors generate first color signals of a first color channel and the second group of photo-sensors generate second color signals of a second color channel. The color image sensor further includes a color signal combiner circuit (“CSCC”) coupled to receive the first and second color signals output from the pixel array. The CSCC includes a combiner coupled to combine the first and second colors signals to generate third color signals of a third color channel. An output port is coupled to the CSCC to output the color image data. | 04-04-2013 |
20130083224 | IMAGE SENSOR WITH DUAL ELEMENT COLOR FILTER ARRAY AND THREE CHANNEL COLOR OUTPUT - A color image sensor includes a pixel array including a CFA overlaying an array of photo-sensors for acquiring a color image. The CFA includes first color filter elements of a first color overlaying a first group of the photo-sensors, second color filter elements of a second color overlaying a second group of the photo-sensors, and a plurality of filter stacks overlaying a third group of the photo-sensors. The first group generates first color signals of a first color channel and the second group generates second color signals of a second color channel. Each of the filter stacks includes a first stacked filter of the first color and a second stacked filter of the second color. A sensitivity of the filter stacks equals a product of sensitivities of the first and the second stacked filters and the filter stacks generate a third color channel. | 04-04-2013 |
20130092982 | PARTIAL BURIED CHANNEL TRANSFER DEVICE FOR IMAGE SENSORS - Embodiments of an image sensor pixel that includes a photosensitive element, a floating diffusion region, and a transfer device. The photosensitive element is disposed in a substrate layer for accumulating an image charge in response to light. The floating diffusion region is dispose in the substrate layer to receive the image charge from the photosensitive element. The transfer device is disposed between the photosensitive element and the floating diffusion region to selectively transfer the image charge from the photosensitive element to the floating diffusion region. The transfer device includes a buried channel device including a buried channel gate disposed over a buried channel dopant region. The transfer device also includes a surface channel device including a surface channel gate disposed over a surface channel region. The surface channel device is in series with the buried channel device. The surface channel gate has the opposite polarity of the buried channel gate. | 04-18-2013 |
20130113065 | PAD DESIGN FOR CIRCUIT UNDER PAD IN SEMICONDUCTOR DEVICES - Embodiments of a semiconductor device that includes a semiconductor substrate and a cavity disposed in the semiconductor substrate that extends at least from a first side of the semiconductor substrate to a second side of the semiconductor substrate. The semiconductor device also includes an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity. A conductive layer including a bonding pad is disposed over the insulation layer. The conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate. A through silicon via pad is disposed below the second side of the semiconductor substrate and connected to the metal stack. The through silicon via pad is position to accept a through silicon via. | 05-09-2013 |
20130122637 | SEAL RING SUPPORT FOR BACKSIDE ILLUMINATED IMAGE SENSOR - A backside illuminated imaging sensor with a seal ring support includes an epitaxial layer having an imaging array formed in a front side of the epitaxial layer. A metal stack is coupled to the front side of the epitaxial layer, wherein the metal stack includes a seal ring formed in an edge region of the imaging sensor. An opening is included that extends from the back side of the epitaxial layer to a metal pad of the seal ring to expose the metal pad. The seal ring support is disposed on the metal pad and within the opening to structurally support the seal ring. | 05-16-2013 |
20130200396 | PREVENTION OF LIGHT LEAKAGE IN BACKSIDE ILLUMINATED IMAGING SENSORS - An apparatus includes a semiconductor layer, a dielectric layer, and a light prevention structure. The semiconductor layer has a front surface and a backside surface. The semiconductor layer includes a light sensing element and a periphery circuit region containing a light emitting element and not containing the light sensing element. The dielectric layer contacts at least a portion of the backside surface of the semiconductor layer. At least a portion of the light prevention structure is disposed between the light sensing element and the light emitting element. The light prevention structure is positioned to prevent light emitted by the light emitting element from reaching the light sensing element. | 08-08-2013 |
20130207212 | LATERAL LIGHT SHIELD IN BACKSIDE ILLUMINATED IMAGING SENSORS - A backside illuminated image sensor includes a semiconductor layer and a trench disposed in the semiconductor layer. The semiconductor layer has a frontside surface and a backside surface. The semiconductor layer includes a light sensing element of a pixel array disposed in a sensor array region of the semiconductor layer. The pixel array is positioned to receive external incoming light through the backside surface of the semiconductor layer. The semiconductor layer also includes a light emitting element disposed in a periphery circuit region of the semiconductor layer external to the sensor array region. The trench is disposed in the semiconductor layer between the light sensing element and the light emitting element. The trench is positioned to impede a light path between the light emitting element and the light sensing element when the light path is internal to the semiconductor layer. | 08-15-2013 |
20130217173 | METHODS OF FORMING VARYING DEPTH TRENCHES IN SEMICONDUCTOR DEVICES - A method of forming trenches in a semiconductor device includes forming an etchant barrier layer above a first portion of a semiconductor layer. A first trench is etched in a second portion of the semiconductor layer using a first etchant. The second portion of the semiconductor layer is not disposed underneath the etchant barrier layer. The etchant barrier layer is etched through using a second etchant that does not substantially etch the semiconductor layer. A second trench is etched in the first portion of the semiconductor layer using a third etchant. The third etchant also extends a depth of the first trench. | 08-22-2013 |
20130256822 | METHOD AND DEVICE WITH ENHANCED ION DOPING - Techniques for providing a pixel cell which exhibits improved doping in a semiconductor substrate. In an embodiment, a first doping is performed through a backside of the semiconductor substrate. After the first doping, the semiconductor substrate is thinned to expose a front side which is opposite of the backside. In another embodiment, a second doping is performed through the exposed front side of the thinned semiconductor substrate to form at least part of a pixel cell structure. | 10-03-2013 |
20130258144 | SYSTEM, APPARATUS AND METHOD FOR DARK CURRENT CORRECTION - Embodiments of the invention describe a system, apparatus and method for obtaining black reference pixels for dark current correction processing are described herein. Embodiments of the invention capture image signal data via a plurality of pixel cells of a pixel unit of an image device, wherein capturing image signal data involves establishing a first state of exposing incident light on each pixel of the pixel unit and a second state of shielding incident light from one or more pixels of the pixel unit via a shutter unit disposed over the pixel unit. Image signal data from each pixel of the pixel unit captured during the first state and the second state is read, and scene image data is created by combining a subset of image signal data captured during the first state with a dark current component including a subset of image signal data captured during the second state. | 10-03-2013 |
20130264688 | METHOD AND APPARATUS PROVIDING INTEGRATED CIRCUIT SYSTEM WITH INTERCONNECTED STACKED DEVICE WAFERS - An integrated circuit system includes a first device wafer that has a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer that has a second semiconductor layer proximate to a second metal layer including a second conductor disposed within a second metal layer oxide is also included. A frontside of the first metal layer oxide is bonded to a frontside of the second metal layer oxide at an oxide bonding interface between the first metal layer oxide and the second metal layer oxide. A conductive path couples the first conductor to the second conductor with conductive material formed in a cavity etched between the first conductor and the second conductor and etched through the oxide bonding interface and through the second semiconductor layer from a backside of the second device wafer. | 10-10-2013 |
20130285183 | DUAL-FACING CAMERA ASSEMBLY - Embodiments of the invention relate to a camera assembly including a rear-facing camera and a front-facing camera operatively coupled together (e.g., bonded, stacked on a common substrate). | 10-31-2013 |
20130292751 | IMAGE SENSOR WITH SEGMENTED ETCH STOP LAYER - An apparatus includes a semiconductor layer having an array of pixels arranged therein. A passivation layer is disposed proximate to the semiconductor layer over the array of pixels. A segmented etch stop layer including a plurality of etch stop layer segments is disposed proximate to the passivation layer over the array of pixels. Boundaries between each one of the plurality of etch stop layer segments are aligned with boundaries between pixels in the array of pixels. | 11-07-2013 |
20140014813 | INTEGRATED CIRCUIT STACK WITH INTEGRATED ELECTROMAGNETIC INTERFERENCE SHIELDING - An integrated circuit system includes a first device wafer having a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer having a second semiconductor layer proximate to a second metal layer including a second conductor is disposed within a second metal layer oxide. A frontside of the first device wafer is bonded to a frontside of the second device wafer at a bonding interface. A conductive path couples the first conductor to the second conductor through the bonding interface. A first metal EMI shield is disposed in one of the first metal oxide layer and second metal layer oxide layer. The first EMI shield is included in a metal layer of said one of the first metal oxide layer and the second metal layer oxide layer nearest to the bonding interface. | 01-16-2014 |
20140048897 | PIXEL WITH NEGATIVELY-CHARGED SHALLOW TRENCH ISOLATION (STI) LINER - Embodiments of a pixel including a substrate having a front surface and a photosensitive region formed in or near the front surface of the substrate. An isolation trench is formed in the front surface of the substrate adjacent to the photosensitive region. The isolation trench includes a trench having a bottom and sidewalls, a passivation layer formed on the bottom and the sidewalls, and a filler to fill the portion of the trench not filled by the passivation layer. | 02-20-2014 |
20140084135 | Backside-Illuminated Photosensor Array With White, Yellow ad Red-Sensitive Elements - A monolithic backside-sensor-illumination (BSI) image sensor has a sensor array is tiled with a multiple-pixel cells having a first pixel sensor primarily sensitive to red light, a second pixel sensor primarily sensitive to red and green light, and a third pixel sensor having panchromatic sensitivity, the pixel sensors laterally adjacent each other. The image sensor determines a red, a green, and a blue signal comprising by reading the red-sensitive pixel sensor of each multiple-pixel cell to determine the red signal, reading the sensor primarily sensitive to red and green light to determine a yellow signal and subtracting the red signal to determine a green signal. The image sensor reads the panchromatic-sensitive pixel sensor to determine a white signal and subtracts the yellow signal to provide the blue signal. | 03-27-2014 |
20140103189 | Compact In-Pixel High Dynamic Range Imaging - Embodiments of the invention describe providing a compact solution to provide high dynamic range imaging (HDRI or simply HDR) for an imaging pixel by utilizing a control node for resetting a floating diffusion node to a reference voltage value and for selectively transferring an image charge from a photosensitive element to a readout node. Embodiments of the invention further describe control node to have to a plurality of different capacitance regions to selectively increase the overall capacitance of the floating diffusion node. This variable capacitance of the floating diffusion node increases the dynamic range of the imaging pixel, thereby providing HDR for the host imaging system, as well as increasing the signal-to-noise ratio (SNR) of the imaging system. | 04-17-2014 |
20140103410 | PARTIAL BURIED CHANNEL TRANSFER DEVICE IN IMAGE SENSORS - An image sensor pixel includes a photosensitive element, a floating diffusion (“FD”) region, and a transfer device. The photosensitive element is disposed in a substrate layer for accumulating an image charge in response to light. The FD region is dispose in the substrate layer to receive the image charge from the photosensitive element. The transfer device is disposed between the photosensitive element and the FD region to selectively transfer the image charge from the photosensitive element to the FD region. The transfer device includes a gate, a buried channel dopant region and a surface channel region. The gate is disposed between the photosensitive element and the FD region. The buried channel dopant region is disposed adjacent to the FD region and underneath the gate. The surface channel region is disposed between the buried channel dopant region and the photosensitive element and disposed underneath the gate. | 04-17-2014 |
20140124889 | DIE SEAL RING FOR INTEGRATED CIRCUIT SYSTEM WITH STACKED DEVICE WAFERS - An integrated circuit system includes a first device wafer bonded to a second device wafer at a bonding interface of dielectrics. Each wafer includes a plurality of dies, where each die includes a device, a metal stack, and a seal ring that is formed at an edge region of the die. Seal rings included in dies of the second device wafer each include a first conductive path provided with metal formed in a first opening that extends from a backside of the second device wafer, through the second device wafer, and through the bonding interface to the seal ring of a corresponding die in the first device wafer. | 05-08-2014 |
20140210028 | COLOR FILTER INCLUDING CLEAR PIXEL AND HARD MASK - Embodiments of an apparatus including a color filter arrangement formed on a substrate having a pixel array formed therein. The color filter arrangement includes a clear filter having a first clear hard mask layer and a second clear hard mask layer formed thereon, a first color filter having the first clear hard mask layer and the second hard mask layer formed thereon, a second color filter having the first clear hard mask layer formed thereon, and a third color filter having no clear hard mask layer formed thereon. Other embodiments are disclosed and claimed. | 07-31-2014 |
20140231622 | CIRCUIT STRUCTURE FOR PROVIDING CONVERSION GAIN OF A PIXEL ARRAY - Techniques and mechanisms for a pixel array to provide a level of conversion gain. In an embodiment, the pixel array includes conversion gain control circuitry to be selectively configured at different times for different operational modes, each mode for implementing a respective conversion gain. The conversion gain control circuitry selectively provides switched coupling of the pixel cell to—and/or switched decoupling of the pixel cell from—a supply voltage. In another embodiment, the conversion gain control circuitry selectively provides switched coupling of the pixel cell to—and/or switched decoupling of the pixel cell from—sample and hold circuitry. | 08-21-2014 |
20140239152 | IMAGE SENSOR WITH PIXEL UNITS HAVING MIRRORED TRANSISTOR LAYOUT - An image sensor includes a first pixel unit horizontally adjacent to a second pixel unit. Each pixel unit includes plurality of photodiodes and a shared floating diffusion region. A first pixel transistor region of the first pixel unit has a plurality of pixel transistors. A second pixel transistor region of the second pixel unit is horizontally adjacent to the first pixel transistor region and also has a plurality of pixel transistors. A transistor layout of the second pixel transistor region is a minor image of a transistor layout of the first pixel transistor region. | 08-28-2014 |
20140239154 | HIGH DYNAMIC RANGE PIXEL HAVING A PLURALITY OF AMPLIFIER TRANSISTORS - A pixel cell for use in a high dynamic range image sensor includes a photodiode disposed in semiconductor material to accumulate charge in response to light incident upon the photodiode. A transfer transistor is disposed in the semiconductor material and is coupled between a floating diffusion and the photodiode. A first amplifier transistor is disposed in the semiconductor material having a gate terminal coupled to the floating diffusion and a source terminal coupled to generate a first output signal of the pixel cell. A second amplifier transistor is disposed in the semiconductor material having a gate terminal coupled to the floating diffusion and a source terminal coupled to generate a second output signal of the pixel cell. | 08-28-2014 |
20140239351 | PROCESS TO ELIMINATE LAG IN PIXELS HAVING A PLASMA-DOPED PINNING LAYER - Embodiments of a process including depositing a sacrificial layer on the surface of a substrate over a photosensitive region, over the top surface of a transfer gate, and over at least the sidewall of the transfer gate closest to the photosensitive region, the sacrificial layer having a selected thickness. A layer of photoresist is deposited over the sacrificial layer, which is patterned and etched to expose the surface of the substrate over the photosensitive region and at least part of the transfer gate top surface, leaving a sacrificial spacer on the sidewall of the transfer gate closest to the photosensitive region. The substrate is plasma doped to form a pinning layer between the photosensitive region and the surface of the substrate. The spacing between the pinning layer and the sidewall of the transfer gate substantially corresponds to a thickness of the sacrificial spacer. Other embodiments are disclosed and claimed. | 08-28-2014 |
20140246561 | HIGH DYNAMIC RANGE PIXEL HAVING A PLURALITY OF PHOTODIODES WITH A SINGLE IMPLANT - A high dynamic range image sensor pixel includes a short integration photodiode and a long integration photodiode disposed in semiconductor material. The long integration photodiode has a light exposure area that is substantially larger than a light exposure area of the short integration photodiode. The light exposure area of the short integration photodiode has a first doping concentration from a first doping implantation. The light exposure area of the long integration photodiode includes at least one implanted portion having the first doping concentration from the first doping implantation. The light exposure area of the long integration photodiode further includes at least one non-implanted portion photomasked from the first doping implantation such that a combined doping concentration of the implanted and non-implanted portions of the light exposure area of the long integration photodiode is less than the first doping concentration of the light exposure area of the short integration photodiode. | 09-04-2014 |
20140299956 | LAYERS FOR INCREASING PERFORMANCE IN IMAGE SENSORS - An imaging device includes a semiconductor substrate having a photosensitive element for accumulating charge in response to incident image light. The semiconductor substrate includes a light-receiving surface positioned to receive the image light. The imaging device also includes a negative charge layer and a charge sinking layer. The negative charge layer is disposed proximate to the light-receiving surface of the semiconductor substrate to induce holes in an accumulation zone in the semiconductor substrate along the light-receiving surface. The charge sinking layer is disposed proximate to the negative charge layer and is configured to conserve or increase an amount of negative charge in the negative charge layer. The negative charge layer is disposed between the semiconductor substrate and the charge sinking layer. | 10-09-2014 |
20140299957 | IMAGE SENSOR HAVING METAL CONTACT COUPLED THROUGH A CONTACT ETCH STOP LAYER WITH AN ISOLATION REGION - An image sensor pixel includes one or more photodiodes disposed in a semiconductor layer. Pixel circuitry is disposed in the semiconductor layer coupled to the one or more photodiodes. A passivation layer is disposed proximate to the semiconductor layer over the pixel circuitry and the one or more photodiodes. A contact etch stop layer is disposed over the passivation layer. One or more metal contacts are coupled to the pixel circuitry through the contact etch stop layer. One or more isolation regions are defined in the contact etch stop layer that isolate contact etch stop layer material through which the one or more metal contacts are coupled are coupled to the pixel circuitry from the one or more photodiodes. | 10-09-2014 |
20140306360 | METHOD OF FORMING DUAL SIZE MICROLENSES FOR IMAGE SENSORS - A method of forming microlenses for an image sensor having at least one large-area pixel and at least one small-area pixel is disclosed. The method includes forming a uniform layer of microlens material on a light incident side of the image sensor over the large-area pixel and over the small-area pixel. The method also includes forming the layer of microlens material into a first block disposed over the large-area pixel and into a second block disposed over the small-area pixel. A void is also formed in the second block to reduce a volume of microlens material included in the second block. The first and second blocks are then reflowed to form a respective first microlens and second microlens. The first microlens has substantially the same effective focal length as the second microlens. | 10-16-2014 |
20140346572 | IMAGE SENSOR PIXEL CELL WITH GLOBAL SHUTTER HAVING NARROW SPACING BETWEEN GATES - A pixel cell includes a photodiode, a storage transistor, a transfer transistor and an output transistor disposed in a semiconductor substrate. The transfer transistor selectively transfers image charge accumulated in the photodiode from the photodiode to the storage transistor. The output transistor selectively transfers the image charge from the storage transistor to a readout node. A first isolation fence is disposed over the semiconductor substrate separating a transfer gate of the transfer transistor from a storage gate of the storage transistor. A second isolation fence is disposed over the semiconductor substrate separating the storage gate from an output gate of the output transistor. Thicknesses of the first and second isolation fences are substantially equal to spacing distances between the transfer gate and the storage gate, and between the storage gate and the output gate, respectively. | 11-27-2014 |
20150048427 | IMAGE SENSOR PIXEL CELL WITH SWITCHED DEEP TRENCH ISOLATION STRUCTURE - A pixel cell includes a photodiode disposed in an epitaxial layer in a first region of semiconductor material. A floating diffusion is disposed in a well region disposed in the epitaxial layer in the first region. A transfer transistor is disposed in the first region and coupled between the photodiode and the floating diffusion to selectively transfer image charge from the photodiode to the floating diffusion. A deep trench isolation (DTI) structure lined with a dielectric layer inside the DTI structure is disposed in the semiconductor material isolates the first region on one side of the DTI structure from a second region of the semiconductor material on an other side of the DTI structure. Doped semiconductor material inside the DTI structure is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion. | 02-19-2015 |
20150054106 | DUAL-FACING CAMERA ASSEMBLY - Embodiments of the invention relate to a camera assembly including a rear-facing camera and a front-facing camera operatively coupled together (e.g., bonded, stacked on a common substrate). | 02-26-2015 |