Patent application number | Description | Published |
20090256264 | SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING THE SAME - A semiconductor device is provided. An amorphous silicon layer that acts as a UV blocking layer replaces a conventional silicon-rich oxide (SRO) layer or the super silicon-rich oxide (SSRO) layer. By doing this, the process window is increased. In addition, silicon nitride sidewall spacer is formed inside the contact hole to prevent charge loss. | 10-15-2009 |
20110260230 | CELL WITH SURROUNDING WORD LINE STRUCTURES AND MANUFACTURING METHOD THEREOF - A memory cell with surrounding word line structures includes an active area; a plurality of first trenches formed on the active area in a first direction, each first trench has a bit line on a sidewall therein; a plurality of second trenches formed on the active area in a second direction, each second trench has two word lines formed correspondingly on the sidewalls in the second trench; and a plurality of transistors formed on the active area. The word line pairs are arranged into a surrounding word line structure. The transistor is controlled by the bit line and the two word lines, thus improving the speed of the transistor. | 10-27-2011 |
20120012907 | Memory layout structure and memory structure - A memory layout structure is disclosed, in which, a lengthwise direction of each active area and each row of active areas form an included angle not equal to zero and not equal to 90 degrees, bit lines and word lines cross over each other above the active areas, the bit lines are each disposed above a row of active areas, bit line contact plugs or node contact plugs may be each disposed entirely on an source/drain region, or partially on the source/drain region and partially extend downward along a sidewall (edge wall) of the substrate of the active area to carry out a sidewall contact. Self-aligned node contact plugs are each disposed between two adjacent bit lines and between two adjacent word lines. | 01-19-2012 |
20120256230 | POWER DEVICE WITH TRENCHED GATE STRUCTURE AND METHOD OF FABRICATING THE SAME - A power device with trenched gate structure, includes: a substrate having a first face and a second face opposing to the first face, a body region of a first conductivity type disposed in the substrate, a base region of a second conductivity type disposed in the body region, a cathode region of the first conductivity type disposed in the base region, an anode region of the second conductivity type disposed in the substrate at the second face a trench disposed in the substrate and extending from the first face into the body region, and the cathode region encompassing the trench, wherein the trench has a wavelike sidewall, a gate structure disposed in the trench and an accumulation region disposed in the body region and along the wavelike sidewall. The wavelike sidewall can increase the base current of the bipolar transistor and increase the performance of the IGBT. | 10-11-2012 |
20120256255 | RECESSED TRENCH GATE STRUCTURE AND METHOD OF FABRICATING THE SAME - A recessed trench gate structure is provided. The recessed trench gate structure includes a substrate with a recessed trench, a gate dielectric layer disposed around an inner surface of the recessed trench, a lower gate conductor disposed at a lower portion of the recessed trench and on the gate dielectric layer. Specially, the lower gate conductor has a convex top surface. A spacer is disposed along an inner side wall of a upper portion of the recessed trench and a upper gate conductor is disposed on the lower gate conductor. The convex top surface can prevent the electric field from distributing not uniformly, so that the GIDL can be prevented. | 10-11-2012 |
20120256256 | RECESSED GATE TRANSISTOR WITH CYLINDRICAL FINS - A recessed gate transistor with cylindrical fins is disclosed. The recessed gate transistor is disposed in an active region of a semiconductor substrate. Two isolation regions disposed in the semiconductor substrate to define an active region therebetween. The recessed gate transistor includes a gate structure, a source doping region and a drain doping region. The gate structure has at least three fins forms a concave and convex bottom of the gate structure. The front fin is disposed in one of the two isolation regions, the middle fin is disposed in the active region and a last fin disposed in the other one of the two isolation regions. The front fin and the last fin are both cylindrical. A lower part of the gate structure is M-shaped when view from the source doping region to the drain doping region direction. | 10-11-2012 |
20120256257 | TRANSISTOR WITH BURIED FINS - The present invention disclosed a recessed gate transistor with buried fins. The recessed gate transistor with buried fins is disposed in an active region on a semiconductor substrate. Two isolation regions disposed in the semiconductor substrate, and sandwich the active region. A gate structure is disposed in the semiconductor substrate, wherein the gate structure includes: an upper part and a lower part. The upper part is disposed in the active region and a lower part having a front fin disposed in one of the two isolation regions, at least one middle fin disposed in the active region, and a last fin disposed in the other one of the two isolation regions, wherein the front fin are both elliptic cylindrical. | 10-11-2012 |
20120256279 | METHOD OF GATE WORK FUNCTION ADJUSTMENT AND METAL GATE TRANSISTOR - A method of gate work function adjustment includes the steps as follow. First, a substrate is provided, wherein a metal gate is disposed on the substrate, a source doping region and a drain doping region are disposed in the substrate at opposite sites of the metal gate, wherein the metal gate is divided into a source side adjacent to the source doping region, and a drain side adjacent to the drain doping region. Later, a mask layer is formed to cover the source doping region and the drain doping region. After that, an implantation process is performed to implant nitrogen into the metal gate so as to make a first nitrogen concentration of the source side higher than a second nitrogen concentration of the drain side. Finally, the mask layer is removed. | 10-11-2012 |
20120264299 | CHEMICAL MECHANICAL POLISHING METHOD - A chemical mechanical polishing (CMP) method is provided The method is capable of polishing a substrate in a CMP apparatus by using a hydrophobic polishing pad and includes following steps. A first CMP process is performed to the substrate. A first cleaning process is performed to the hydrophobic polishing pad. A second CMP process is performed to the substrate, wherein the first CMP process, the first cleaning process and the second CMP process are performed in sequence. | 10-18-2012 |
20120264300 | METHOD OF FABRICATING SEMICONDUCTOR COMPONENT - A method of fabricating the semiconductor component including following steps is provided. A substrate is provided, wherein an opening is already formed in the substrate. A material layer is formed on the substrate, wherein the material layer fills up the opening, and the material layer outside and above the opening has a recess therein. A sacrifice layer is formed on a surface of the recess. A chemical mechanical polishing (CMP) process is performed to remove the sacrifice layer and the material layer outside the opening, wherein a polishing rate of the CMP process on the material layer is greater than that of the CMP process on the sacrifice layer. | 10-18-2012 |
20120264354 | DISTANCE MONITORING DEVICE - A distance monitoring device is provided. The device is suitable for a chemical mechanical polishing (CMP) apparatus. A polishing head of the CMP apparatus includes a frame and a membrane. The membrane is mounted on the frame, and a plurality of air bags is formed by the membrane and the frame in the polishing head. The distance monitoring device includes a plurality of distance detectors disposed on the frame corresponding to the air bags respectively to set a location of each of the distance detectors on the frame as a reference point, wherein each of the distance detectors is configured to measure a distance between each of the reference points and the membrane. | 10-18-2012 |
20120264359 | MEMBRANE - A membrane is suitable to be mounted on a polishing head of a chemical mechanical polishing apparatus and includes a main portion and an edge portion. The edge portion is located at an edge of the main portion, wherein a first included angle between the main portion and the edge portion is an obtuse angle. | 10-18-2012 |
20120267727 | METHOD FOR FORMING SELF-ALIGNED CONTACT - An integrated circuit with a self-aligned contact includes a substrate with a transistor formed thereover, a dielectric spacer, a protection barrier, and a conductive layer. The transistor includes a mask layer and a pair of insulating spacers formed on opposite sides of the mask layer. The dielectric spacer partially covers at least one of the insulating spacers of the transistor. The protection barrier is formed over the dielectric spacer. The conductive layer is formed over the mask layer, the protection barrier, the dielectric spacer, the insulating spacer and the dielectric spacer as a self-aligned contact for contacting a source/drain region of the transistor. | 10-25-2012 |
20120267760 | CAPACITOR AND MANUFACTURING METHOD THEREOF - A capacitor and a manufacturing method thereof are provided. The capacitor includes a first electrode, a first metal layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate. The first metal layer is disposed on the first electrode. The dielectric layer is disposed on the first metal layer, wherein the material of the first metal layer does not react with the material of the dielectric layer. The second electrode is disposed on the dielectric layer. | 10-25-2012 |
20120270408 | MANUFACTURING METHOD OF GATE DIELECTRIC LAYER - A manufacturing method of a gate dielectric layer that includes a nitride layer and an oxide layer is provided. A substrate is provided. A nitridation treatment is performed to form the nitride layer on the substrate. An oxidation treatment is performed subsequent to the formation of the nitride layer to form the oxide layer between the nitride layer and the substrate. | 10-25-2012 |
20120270411 | MANUFACTURING METHOD OF GATE DIELECTRIC LAYER - A manufacturing method of a gate dielectric layer is provided. An oxidation treatment is performed to form an oxide layer on a substrate. A nitridation treatment is performed to form a nitride layer on the oxide layer. An annealing treatment is performed in a mixing gas of N | 10-25-2012 |
20120270474 | POLISHING PAD WEAR DETECTING APPARATUS - A polishing pad wear detecting apparatus suitable for a chemical mechanical polishing (CMP) apparatus is provided. The polishing pad wear detecting apparatus includes an arm and a height detector. One end of the arm is fastened on the CMP apparatus. The height detector is disposed on the arm for detecting height variation of a polishing pad. | 10-25-2012 |
20120273874 | MEMORY DEVICE HAVING BURIED BIT LINE AND VERTICAL TRANSISTOR AND FABRICATION METHOD THEREOF - A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line. | 11-01-2012 |
20120276707 | METHOD FOR FORMING TRENCH ISOLATION - A method for forming a trench isolation is disclosed, comprising, providing a substrate comprising a trench, forming a polysilicon layer in the trench, and subjecting the substrate to a treating process to convert the polysilicon layer to an isolating layer, wherein the treating process is fine tuned for the isolating layer on opposite sidewalls of the trench to expand to contact with each other so that the isolating layer fills the trench. | 11-01-2012 |
20120276714 | METHOD OF OXIDIZING POLYSILAZANE - A method of oxidizing polysilazane is disclosed, comprising providing a substrate, comprising a trench, forming a polysilazane layer in the trench, and treating the polysilazane layer in an acid containing solution applied with mega-sonic waves to oxidize the polysilazane layer, wherein the acid containing solution comprises phosphoric acid, sulfuric acid, H | 11-01-2012 |
20120282777 | METHOD FOR INCREASING ADHESION BETWEEN POLYSILAZANE AND SILICON NITRIDE - A method for increasing adhesion between polysilazane and silicon nitride is disclosed, comprising, providing a substrate comprising a trench, forming a silicon nitride liner layer on a bottom surface and a sidewall of the trench, performing a treating process to the silicon nitride liner layer for producing a hydrophilic surface with OH groups that can increase adhesion between the silicon nitride liner layer and a subsequently formed polysilazane coating layer, and forming a polysilazane coating layer into the trench and on the silicon nitride liner layer. | 11-08-2012 |
20120284936 | POST-CMP WAFER CLEANING APPARATUS - A post-CMP wafer cleaning apparatus includes a chamber; a plurality of rollers adapted to hold and rotate a wafer within the chamber; at least one brush adapted to scrub a surface of the wafer to be cleaned; and a liquid spraying device adapted to spray a liquid on the wafer, the liquid spraying device comprising two spray bars jointed together via a joint member. | 11-15-2012 |
20120285483 | METHOD OF CLEANING A WAFER - A method of cleaning a wafer is disclosed in the present invention. This method is particularly suitable for cleaning the metal layer on the wafer. First, a wafer having a metal layer is loaded into a cleaning chamber, wherein a plurality of particles are inlaid in a surface of the metal layer. Later, a first clean stage is performed to rinse the wafer by jetted liquid introduced with megasonic energy. After the first clean stage, a second clean stage is performed to scrub the wafer. Finally, the wafer is dried. | 11-15-2012 |
20120285484 | METHOD FOR CLEANING A SEMICONDUCTOR WAFER - A wafer cleaning method includes: (1) providing a wafer cleaning apparatus comprising a sponge for scrubbing a surface of a semiconductor wafer to be cleaned; (2) implementing a pre-conditioning flow to pre-condition the sponge using a dummy wafer; and (3) performing a regular cleaning flow to scrub the surface of the semiconductor wafer to be cleaned using the pre-conditioned sponge. The dummy wafer has a plurality of upward protruding features on a surface of the dummy wafer for removing residual fibers or unwanted substances from the sponge. | 11-15-2012 |
20120286352 | TRENCH MOS STRUCTURE AND METHOD FOR MAKING THE SAME - A trench MOS structure is provided. The trench MOS structure includes a substrate, an epitaxial layer, a trench, a gate isolation, a trench gate, a guard ring and a reinforcement structure within the guard ring. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The trench is disposed in the epitaxial layer. The gate isolation covers the inner wall of the trench. The trench gate is disposed in the trench and has the first conductivity type. The guard ring has a second conductivity type and is disposed within the epitaxial layer. The reinforcement structure has an electrically insulating material and is disposed within the guard ring. | 11-15-2012 |
20120286353 | TRENCH MOS STRUCTURE AND METHOD FOR FORMING THE SAME - A trench MOS structure is disclosed. The trench MOS structure includes a substrate, an epitaxial layer, a doping well, a doping region and a trench gate. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. The trench gate is partially disposed in the doping region. The trench gate has a bottle shaped profile with a top section smaller than a bottom section, both are partially disposed in the doping well. The bottom section of two adjacent trench gates results in a higher electrical field around the trench MOS structures. | 11-15-2012 |
20120286402 | PROTUBERANT STRUCTURE AND METHOD FOR MAKING THE SAME - A cuboidal protuberant structure is provided. The cuboidal protuberant structure includes a substrate and a protrusion disposed on the substrate. The protrusion has a vertical side wall with a rounded corner, a protuberant width and a protuberant length. At least one of the protuberant width and the protuberant length is not greater than 33 nm. | 11-15-2012 |
20120286819 | MOS TEST STRUCTURE, METHOD FOR FORMING MOS TEST STRUCTURE AND METHOD FOR PERFORMING WAFER ACCEPTANCE TEST - A MOS test structure is disclosed. A scribe line region is disposed on a substrate which has a first side and a second side opposite to the first side. An epitaxial layer is disposed on the first side, the doping well is disposed on the epitaxial layer and the doping region is disposed on the doping well. A trench gate of a first depth is disposed in the doping region, in the doping well and in the scribe line region. A conductive material fills the test via which has a second depth and an isolation covering the inner wall of the test via and is disposed in the doping region, in the doping well, in the epitaxial layer and in the scribe line region, to electrically connect to the epitaxial layer so that the test via is capable of testing the epitaxial layer and the substrate together. | 11-15-2012 |
20120287500 | OPTICAL LENS AND OPTICAL MICROSCOPE SYSTEM USING THE SAME - An optical lens is provided in the present invention. The optical lens includes a first curved surface and an annular mask component on and in direct contact with the first curved surface, wherein the annular mask component shields a peripheral annular region of the optical lens from entry of light. The present invention further provides an optical microscope system using the same. | 11-15-2012 |
20120288355 | Method for storing wafers - A method for storing wafers is disclosed. A plurality of wafers are placed into the wafer cassette box. The wafer cassette box is hermetically sealed and pumped down to vacuum for the wafer storage. Alternatively, the wafers carried by a holder conveyed on a wafer conveyor are placed into a pump-down chamber enclosing a section of the wafer conveyor. The pump-down chamber is hermetic sealed and pumped down to vacuum for the wafer storage on the wafer conveyor. | 11-15-2012 |
20120288683 | PROTUBERANT STRUCTURE AND METHOD FOR MAKING THE SAME - The protuberant structure of the present invention includes a substrate and a protrusion disposed on the substrate. The protrusion has a top side, a bottom side and a tapered side wall disposed between the top side and the bottom side. The top side has an extremely small top width which is not greater than 32 nm. | 11-15-2012 |
20120288684 | BUMP STRUCTURE AND FABRICATION METHOD THEREOF - A bump structure including a base portion, an inlaid wire segment, and a protruding tail segment is provided. The base portion is bonded on a bonding site. The inlaid wire segment is pressed into a top surface of the base portion. The protruding tail segment extends from the inlaid wire segment. The methods for forming the bump structure are also provided. | 11-15-2012 |
20120288802 | METHOD OF FORMING GATE CONDUCTOR STRUCTURES - A method of forming gate conductor structures. A substrate having thereon a gate electrode layer is provided. A multi-layer hard mask is formed overlying the gate electrode layer. The multi-layer hard mask comprises a first hard mask, a second hard mask, and a third hard mask. A photoresist pattern is formed on the multi-layer hard mask. A first etching process is performed to etch the third hard mask, using the photoresist pattern as a first etch resist, thereby forming a patterned third hard mask. A second etching process is performed to etch the second hard mask and the first hard mask, using the patterned third hard mask as a second etch resist, thereby forming a patterned first hard mask. A third etching process is performed to etch a layer of the gate electrode layer, using the patterned first hard mask as a third etch resist. | 11-15-2012 |
20120288966 | METHOD FOR DECAPSULATING INTEGRATED CIRCUIT PACKAGE - A method for decapsulating an integrated circuit package in the absence of a mask is disclosed. First, a package is provided. The package includes at least a circuit element and a molding compound enclosing the circuit. Second, a caustic solution is simultaneously provided and drained. The caustic solution is capable of etching the molding compound while in continuous contact with the molding compound to etch the molding compound. As a consequence, the molding compound is removed so that the circuit element in the package is substantially exposed. | 11-15-2012 |
20120288967 | METHOD FOR PROCESSING CIRCUIT IN PACKAGE - A method for decapsulating an integrated circuit package without the need of using a mask during the decapsulation process is disclosed. First, a package is provided. The package includes at least a circuit element and a molding compound enclosing the circuit. Second, a caustic solution is simultaneously provided. The caustic solution is capable of etching the molding compound and intermittently contacts a pre-selected area of the molding compound to etch the molding compound. As a consequence, the caustic solution removes the molding compound in the pre-selected area so the circuit element in the package is substantially exposed. | 11-15-2012 |
20120288968 | Method for repairing a semiconductor structure having a current-leakage issue - A method for repairing a semiconductor structure having a current-leakage issue includes finding a semiconductor structure having a current-leakage issue through application of a test voltage from an electric test device and applying an electric power stress to the semiconductor structure to melt a stringer or a bridge between two conductive elements or to allow the stringer or the bridge to be oxidized. | 11-15-2012 |
20120289048 | Method for obtaining a layout design for an existing integrated circuit - A method for obtaining a layout design for an existing integrated circuit, in which, an integrated circuit die is polished with a tilt angle to form an inclined polished surface and one or more images of the inclined polished surface are obtained. The images may be overlapped directly, or the image or the images may be utilized to provide information to obtain a layout design comprising at least one repeating unit structure of the layout structure. | 11-15-2012 |
20120289050 | METHOD OF ETCHING TRENCHES IN A SEMICONDUCTOR SUBSTRATE UTILIZING PULSED AND FLUOROCARBON-FREE PLASMA - A method of etching trenches in a semiconductor substrate. A patterned hard mask is formed over a semiconductor substrate. Using the patterned hard mask as an etching mask, a plasma etching process is then carried out to etch trenches into the semiconductor substrate not covered by the patterned hard mask, wherein the plasma etching process employs a fluorocarbon-free plasma etching chemistry and is performed under a plasma pulse output mode. | 11-15-2012 |
20120289128 | CHEMICAL MECHANICAL POLISHING SYSTEM - A chemical mechanical polishing (CMP) system includes a wafer polishing unit comprising a waste liquid sink for receiving a used slurry and a waste slurry drain piping for draining the used slurry; and a post-CMP cleaning unit coupled to the wafer polishing unit such that a used base chemical such as tetramethyl ammonium hydroxide (TMAH) produced from the post-CMP cleaning unit flows toward the wafer polishing unit to frequently wash at least the waste slurry drain piping in a real time fashion on a wafer by wafer basis. | 11-15-2012 |
20120289131 | CMP APPARATUS AND METHOD - A CMP apparatus includes an enclosure; a platen disposed within the enclosure, and a carrier for holding and rotating a wafer. The platen consists of a central, circular-shaped segment and a peripheral, annular-shaped segment with a gap formed therebetween. A first polishing pad is mounted on the central, circular-shaped segment. A second polishing pad is mounted on the peripheral, annular-shaped segment. In polishing, the carrier rotates between the first and second polishing pads, such that an annular edge region of the wafer is in direct contact with the second polishing pad. | 11-15-2012 |
20120289133 | CHEMICAL MECHANICAL POLISHING SYSTEM - A chemical mechanical polishing (CMP) system includes a wafer polishing unit producing a used slurry; a slurry treatment system for receiving and treating the used slurry to thereby produce an extracted basic solution; and a post-CMP cleaning unit utilizing the extracted basic solution to wash a polished wafer surface. The post-CMP cleaning unit includes a plurality of rollers for supporting and rotating a wafer, a brush for scrubbing the wafer, and a spray bar disposed in proximity to the brush for spraying the extracted basic solution onto the polished wafer surface. | 11-15-2012 |
20120289134 | CMP SLURRY MIX AND DELIVERY SYSTEM - A CMP slurry mix and delivery system includes at least one container for holding a polishing agent; a pump connected to the container for pumping the polishing agent to a point of use; and a slurry dispersion unit installed between the pump and the point of use, wherein slurry dispersion unit provides megasonic energy that is capable of dispersing the polishing agent flowing through the slurry dispersion unit. | 11-15-2012 |
20120293196 | TEST KEY STRUCTURE FOR MONITORING GATE CONDUCTOR TO DEEP TRENCH MISALIGNMENT AND TESTING METHOD THEREOF - The disclosure provides a test key structure for monitoring gate conductor to deep trench misalignment and a testing method thereof. The test key structure for monitoring gate conductor to deep trench misalignment includes: a deep trench capacitor structure comprising a plurality of parallel deep trench capacitor lines and a deep trench capacitor connect; a buried strap out-diffusion adjacent to a first side of the deep trench capacitor line; a first gate conductor structure comprising a plurality of parallel first gate conductor lines and a first gate conductor connect, wherein each first gate conductor line is disposed directly over the corresponding deep trench capacitor line; and a second gate conductor structure comprising a plurality of parallel second gate conductor lines and a second gate conductor connect, wherein the first gate conductor lines are electrically connected to each other via the second gate conductor connect, and wherein the first gate conductor lines and the second gate conductor lines are parallel to each other, and the first gate conductor lines and the second gate conductor lines are arranged alternately. | 11-22-2012 |
20120295408 | METHOD FOR MANUFACTURING MEMORY DEVICE - The method for manufacturing a memory device is provided. The method includes: implanting a first impurity into the substrate adjacent to the gate conductor structure to form a source region on a first side of the gate conductor structure and a drain region on a second side of the gate conductor structure; implanting a second impurity into the substrate to form a halo implantation region disposed adjacent to the source region, wherein the halo implantation region has a doping concentration which does not degrade a data retention time of the memory device; and performing an annealing process to the drain region, forming a diffusion region under the drain region, wherein the process temperature of the annealing process is controlled to ensure that the diffusion region has a doping concentration substantially equal to a threshold concentration which maintains an electrical connection between the drain and the deep trench capacitor. | 11-22-2012 |
20120298992 | TEST LAYOUT STRUCTURE - A test layout structure includes a substrate, a first oxide region of a first height, a second oxide region of a second height, a plurality of border regions, and a test layout pattern. The first oxide region is disposed on the substrate. The second oxide region is also disposed on the substrate and adjacent to the first oxide region. The first height is substantially different from the second height. A plurality of border regions are disposed between the first oxide region and the second oxide region. The test layout pattern includes a plurality of individual sections. A test region is disposed between two of the adjacent individual sections which are parallel to each other. | 11-29-2012 |
20120299185 | Slit Recess Channel Gate and Method of Forming the Same - A slit recess channel gate is further provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer. The present invention also provides a method of forming the slit recess channel gate. | 11-29-2012 |
20120301833 | METHOD OF REDUCING MICROLOADING EFFECT - The present invention provides a method of reducing microloading effect by using a photoresist layer as a buffer. The method includes: providing a substrate defined with a dense region and an isolated region. Then, a dense feature pattern and an isolated feature pattern are formed on the dense region and the isolated region respectively. After that, a photoresist layer is formed to cover the isolated region. Finally, the substrate and the photoresist layer are etched by taking the dense feature pattern and the isolated feature pattern as a mask. | 11-29-2012 |
20120302030 | METHOD OF FABRICATING A DEEP TRENCH DEVICE - A method of fabricating a deep trench capacitor includes the steps as follows. Firstly, a substrate having a trench therein is provided. Then, a bottom electrode is formed in the substrate around the trench. Later, a capacitor dielectric layer is formed to surround an inner sidewall of the trench. After that, a first conductive layer is form to fill up the trench. Subsequently, a material layer is formed on the substrate. Later, a hole is formed in the material layer, wherein the hole is directly above the trench. Finally, a second conductive layer is form to fill in the hole. | 11-29-2012 |
20120302049 | METHOD FOR IMPLANTING WAFER - The disclosure provides a method for wafer implantation including the following steps: providing a wafer, wherein the wafer comprises a central circular portion, and a peripheral annular portion adjacent to a edge of the wafer, and wherein the central circular portion and the peripheral annular portion are concentric; and implanting ion beams into the wafer, wherein the central circular portion has a first average implantation dose and the peripheral annular portion has a second average implantation dose, and the first average implantation dose and the second first average implantation dose are different. | 11-29-2012 |
20120302060 | METHOD FOR MANUFACTURING MEMORY DEVICE - The disclosure provides a method for manufacturing a memory device, including: providing a plurality of gate structures formed on a substrate, wherein the gate structures comprise a cap layer disposed on the top of the gate structure, and each two adjacent gate structures are separated by a gap; blanketly forming a polysilicon layer on the substrate to fill the gap; performing a planarization process to the polysilicon layer, obtaining a polysilicon plug; and performing an oxidation process after the planarization process, converting a part of the polysilicon plug and a residual polysilicon layer over the gate structure to silicon oxide. | 11-29-2012 |
20120305525 | METHOD OF REDUCING STRIATION ON A SIDEWALL OF A RECESS - A method of reducing striation on a sidewall of a recess is provided. The method includes the steps of providing a substrate covered with a photoresist layer. Then, the photoresist layer is etched to form a patterned photoresist layer. Later, a repairing process is performed by treating the patterned photoresist layer with a repairing gas which is selected from the group consisting of CF | 12-06-2012 |
20120309155 | SEMICONDUCTOR PROCESS - A semiconductor process is provided. A substrate is provided, gates each including a silicon layer, a silicide layer and a cap layer are formed thereon, and doped regions are formed at two sides of each gate. An insulating layer is formed to cover a memory region and a periphery region. First contact holes are formed in the insulating layer in the memory region, and each first contact hole is disposed between the two adjacent gates and exposes the doped region. A contact plug is formed in each first contact hole to electrically connect the doped region. A patterned mask layer is formed on the substrate to cover the memory region and expose a portion of the periphery region. Using the patterned mask layer as a mask, second and third contact holes are formed in the insulating layer in the periphery region, to expose the silicide layer and the doped region. | 12-06-2012 |
20120309192 | SEMICONDUCTOR PROCESS - A semiconductor process is provided. A mask layer is formed on a substrate and has a first opening exposing a portion of the substrate. Using the mask layer as a mask, a dry etching process is performed on the substrate to form a second opening therein. The second opening has a bottom portion and a side wall extending upwards and outwards from the bottom portion, wherein the bottom portion is exposed by the first opening and the side wall is covered by the mask layer. Using the mask layer as a mask, a vertical ion implantation process is performed on the bottom portion. A conversion process is performed, so as to form converting layers on the side wall and the bottom portion of the second opening, wherein a thickness of the converting layer on the side wall is larger than a thickness of the converting layer on the bottom portion. | 12-06-2012 |
20130017684 | PROCESS OF FORMING SLIT IN SUBSTRATEAANM Wang; Wen-ChiehAACI Taoyuan CountyAACO TWAAGP Wang; Wen-Chieh Taoyuan County TWAANM Chen; Yi-NanAACI Taipei CityAACO TWAAGP Chen; Yi-Nan Taipei City TWAANM Liu; Hsien-WenAACI Taoyuan CountyAACO TWAAGP Liu; Hsien-Wen Taoyuan County TW - A process of forming a slit in a substrate is provided. A mask layer is formed on a substrate, wherein the mask layer does not include carbon. An etching process is performed to be substrate by using the mask layer as a mask, so as to form a slit in the substrate. The etching gas includes Cl | 01-17-2013 |
20130017687 | METHOD FOR FORMING OPENINGS IN SEMICONDUCTOR DEVICEAANM Lin; Chih-ChingAACI Taoyuan CountyAACO TWAAGP Lin; Chih-Ching Taoyuan County TWAANM Chen; Yi-NanAACI Taoyuan CountyAACO TWAAGP Chen; Yi-Nan Taoyuan County TWAANM Liu; Hsien-WenAACI Taoyuan CountyAACO TWAAGP Liu; Hsien-Wen Taoyuan County TW - A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O | 01-17-2013 |
20130043470 | CRACK STOP STRUCTURE AND METHOD FOR FORMING THE SAME - The present invention in a first aspect proposes a semiconductor structure with a crack stop structure. The semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in the form of a grid to form a crack stop structure. | 02-21-2013 |
20130045600 | METHOD FOR FORMING FIN-SHAPED SEMICONDUCTOR STRUCTURE - A method for fabricating a fin-shaped semiconductor structure is provided, including: providing a semiconductor substrate with a semiconductor island and a dielectric layer formed thereover; forming a mask layer over the semiconductor island and the dielectric layer; forming an opening in the mask layer, exposing a top surface of the semiconductor island and portions of the dielectric layer adjacent to the semiconductor island; performing an etching process, simultaneously etching portions of the mask layer, and portions of the semiconductor island and the dielectric layer exposed by the opening; and removing the mask layer and the dielectric layer, leaving an etched semiconductor island with curved top surfaces and various thicknesses over the semiconductor substrate. | 02-21-2013 |
20130052820 | METHOD OF FORMING CONDUCTIVE PATTERN - A method of forming conductive pattern is provided. A seeding layer is formed on an underlayer. By using an energy ray, an irradiation treatment is performed on a portion of a surface of the seeding layer. The seeding layer thus includes a plurality of irradiated regions and a plurality of unirradiated regions. A conversion treatment is performed on the irradiated regions of the seeding layer. A selective growth process is performed, so as to form a conductive pattern on each unirradiated region of the seeding layer. The irradiated regions of the seeding layer are removed, so that the conductive patterns are insulated from each other. | 02-28-2013 |
20130062727 | CRACK STOP STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure. | 03-14-2013 |
20130068264 | WAFER SCRUBBER APPARATUS - A wafer scrubber apparatus is disclosed, including a chamber, and holder connecting to a spindle disposed in the chamber, wherein the holder supports a wafer, and a gas purge pipe disposed at the top of a wall of the chamber, wherein the gas purge pipe comprises a plurality of gas injection holes facing downward to purge gas along the chamber wall making water flow along the chamber wall more smoothly and more quickly for preventing the water from scattering back to the wafer. | 03-21-2013 |
20130069235 | BONDING PAD STRUCTURE FOR SEMICONDUCTOR DEVICES - A bonding pad structure includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers comprising at least a topmost IMD layer; a bondable metal pad layer disposed on a surface of the topmost IMD layer within a pad forming region; a passivation layer covering a periphery of the bondable metal pad layer and the surface of the topmost IMD layer; anda plurality of via plugs disposed in the topmost IMD layer within an annular region of the pad forming region, wherein the via plugs are not formed in a central region of the pad forming region. | 03-21-2013 |
20130071790 | METHOD OF FORMING AN ETCH MASK - A method of forming an etch mask includes: providing a substrate having thereon a material layer to be etched; forming a hard mask layer consisting of a radiation-sensitive, single-layer resist material on the material layer; exposing the hard mask layer to actinic energy to change solvent solubility of exposed regions of the hard mask layer; and subjecting the hard mask layer to water treatment to remove the exposed regions of the hard mask layer, thereby forming a masking pattern consisting of unexposed regions of the hard mask layer. | 03-21-2013 |
20130071978 | FABRICATING METHOD OF TRANSISTOR - A fabricating method of a transistor is provided. A patterned sacrificed layer is formed on a substrate, wherein the patterned sacrificed layer includes a plurality of openings exposing the substrate. By using the patterned sacrificed layer as a mask, a doping process is performed on the substrate, thereby forming a doped source region and a doped drain region in the substrate exposed by the openings. A selective growth process is performed to form a source and a drain on the doped source region and the doped drain region, respectively. The patterned sacrificed layer is removed to expose the substrate between the source and the drain. A gate is formed on the substrate between the source and the drain. | 03-21-2013 |
20130071992 | SEMICONDUCTOR PROCESS - A semiconductor process is provided. An insulating layer is formed on a semiconductor substrate. A portion of the insulating layer is removed, so as to form a plurality of isolation structures and a mesh opening disposed between the isolation structures and exposing the semiconductor substrate. By performing a selective growth process, a semiconductor layer is formed from a surface of the semiconductor substrate exposed by the mesh opening, so that the isolation structures are disposed in the semiconductor layer. | 03-21-2013 |
20130074878 | WAFER SCRUBBER - A wafer scrubber is disclosed, including a chamber, and a holder connecting to a spindle disposed in the chamber, wherein the holder supports a wafer, and the wafer spins to remove water on the wafer, and a mashed inner cup comprising a plurality of through holes disposed between the holder and a wall of the chamber, wherein the mashed inner cup receives water from a surface of the wafer and rotates around the spindle to release the water through the through holes. | 03-28-2013 |
20130078774 | METHOD FOR FORMING DOPE REGIONS WITH RAPID THERMAL PROCESS - The invention provides a method for forming a semiconductor device, including providing a substrate, forming a gate dielectric layer, forming a gate electrode on the gate dielectric layer, forming a spacer on sidewalls of the gate dielectric layer and the gate electrode, and using a rapid thermal process (RTP) apparatus comprising a plurality of lamps and a bias applying system to dope the substrate to form a source/drain region, wherein in the RTP apparatus, gaseous dopant species are illuminated by the lamps to be excited for transference gaseous dopant species to dopant ions and the dopant ions are moved by a bias from the bias applying system to be doped into the substrate. | 03-28-2013 |
20130078804 | METHOD FOR FABRICATING INTEGRATED DEVICES WITH REDUCTED PLASMA DAMAGE - A method for fabricating an integrated device with reduced plasma damage is disclosed, including providing a substrate, forming a structural layer on the substrate, forming a photoresist layer on the structural layer, and performing an etching process to the structural layer, wherein the photoresist layer is conductive to reduce plasma damage during the etching process. | 03-28-2013 |
20130078815 | METHOD FOR FORMING SEMICONDUCTOR STRUCTURE WITH REDUCED LINE EDGE ROUGHNESS - A method for forming a semiconductor structure with reduced line edge roughness is provided, including: providing a device layer with a patterned photoresist layer formed thereon; and performing a plasma etching process to pattern the device layer with the patterned photoresist layer formed thereon, forming a patterned device layer, wherein the plasma etching process is operated under a continuous on-stage voltage provided with a relative higher frequency and an on-off stage voltage with pulsing modulation provided with a relative lower frequency. | 03-28-2013 |
20130099309 | VERTICAL MOSFET ELECTROSTATIC DISCHARGE DEVICE - A vertical MOSFET electrostatic discharge device is disclosed, including a substrate comprising a plurality of trenches, a recessed gate disposed in each trench, a drain region disposed between each of the two neighboring recessed gates, an electrostatic discharge implant region disposed under each drain region, and a source region surrounding and disposed under the recessed gates and the electrostatic discharge implant regions. | 04-25-2013 |
20130102123 | METHOD FOR FABRICATING SINGLE-SIDED BURIED STRAP IN A SEMICONDUCTOR DEVICE - A method for manufacturing a buried-strap includes: forming a trench capacitor structure in a semiconductor substrate, wherein the trench capacitor structure has a doped polysilicon layer and an isolation collar covered by the doped polysilicon layer, and a top surface of the doped polysilicon layer is lower than a top surface of the semiconductor substrate such that a first recess is formed; sequentially forming a first resist layer, a second resist layer and a third resist layer over the semiconductor substrate; sequentially patterning the third resist layer, the second resist layer and the first resist layer, forming a patterned tri-layer resist layer over the semiconductor substrate; partially removing a portion of the doped polysilicon layer exposed by the patterned tri-layer resist layer to form a second recess; removing the patterned tri-layer resist layer; and forming an insulating layer in the second recess and a portion of the first recess. | 04-25-2013 |
20130307067 | Slit Recess Channel Gate - A slit recess channel gate is provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer. | 11-21-2013 |
20140154864 | CRACK STOP STRUCTURE AND METHOD FOR FORMING THE SAME - The present invention in a first aspect proposes a semiconductor structure with a crack stop structure. The semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in the form of a grid to form a crack stop structure. | 06-05-2014 |
20140213027 | MEMORY DEVICE HAVING BURIED BIT LINE AND VERTICAL TRANSISTOR AND FABRICATION METHOD THEREOF - A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line. | 07-31-2014 |
20150064893 | METHOD FOR FORMING TRENCH MOS STRUCTURE - A method for forming a trench MOS structure. First, a substrate, an epitaxial layer, a doping region and a doping well are provided. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. A gate trench penetrates the doping region and the doping well. The doping well is partially removed to form a bottom section of the gate trench. A gate isolation is formed to cover the inner wall of the bottom section and a top section of the gate trench. The gate trench is filled with a conductive material to form a trench gate. | 03-05-2015 |