Patent application number | Description | Published |
20110193221 | 3DIC Architecture with Interposer for Bonding Dies - A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure. | 08-11-2011 |
20110193235 | 3DIC Architecture with Die Inside Interposer - A device is formed to include an interposer having a top surface, and a bump on the top surface of the interposer. An opening extends from the top surface into the interposer. A first die is bonded to the bump. A second die is located in the opening of the interposer and bonded to the first die. | 08-11-2011 |
20110291232 | 3D Inductor and Transformer - In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture. | 12-01-2011 |
20110298551 | INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME - A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV. | 12-08-2011 |
20120061795 | Through-Substrate Via Waveguides - A device includes a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a first surface and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the semiconductor substrate. A well region of a second conductivity type opposite the first conductivity type encircles the TSV, and extends from the first surface to the second surface of the semiconductor substrate. | 03-15-2012 |
20120104578 | Approach for Bonding Dies onto Interposers - A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs. | 05-03-2012 |
20120206160 | TESTING OF SEMICONDUCTOR CHIPS WITH MICROBUMPS - Test structures for performing electrical tests of devices under one or more microbumps are provided. Each test structure includes at least one microbump pad and a test pad. The microbump pad is a part of a metal pad connected to an interconnect for a device. A width of the microbump pad is equal to or less than about 50 μm. The test pad is connected to the at least one microbump pad. The test pad has a size large enough to allow circuit probing of the device. The test pad is another part of the metal pad. A width of the test pad is greater than the at least one microbump pad. | 08-16-2012 |
20120238057 | Approach for Bonding Dies onto Interposers - A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs. | 09-20-2012 |
20120305916 | Interposer Test Structures and Methods - An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads. | 12-06-2012 |
20130009317 | FORMING GROUNDED THROUGH-SILICON VIAS IN A SEMICONDUCTOR SUBSTRATE - A method of forming an interposer includes providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface opposite the front surface; forming one or more through-silicon vias (TSVs) extending from the front surface into the semiconductor substrate; forming an inter-layer dielectric (ILD) layer overlying the front surface of the semiconductor substrate and the one or more TSVs; and forming an interconnect structure in the ILI) layer, the interconnect structure electrically connecting the one or more TSVs to the semiconductor substrate. | 01-10-2013 |
20130092935 | Probe Pad Design for 3DIC Package Yield Analysis - An interposer includes a first surface on a first side of the interposer and a second surface on a second side of the interposer, wherein the first and the second sides are opposite sides. A first probe pad is disposed at the first surface. An electrical connector is disposed at the first surface, wherein the electrical connector is configured to be used for bonding. A through-via is disposed in the interposer. Front-side connections are disposed on the first side of the interposer, wherein the front-side connections electrically couple the through-via to the probe pad. | 04-18-2013 |
20130113070 | Interposers for Semiconductor Devices and Methods of Manufacture Thereof - Interposers for semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, an interposer includes a substrate, a contact pad disposed on the substrate, and a first through-via in the substrate coupled to the contact pad. A first fuse is coupled to the first through-via. A second through-via in the substrate is coupled to the contact pad, and a second fuse is coupled to the second through-via. | 05-09-2013 |
20130120018 | Test Structure and Method of Testing Electrical Characteristics of Through Vias - A method and apparatus for testing the electrical characteristics, such as electrical continuity, is provided. A substrate, such as a wafer or an interposer, having a plurality of through vias (TVs) is provided. Along one side of the substrate, a conductive layer electrically couples two or more of the TVs. Thereafter, the electrical characteristics of the TVs may be test by, for example, a probe card in electrical contact with the TVs on the other side of the substrate. During testing, current passes through a first TV from a first side of the substrate, to the conductive layer on a second side of the substrate, to a second TV, and back to the first side of the substrate through the second TV. | 05-16-2013 |
20140106536 | Cylindrical Embedded Capacitors - A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate. | 04-17-2014 |
20140167269 | Methods and Apparatus of Packaging with Interposers - Methods and apparatus for forming a semiconductor device package on an interposer using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, where a micro-bump is used as a vertical connection between a die and the interposer, and a micro-bump line is used as a horizontal connection for signal transmission between different dies above the interposer. The micro-bump lines may be formed at the same time as the formation of the micro-bumps with little or no additional cost. | 06-19-2014 |
20140203397 | Methods and Apparatus for Inductors and Transformers in Packages - Methods and apparatus for forming a semiconductor device package with inductors and transformers using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top die and a bottom die, or between a die and an interposer. An inductor can be formed by a redistribution layer within a bottom device and a micro-bump line above the bottom device connected to the RDL. The inductor may be a symmetric inductor, a spiral inductor, a helical inductor which is a vertical structure, or a meander inductor. A pair of inductors with micro-bump lines can form a transformer. | 07-24-2014 |
20140327464 | TESTING OF SEMICONDUCTOR CHIPS WITH MICROBUMPS - A test structure including an array of microbumps electrically connecting a chip and a substrate, wherein a width of each microbump of the array of microbumps is equal to or less than about 50 microns (μm). The test structure further includes an interconnect structure connected to the array of microbumps. The test structure further includes an array of test pads around a periphery of the array of microbumps, wherein a test pad of the array of test pads is connected to a corresponding microbump of the array of microbumps through the interconnect structure. A width of the test pad is greater than a width of the corresponding microbump, and the test pad is adapted to be covered after circuit probing by a passivation material to prevent particle and corrosion issues. | 11-06-2014 |
20140374875 | 3D Inductor and Transformer - In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture. | 12-25-2014 |
20150031184 | METHODS OF MANUFACTURING A PACKAGE - A method of manufacturing a package may include: providing a first device having a first redistribution layer (RDL) and an insulator layer disposed over the first RDL; and forming a first micro-bump line over the insulator layer of the first device. The first micro-bump line may extend laterally over a surface of the insulator layer facing away from the first RDL, and a first inductor of the package comprises the first RDL and the first micro-bump line. | 01-29-2015 |