Patent application number | Description | Published |
20140272135 | DEPOSITION INJECTION MASKING - In deposition devices, a precursor is directed at a substrate within a deposition chamber, and a block plate comprising a set of block plate apertures adjusts the direction and volume of the outflowing precursor. However, arrangements of block plate apertures that are suitable for some deposition scenarios (such as one type of precursor) are unsuitable for other deposition scenarios, resulting in precursor deposition that is undesirably thick, thin, or inconsistent. A set of block plate masks positioned over respective zones of the block plate are adjustable to align a set of masking apertures with respect to the block plate apertures, such as by operating a block plate motor to rotate a ring-shaped block plate mask over a cylindrical zone of the block plate. This configuration enables adjustable exposure of the block plate apertures to control the adjusted outflow of precursor through the block plate. | 09-18-2014 |
20140272193 | DIRECTING PLASMA DISTRIBUTION IN PLASMA-ENHANCED CHEMICAL VAPOR DEPOSITION - Plasma-enhanced chemical vapor deposition (PECVD) devices enable the generation of a plasma in a plasma zone of a deposition chamber, which reacts with a surface of a substrate to form a deposited film in the fabrication of a semiconductor component. The plasma generator is often positioned over the center of the substrate, and the generated plasma often remains in the vicinity of the plasma generator, resulting in a thicker deposition near the center than at the edges of the substrate. Tighter process control is achievable by positioning one or more electromagnets in a periphery of the plasma zone and supplying power to generate a magnetic field, thereby inducing the charged plasma to achieve a more consistent distribution within the plasma zone and more uniform deposition on the substrate. Variations in the number, configuration, and powering of the electromagnets enable various redistributive effects on the plasma within the plasma zone. | 09-18-2014 |
20150252475 | CVD APPARATUS WITH GAS DELIVERY RING - The present disclosure relates to a chemical vapor deposition apparatus and associated methods. In some embodiments, the CVD apparatus has a vacuum chamber and a gas import having a gas import axis through which a process gas is imported into the vacuum chamber and being arranged near an upper region of the vacuum chamber. At least one exhaust port is arranged near a bottom region of the vacuum chamber. The CVD apparatus also has a gas delivery ring with an outlet disposed under the gas import. A pressure near the outlet of the gas delivery ring is smaller than that of the rest of the vacuum chamber. | 09-10-2015 |
20150270156 | SEMICONDUCTOR STRUCTURE AND METHOD MAKING THE SAME - The present disclosure provides a method for forming a semiconductor structure. In accordance with some embodiments, the method includes providing a substrate and a conductive feature formed over the substrate; forming a first etch stop layer over the conductive feature; forming a low-k dielectric layer over the first etch stop layer; etching the low-k dielectric layer to form a contact trench aligned with the conductive feature; performing a sputtering process to the first etch stop layer exposed in the contact trench; and forming a sealing oxide layer on the low-k dielectric layer. In some embodiments, the sealing oxide layer is self-aligned and conformed to surfaces of the low-k dielectric layer exposed in the contact trench. | 09-24-2015 |
20150303140 | SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING THE SAME - One or more semiconductor arrangements are provided. A semiconductor arrangement includes a first dielectric layer defining a first recess, a first contact in the first dielectric layer, a first metal cap over at least part of the first contact and a second dielectric layer over the first dielectric layer within the first recess and defining an air gap proximate the first contact. One or more methods of forming a semiconductor arrangement are also provided. Such a method includes forming a first metal cap on a first exposed surface of a first contact, the first metal cap having an extension region that extends into a first recess defined in a first dielectric layer and forming a second dielectric layer over the first dielectric layer within the first recess such that an air gap is defined within the second dielectric layer proximate the first contact due to the extension region. | 10-22-2015 |
20150311114 | SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING THE SAME - The present disclosure provides a method for forming a semiconductor structure. In accordance with some embodiments, the method includes providing a substrate and a conductive feature formed over the substrate; forming a low-k dielectric layer over the conductive feature; forming a contact trench aligned with the conductive feature; and selectively growing a sealing layer which is a monolayer formed on sidewalls of the contact trench. | 10-29-2015 |
20150318206 | METHOD FOR FORMING SEMICONDUCTOR STRUCTURE - One or more techniques or systems for forming a semiconductor structure having a gap are provided herein. In some embodiments, a gap is formed between a first etch stop layer (ESL) and an ESL seal region. For example, the gap is formed by removing a portion of a low-k (LK) dielectric region above an oxide region and removing the oxide region. In some embodiments, the oxide region below the LK dielectric region facilitates removal of the LK dielectric region, at least because the oxide region enhances a bottom etch rate of a bottom of the LK dielectric region such that the bottom etch rate is similar to a wall etch rate of a wall of the LK dielectric region. | 11-05-2015 |
Patent application number | Description | Published |
20150371940 | INSULATOR VOID ASPECT RATIO TUNING BY SELECTIVE DEPOSITION - Disclosed herein is a structure conductive lines disposed in a base layer and separated by a first region. Pillars are each disposed over a respective one of the conductive lines. A dielectric fill layer is disposed over the pillars and extending between the pillars into the first region, and a void is disposed in the dielectric fill layer in the first region between the conductive lines. | 12-24-2015 |
20150380303 | CONDUCTIVE ELEMENT STRUCTURE AND METHOD - Conductive element structures and methods of manufacture thereof are disclosed. In some embodiments, a method of forming a conductive element in an insulating layer includes: forming a recess in a metal layer disposed over the insulating layer; selectively forming a metal liner on a sidewall of the recess; and etching a via in the insulating layer using the metal layer and the metal liner as a mask. | 12-31-2015 |
20160005691 | Hybrid Copper Structure for Advance Interconnect Usage - The present disclosure relates to a method of forming a BEOL metallization layer that uses different conductive materials (e.g., metals) to fill different size openings in an inter-level dielectric layer, and an associated apparatus. In some embodiments, the present disclosure relates to an integrated chip having a first plurality of metal interconnect structures disposed within a first BEOL metallization layer, which include a first conductive material. The integrated chip also has a second plurality of metal interconnect structures disposed within the first BEOL metallization layer at positions laterally separated from the first plurality of metal interconnect structures. The second plurality of metal interconnect structures have a second conductive material that is different than the first conductive material. By forming different metal interconnect structures on a same BEOL metallization layer using different conductive materials, gap-fill problems in narrow BEOL metal interconnect structures can be mitigated, thereby improving reliability of integrated chips. | 01-07-2016 |