Patent application number | Description | Published |
20080236793 | WATER BLOCK - A water block is used to be adhered to a heat-generating element and includes a cavity. The cavity has a chamber therein. One side or both sides of the chamber is provided with an inlet pipeline and an outlet pipeline respectively, thereby communicating with the chamber. Further, the chamber is provided therein with a heat-exchanging means for performing a heat-exchanging action with a working fluid. Finally, the top face of the cavity is provided with a membrane. An activating element is adhered on the membrane for driving the membrane to swing up and down, thereby forcing the working fluid within the chamber to circulate in single direction. The activating element is used as a power source, and in addition, the water block can be made much thinner. | 10-02-2008 |
20080260552 | MEMBRANE PUMP - A membrane pump powered by an activating element includes a chamber body. The interior of the chamber body is provided with a first chamber and a second chamber that are in fluid communication with each other. One side or both sides of the chamber body are provided with an inlet pipeline and an outlet pipeline that are in fluid communication with the first chamber and second chamber, respectively. Valves are provided on the inner wall face of same side of the first chamber and the second chamber, thereby preventing the working fluid from generating a backflow phenomenon. Furthermore, the top surface of the chamber body is provided with a membrane. An activating element abuts on the membrane for driving the membrane to swing up and down, thereby pressing the working fluid within the first chamber to circulatively flow in one direction. Via this arrangement, in addition to miniaturize the pump structure to a further extent, the working performance of the pump and the flowing amount of the working fluid are also increased. | 10-23-2008 |
20080260553 | MEMBRANE PUMP DEVICE - A membrane pump device powered by an activating element includes a chamber body and a second chamber body. The interior of the chamber body is provided with a chamber. Both sides of the chamber body are provided with an inlet pipeline and an outlet pipeline that are in fluid communication with the aforementioned chamber, respectively. A valve is provided on the inner wall face of the chamber, thereby preventing the working fluid from generating a backflow phenomenon. Furthermore, the top surface of the chamber body is provided with a membrane. An activating element abuts on the membrane for driving the membrane to swing up and down, thereby pressing the working fluid within the chamber to circulatively flow in one direction. Finally, the second chamber body is in fluid communication with the chamber body. The interior of the second chamber body is provided with another valve. Via this arrangement, in addition to miniaturize the pump structure to a further extent, the working performance of the pump and the flowing amount of the working fluid are also increased. | 10-23-2008 |
20080283224 | WATER-COOLING HEAT-DISSIPATING SYSTEM - A water-cooling heat-dissipating system for facilitating a heat-dissipating action with a heat-generating element includes a water block and a heat exchanger. The above-mentioned components are in fluid communication with one another via a plurality of conduits. The water block is attached on the heat-generating element to absorb the heat generated by the heat-generating element. The top surface of the water block is provided with a membrane. The membrane is provided thereon with an activating element, so that the membrane swings up and down at one side thereof to guide the flow of the working fluid. The heat exchanger performs a heat-conducting action with the flowing working fluid, thereby dissipating the heat absorbed by the working fluid to the outside. In this way, the heat-generating element can be kept in a normal range of working temperature. | 11-20-2008 |
20080283225 | WATER-COOLING HEAT-DISSIPATING SYSTEM - A water-cooling heat-dissipating system for facilitating a heat-dissipating action with a heat-generating element includes a water block, a membrane pump, a water tank and a heat exchanger. The above-mentioned components are in fluid communication with one another via a plurality of conduits. The water block is attached on the heat-generating element to absorb the heat generated by the heat-generating element. The membrane pump generates a thrust to facilitate the working fluid to perform a cooling action. The water tank is used to store additional working fluid. The heat exchanger performs a heat-conducting action with the flowing working fluid, thereby dissipating the heat absorbed by the working fluid to the outside. In this way, the heat-generating element can be kept in a normal range of working temperature. | 11-20-2008 |
Patent application number | Description | Published |
20110111598 | METHOD FOR PREPARING PATTERNED SUBSTRATE BY USING NANO- OR MICRO- PARTICLES - A method for preparing patterned substrate by using nano- or micro-particles is disclosed, which comprises the following steps: (A) providing a substrate with a photoresist layer formed thereon; (B) coating a surface of the photoresist layer with plural nano- or micro-particles, to form a particle layer; (C) exposing and developing the photoresist layer to obtain a patterned photoresist layer; and (D) removing the particle layer. In addition, after the particle layer is removed, the method of the present invention further comprises: (E1) using the patterned photoresist layer as an etching template to etch the substrate; and (E2) removing the patterned photoresist layer to obtain a patterned substrate with plural cavities formed thereon. | 05-12-2011 |
20130026491 | LED STRUCTURE AND METHOD FOR MANUFACTURING THEREOF - The present invention discloses a LED structure and a method for manufacturing the LED structure. The LED structure includes a substrate, a reflection layer, a first conducting layer, a light emitting layer, and a second conducting layer. The substrate has a plurality of grooves, and the reflection layer is disposed inside the plurality of grooves. The reflection layer is formed as a reflection block inside each of the grooves. The first conducting layer is disposed on the substrate, that is, the reflection layer is disposed between the first conducting layer and the substrate. The light emitting layer and the second conducting layer are sequentially disposed on the first conducting layer. The light emitting layer generates light when a current pass through the light emitting layer. Accordingly, the light generated by the light emitting layer can be emitted to the same side of the LED structure. | 01-31-2013 |
20130112998 | SOLID STATE LIGHT EMITTING SEMICONDUCTOR DEVICE - A solid state light emitting semiconductor device including a substrate, a mesa epitaxy stacking structure, an insulating layer, a first type electrode and a second type electrode is provided. The mesa epitaxy stacking structure includes a first type semiconductor layer, an active layer and a second type semiconductor layer arranged in order. A concave area is formed in the middle of the mesa epitaxy stacking structure to expose a portion of the first type semiconductor layer. The insulating layer covers the exposed surface of the first type semiconductor layer around the mesa epitaxy structure, sidewalls of the mesa epitaxy stacking structure and a portion of surface of the second type semiconductor layer. The first type electrode is located on the exposed first type semiconductor layer in the concave area, and is surrounded by the second type electrode located on the insulating layer around the mesa epitaxy stacking structure. | 05-09-2013 |
Patent application number | Description | Published |
20090070516 | INTEGRATED MEMORY CONTROL APPARATUS - An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory. | 03-12-2009 |
20110252175 | INTEGRATED MEMORY CONTROL APPARATUS - An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory. | 10-13-2011 |
20110276739 | INTEGRATED MEMORY CONTROL APPARATUS - An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory. | 11-10-2011 |
20110276751 | INTEGRATED MEMORY CONTROL APPARATUS AND METHOD THEREOF - An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory. | 11-10-2011 |
Patent application number | Description | Published |
20090261450 | Electrical Fuse Structure and Method - An electrical fuse and a process of programming the same are presented. An electrical fuse comprises a lower level silicide layer on a non-doped or lightly-doped polysilicon layer, an upper level conductive layer, and a tungsten contact coupled between the lower level silicide layer and the upper level conductive layer. The tungsten contact and a neck portion of the silicide layer are the programmable portion of the electrical fuse. High post-programming resistance is achieved by a first programming phase that depletes silicide in the silicide layer, followed by a second programming phase that depletes tungsten in the tungsten contact. | 10-22-2009 |
20100090751 | Electrical Fuse Structure and Method - An electrical fuse and a process of programming the same are presented. An electrical fuse comprises a lower level silicide layer on a non-doped or lightly-doped polysilicon layer, an upper level conductive layer, and a tungsten contact coupled between the lower level silicide layer and the upper level conductive layer. The tungsten contact and a neck portion of the silicide layer are the programmable portion of the electrical fuse. High post-programming resistance is achieved by a first programming phase that depletes silicide in the silicide layer, followed by a second programming phase that depletes tungsten in the tungsten contact. | 04-15-2010 |
20130328131 | Semiconductor Devices, Methods of Manufacture Thereof, and Methods of Forming Resistors - Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor. | 12-12-2013 |
Patent application number | Description | Published |
20100127337 | INVERTER STRUCTURE AND METHOD FOR FABRICATING THE SAME - An inverter structure is disclosed. The inverter structure includes an NMOS transistor and a PMOS transistor. Preferably, the NMOS transistor includes an n-type gate electrode and an n-type source/drain region, and the PMOS transistor includes a p-type gate electrode and a p-type source/drain region. Specifically, the n-type gate electrode and the p-type gate electrode are physically separated and electrically connected by a conductive contact. | 05-27-2010 |
20100135093 | OPERATING VOLTAGE TUNING METHOD FOR STATIC RANDOM ACCESS MEMORY - An operating voltage tuning method for a static random access memory is disclosed. The static random access memory receives a periphery voltage and a memory cell voltage. The steps of the method mentioned above are shown as follows. First, perform a shmoo test on the static random access memory to obtain a shmoo test plot and a minimum operating voltage. Compare the minimum operating voltage with a preset specification. Position a specification position point on the line which the periphery voltage is equal to the memory cell voltage in the shmoo test plot corresponding to the preset specification. Fix one of the memory cell voltage and the periphery voltage and gradually decrease the other to test the static random access memory and obtain a failure bits distribution. Finally, tune process parameters of the static random access memory according to the specification position point and the failure bits distribution. | 06-03-2010 |
20120112782 | METHOD FOR PREDICTING TOLERABLE SPACING BETWEEN CONDUCTORS IN SEMICONDUCTOR PROCESS - A method for predicting tolerable contact-to-gate spacing is provided. At first, a wafer with a plurality of source/drain contacts are provided. Then, a plurality of testing gate lines are formed on the wafer by using a photomask. In one die, there are different contact-to-gate distances ranging from d+Δd to d−Δd wherein d is the standard spacing and Δd05-10-2012 | |
20120256273 | METHOD OF UNIFYING DEVICE PERFORMANCE WITHIN DIE - A method of unifying device performance within an integrated circuit die includes providing a layout of an integrated circuit die with multiple functional circuit blocks; filling a field between the multiple functional circuit blocks with dummy diffusion patterns; and filling the field between the multiple functional circuit blocks with dummy gate patterns such that the dummy gate patterns and the dummy diffusion patterns are completely overlapped. | 10-11-2012 |
20140203828 | LAYOUT STRUCTURE OF ELECTRONIC ELEMENT AND TESTING METHOD OF THE SAME THEREOF - A layout structure of an electronic element comprising an electronic matrix, a first load and a second load is disclosed. The first load couples to a first end of the electronic matrix and comprises a first testing pad and a second testing pad coupling to the first testing pad. The second load couples to a second end of the electronic matrix and comprises a third testing pad and a fourth testing pad coupling to the third testing pad. | 07-24-2014 |
20140354325 | SEMICONDUCTOR LAYOUT STRUCTURE AND TESTING METHOD THEREOF - A semiconductor layout structure and a testing method thereof are disclosed. The semiconductor layout structure includes a device under test (DUT), a first testing pad, a second testing pad and a plurality of third testing pads. The DUT includes a plurality of metal-oxide-semiconductor (MOS) transistors. Each of the MOS transistors includes a first terminal, a second terminal and a third terminal. The first testing pad is coupled to the first terminals for being applied a first voltage. The second testing pad is coupled to the second terminals for being applied a second voltage. The third testing pads are respectively coupled to the third testing pads for being applied a third voltage. The third testing pads are electrical insulated from each other. The third voltage is larger than the first voltage and the second voltage. | 12-04-2014 |
Patent application number | Description | Published |
20090167714 | METHOD OF OPERATING HANDHELD ELECTRONIC DEVICE AND TOUCH INTERFACE APPARATUS AND STORAGE MEDIUM USING THE SAME - A method of operating a handheld electronic device and a touch interface apparatus and a storage medium using the same are provided. In this method, an operating interface displayed on a touch screen of the handheld electronic device is used to operate a function module of the handheld electronic device. First, the function module of the handheld electronic device is activated to display a user interface corresponding to the function module on the touch screen. Next, an operating function of the function module is activated, so as to display a corresponding operating interface on the touch screen. In the meantime, the user interface of the function module is reduced simultaneously and displayed on an area of the touch screen excluding the operating interface. Accordingly, a convenient operating interface is provided for the user to operate while the content of original displayed frame remains. | 07-02-2009 |
20100274471 | ROUTE REPORTING METHOD, SYSTEM AND RECORDING MEDIUM USING THE SAME - A route reporting method, system, and a recording medium using the same are provided. The present method detects a touch and draws a path according to a moving trajectory of the touch. When the touch is finished, a dialog block is displayed to insert route mark information in the drawn path. The aforesaid steps are repeated to draw a plurality of paths. When an end signal is received, those paths are assembled to form a complete route map, which is provided for users to search for routes. | 10-28-2010 |
20130318470 | METHOD OF OPERATING HANDHELD ELECTRONIC DEVICE AND TOUCH INTERFACE APPARATUS AND STORAGE MEDIUM USING THE SAME - A method of operating a handheld electronic device and a touch interface apparatus and a storage medium using the same are provided. In this method, an operating interface displayed on a touch screen of the handheld electronic device is used to operate a function module of the handheld electronic device. First, the function module of the handheld electronic device is activated to display a user interface corresponding to the function module on the touch screen. Next, an operating function of the function module is activated, so as to display a corresponding operating interface on the touch screen. In the meantime, the user interface of the function module is reduced simultaneously and displayed on an area of the touch screen excluding the operating interface. Accordingly, a convenient operating interface is provided for the user to operate while the content of original displayed frame remains. | 11-28-2013 |
Patent application number | Description | Published |
20090111333 | ELECTRICAL CONNECTOR FOR COMPUTER PERIPHERAL DEVICE - An electrical connector of a computer peripheral device has an insulating base having a plurality of slots spaced along the side of the insulating base and each of the slots having a conductive terminal. Each of the conductive terminals has a first end and a second end. The first end protrudes up from the insulating base for electrically contact to a printed circuit board which is located above the insulating base within the computer peripheral device. The second end extends away from the insulating base for electrically coupling to a cable of the computer peripheral device. Therefore the electrical connector facilitates the connection between the printed circuit board and the cable of the computer peripheral device. | 04-30-2009 |
20090310289 | Quick-assembly computer peripheral - A quick-assembly computer peripheral has a bottom casing, a top casing, a vertical mounting device, an electronic assembly and a vertical positioning device. The vertical mounting device is mounted between the top and bottom casings and combining the top and bottom casings together along a vertical direction. The electronic assembly is mounted between the bottom and top casing and has a PCB and a cable assembly. The vertical positioning device mounted between the top and bottom casings and positioning the electronic assembly along the vertical direction. Because fabrication of the quick-assembly computer peripheral does not require fasteners, such as screws or rivets, fabrication is quick and easy. | 12-17-2009 |
20100022107 | Electronic device with retractable connector - An electronic device with a retractable connector has a housing, an electronic assembly being mounted in the housing and a positioning assembly being mounted between the housing and the electronic assembly. The housing has at least one positioning detent being formed in an inner surface of the housing. The electronic assembly has a circuit board and a connector being mounted on the circuit board and through the connector hole of the housing. The positioning assembly is securely mounted on the circuit board and selectively engages in the positioning detent of the housing. Since positioning structures are formed on the housing and the circuit board, the volume of the electronic device is reduced. In addition, no additional holes are formed through the housing and an original design and an appearance of the housing are kept. | 01-28-2010 |
20110042192 | Computer input device and waterproof button mechanism thereof - A waterproof button mechanism of a computer input device has a bottom case having a coding module and at least two micro switches mounted therein and connected with the inner case. Two mounting holes are formed on a front end of the inner case to respectively correspond to the two micro switches on the bottom case. Two waterproof assemblies are respectively mounted on the two mounting holes. A top cover is mounted on the inner case. Two slots are formed through a front end of the top cover. A button is movably mounted in the slot and a front end of the button corresponds to the waterproof assembly. When the button is pressed down, the input device is operated by triggering the micro switches through the waterproof assembly. The waterproof mechanism is waterproof function to be added without sacrificing easy customization of appearance. | 02-24-2011 |
Patent application number | Description | Published |
20100096034 | PROCESS FOR FABRICATING INTEGRAL PLASTIC FAUCET MEMBER AND FINISHED PRODUCT THEREOF - A process for fabricating an integral plastic faucet member and a finished product thereof are provided. The process mainly includes two injection steps. A first plastic injection is used to mold a first part at a middle connecting part of a faucet member. The first part is then placed into a mold for a second plastic injection so as to mold a second part at two sides of the faucet member. The second part is properly wrapped around and bonded to the first part. Meanwhile, desired holes are reserved to serve as water inlets, water outlets, and valve seats. Through such a two-injection process, the conventional complicated and time-consuming copper casting process is simplified, which improves the production efficiency and product quality, lows the cost and defective ratio. Meanwhile, the product weight is also reduced, which greatly reduces the transportation cost. | 04-22-2010 |
20120091626 | Process for fabricating an integral plastic faucet member - A process for fabricating an integral plastic faucet member contains two injection steps. A first plastic injection is used to mold a first part at a middle connecting part of a faucet member. The first part is then placed into a mold for a second plastic injection so as to mold a second part at two sides of the faucet member. The second part is properly wrapped around and bonded to the first part. Meanwhile, desired holes are reserved to serve as water inlets, water outlets, and valve seats. Through such a two-injection process, the conventional complicated and time-consuming copper casting process is simplified, which improves the production efficiency and product quality, lows the cost and defective ratio. Meanwhile, the product weight is also reduced, which greatly reduces the transportation cost. | 04-19-2012 |
Patent application number | Description | Published |
20090008803 | LAYOUT OF DUMMY PATTERNS - A layout of dummy patterns on a wafer having a plurality of pads disposed thereon is described. The layout of the dummy patterns includes having a plurality of dummy patterns spaced apart from each other and enclosing the plurality of the pads. The plurality of dummy patterns also include a plurality of peripheral dummy patterns and a plurality of central dummy patterns, wherein a minimum distance between the plurality of the central dummy patterns and the plurality of the pads is greater a minimum distance between the plurality of the peripheral dumpy patterns and the plurality of the pads. | 01-08-2009 |
20130076388 | TRANSISTOR ARRAY FOR TESTING - A transistor array for testing is provided. The transistor array includes a plurality of tested units. Each of the tested unit includes a tested transistor and a first to third switches. The tested transistor has a control terminal, a first and a second terminals and a bulk. The first switch is coupled between the first terminal and a leakage transporting line. The second switch is coupled between the second terminal and the leakage transporting line. The third switch is coupled between the control terminal and a bias providing line. The first to third switches are turned on or turned off according to a control signal. When the tested transistor is selected to be tested, the first to third switches are turned on according to the control signal. | 03-28-2013 |
20130221407 | MULTI-GATE TRANSISTOR DEVICE - A multi-gate transistor device includes a substrate, a fin structure extending along a first direction formed on the substrate, a gate structure extending along a second direction formed on the substrate, a drain region having a first conductivity type formed in the fin structure, a source region having a second conductivity type formed in the fin structure, and a first pocket doped region having the first conductivity type formed in and encompassed by the source region. The first conductivity type and the second conductivity type are complementary to each other. | 08-29-2013 |
20130240956 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device including a substrate, a plurality of isolation structures, at least a gate structure, a plurality of dummy gate structures and a plurality of epitaxial structures is provided. The substrate has an active area defined by the isolation structures disposed within the substrate. That is, the active area is defined between the isolation structures. The gate structure is disposed on the substrate and located within the active area. The dummy gate structures are disposed on the substrate and located out of the active area. The edge of each dummy gate structure is separated from the boundary of the active area with a distance smaller than 135 angstroms. The epitaxial structures are disposed within the active area and in a portion of the substrate on two sides of the gate structure. The invention also provided a method for fabricating semiconductor device. | 09-19-2013 |
20140089871 | Hierarchical Wafer Yield Prediction Method and Hierarchical Lifetime Prediction Method - For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield domain for wafer yield prediction and a lifetime domain for a wafer lifetime prediction, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised. | 03-27-2014 |
Patent application number | Description | Published |
20100168298 | METHOD FOR MANUFACTURING HYDROGENATED BLOCK COPOLYMER - The present invention relates to a method for manufacturing a substantially hydrogenated vinyl aromatic/conjugated diene block copolymer, which has a hydrogenation level of greater than 90 percent. The resulting substantially hydrogenated vinyl aromatic/conjugated diene block copolymer has advantageous physical properties suitable for use in discs, optical films, light guide plates, etc. | 07-01-2010 |
20110098412 | PARTIALLY HYDROGENATED POLYMER AND METHOD THEREOF - The present invention discloses a method for partially hydrogenating polymer. The method comprises providing a polymer having at least one vinyl aromatic block; and hydrogenating the polymer in presence of a heterogeneous catalyst on a support selected from the group consisting of BaSO | 04-28-2011 |
20120309907 | METHOD FOR PRODUCING EPOXIDIZED POLYMER - The present invention discloses a method for producing an epoxidized polymer. The method comprises the steps of: (1) providing a polymer solution containing a polymer having a conjugated diene group; (2) providing a catalyst solution dissolved in the polymer solution, the catalyst solution containing a transition metal ion and a ligand for bonding to the transition metal ion, the transition metal ion being selected from the group consisting of Ti, Mn, V, Mo, W and any combination thereof; and (3) epoxidizing double bonds of the conjugated diene group to produce the epoxidized polymer by providing an epoxidizing agent dissolved in the polymer solution containing the catalyst solution, wherein the epoxidizing agent is meta-chloroperoxybenzoic acid (mCPBA) or analogues thereof. | 12-06-2012 |
20140066578 | METHOD FOR HYDROGENATING POLYMER AND HYDROGENATED POLYMER THEREOF - A method for hydrogenating a polymer containing vinyl aromatic block and the hydrogenated polymer are provided. The method includes providing a polymer having at least one vinyl aromatic block; and hydrogenating the polymer in presence of a heterogeneous catalyst on a support, wherein the heterogeneous catalyst consists essentially of Ru, Zn and B, or Ru, Zn and P. | 03-06-2014 |
Patent application number | Description | Published |
20110175537 | AC LED LAMP - An alternating current (AC) light-emitting diode (LED) lamp includes a first AC power end, a second AC power end, a lighting module and a direct current (DC) power output circuit. The lighting module has a first end, a second end and at least one LED unit, wherein the first end is electrically coupled to the first AC power end. The at least one LED unit has one or more LEDs connected in series. The DC power output circuit has a first end and a second end, wherein the second end of the DC power output circuit is electrically coupled to the second AC power end, while the first end of the DC power output circuit is electrically coupled to the second end of the lighting module. The DC power output circuit has a DC output side. | 07-21-2011 |
20110181213 | FAN SYSTEM AND BRAKE CONTROL CIRCUIT THEREOF - A fan system including a motor with a coil, a storage unit, a driver, and a buffer circuit is provided. The coil module has a first connection terminal and a second connection terminal. The storage unit electrically couples with a voltage source, stores electrical energy when the voltage source is available, and releases the stored electrical energy to carry out a brake operation when the voltage source is unavailable. The driver electrically couples with the first and second connection terminals of the coil module to control a direction of an inductor current passing through the coil module. The buffer circuit electrically couples with the coil module. In the brake operation, the buffer circuit operates to form a transient potential between the first and second connection terminals of the coil module and to consume electrical energy of the inductor current, for gradually stopping the motor in a buffering time period. | 07-28-2011 |
20110187299 | FAN SYSTEM AND BRAKING CIRCUIT THEREOF - A fan system comprising a motor, a motor driving circuit and a control unit is disclosed. The motor driving circuit is coupled to the motor. The control unit is coupled to the motor driving circuit, generates a forward rotation command for controlling the motor to rotate in a predetermined direction when the control unit receives electrical power, and generates a backward rotation command for controlling the motor to rotate in a direction opposite to the predetermined direction when the control unit fails to receive the electrical power. | 08-04-2011 |
20110254490 | MOTOR-DRIVING APPARATUS - A motor-driving apparatus, comprising a main driving unit having a plurality of main current-driving ends coupled to a stator coil of a motor, a detection control unit coupled to the main driving unit, and an auxiliary driving unit coupled to the detection control unit and having a plurality of auxiliary current-driving ends. Wherein, the number of the main current-driving ends is the same as that of the auxiliary current-driving ends, and each of the main current-driving ends is connected to a respective one of the auxiliary current-driving ends in parallel. | 10-20-2011 |
20110266989 | MOTOR SYSTEM - A motor system comprises a motor and a driving module. The motor has a plurality coil units not electrically connected to each other. The driving module has a control unit, a driving unit and a circuit board. The control unit is coupled to the driving unit. The driving unit has a plurality of driving circuits. The number of the driving circuits is the same as the number of the coil units. Each of the driving circuits is coupled to a respective one of the coil units so as to form a plurality of independent coil loops. The control unit and the driving unit are mounted on the circuit board. | 11-03-2011 |
20120007510 | CONTROL MODULE WITH POWER SUPPLY DETECTION AND LAMP UTILIZING THE SAME - A lamp with power supply detection includes a power supply unit, a control module and a lighting module. The power supply unit provides a direct current (DC) voltage. The control module is coupled to the power supply unit, receives and stores the DC power, and generates a control signal according to whether the DC power is terminated or regained. The lighting module is coupled to the power supply unit and the control module, receives the DC power and adjusts brightness of the lighting module according to the control signal. | 01-12-2012 |
20140210347 | AC LED LAMP - An AC LED lamp includes first and second AC power ends, a lighting module and a DC power output circuit. The lighting module has first and second ends and an LED unit. The first end is connected to the first AC power end. The LED unit has one or more LEDs. The DC power output circuit has first and second ends. The second end of the DC power output circuit is coupled to the second AC power end. The first end of the DC power output circuit is coupled to the second end of the lighting module. The DC power output circuit has a DC output side and is not directly connected to the first AC power end. The DC power output circuit has a rectifying unit and a voltage limiting and filtering unit. The rectifying unit and the voltage limiting and filtering unit are coupled to the lighting module. | 07-31-2014 |
Patent application number | Description | Published |
20110079922 | INTEGRATED CIRCUIT WITH PROTECTIVE STRUCTURE, AND METHOD OF FABRICATING THE INTEGRATED CIRCUIT - A structure includes a semiconductor substrate having semiconductor devices formed on or in the substrate. An interconnecting metallization structure is formed over and connected to the devices. The interconnecting metallization structure including at least one dielectric layer. A passivation layer is deposited over the interconnecting metallization structure and the dielectric layer. At least one metal contact pad and at least one dummy metal structure are provided in the passivation layer. The contact pad is conductively coupled to at least one of the devices. The dummy metal structure is spaced apart from the contact pad and unconnected to the contact pad and the devices. | 04-07-2011 |
20110210444 | 3D Semiconductor Package Using An Interposer - A 3D semiconductor package using an interposer is provided. In an embodiment, an interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die. | 09-01-2011 |
20120305916 | Interposer Test Structures and Methods - An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads. | 12-06-2012 |
20130020698 | Pillar Design for Conductive Bump - A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material. | 01-24-2013 |
20130049220 | Through Silicon Via Keep Out Zone Formation Method and System - Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs. | 02-28-2013 |
20130113070 | Interposers for Semiconductor Devices and Methods of Manufacture Thereof - Interposers for semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, an interposer includes a substrate, a contact pad disposed on the substrate, and a first through-via in the substrate coupled to the contact pad. A first fuse is coupled to the first through-via. A second through-via in the substrate is coupled to the contact pad, and a second fuse is coupled to the second through-via. | 05-09-2013 |
20130120018 | Test Structure and Method of Testing Electrical Characteristics of Through Vias - A method and apparatus for testing the electrical characteristics, such as electrical continuity, is provided. A substrate, such as a wafer or an interposer, having a plurality of through vias (TVs) is provided. Along one side of the substrate, a conductive layer electrically couples two or more of the TVs. Thereafter, the electrical characteristics of the TVs may be test by, for example, a probe card in electrical contact with the TVs on the other side of the substrate. During testing, current passes through a first TV from a first side of the substrate, to the conductive layer on a second side of the substrate, to a second TV, and back to the first side of the substrate through the second TV. | 05-16-2013 |
Patent application number | Description | Published |
20080253113 | Illumination assembly - An illumination assembly comprises a base and at least one illumination cell. The base comprises a supply circuit for supplying an external power after connecting to a power source. The illumination cell is optionally connected to the base or removed from thereof, and includes a power storage unit stored with a storage power, a discharging circuit, and a charging circuit, wherein the power storage unit is electrically connected to the discharging circuit and the charging circuit. When the illumination cell is removed from the base, the storage power released from the power storage unit drives the illumination cell projecting an illumination light beam via the discharging circuit. When the illumination cell is assembled to the base, the supply circuit is electrically connected to the discharging circuit and the charging circuit respectively, so that the external power can drive the illumination cell projecting the illumination light beam and charge the power storage unit simultaneously. | 10-16-2008 |
20090040758 | Lighting assembly - A lighting assembly is adapted to be connected to at least one conductive connection hole of an illumination device. The lighting assembly comprises at least one lighting cell and connection mechanism, wherein the lighting cell comprises a base, at least one electrical connector and a lighting unit. The electrical connector and the lighting unit are connected to the base, and electrically connected with each other. The lighting unit has a plurality of lighting circuits linearly arranged thereon, and one end of the connection mechanism is electrically connected to the electrical connector. When the lighting assembly only comprises one lighting cell, the other end of the connection mechanism is connected to the electrode connection hole; while when the lighting assembly comprises a plurality of said lighting cells, the other end of the connection mechanism is selectively connected to the conductive connection hole and the other electrical connector of the neighbor lighting cell. | 02-12-2009 |
Patent application number | Description | Published |
20090191979 | GOLF CLUB HEAD - A golf club head is disclosed. The golf club head comprises a main body, a striking plate and a thermoplastic elastic vibration-absorbing material. The main body includes a chamber. The striking plate is disposed on the front side of the main body. The thickness of the striking plate is between 0.76 mm and 2.25 mm. The thermoplastic elastic shock absorber is formed in the chamber of the main body and touches the back of the striking plate, wherein the density of the thermoplastic elastic vibration-absorbing material is between 0.5 g/cm | 07-30-2009 |
20100160076 | GOLF CLUB HEAD - A golf club head includes a front face having a grooved striking zone for impacting a golf ball, a rear face opposite to said front face, a top portion, a sole portion, a toe portion, a heel portion, a hosel portion having a shaft-receiving bore. The toe portion surface meets the front face along a first edge, and the toe portion extends outwardly from the first edge in a direction away from the hosel portion such that the vertical projection of the toe portion onto a plane containing the front face is substantially located outside of the front face. Besides, the sole surface meets the rear face along a trailing edge and meets the toe portion surface along a second edge, and the angle included between the trailing edge and the second edge is less than 90 degrees. | 06-24-2010 |
20100292025 | GOLF CLUB HEAD - A golf club head includes a striking face having a plurality of grooves formed therein. At least one groove includes a first curved side surface, a second curved side surface opposite to the first curved side surface, and a bottom surface connecting the first and the second curved side surfaces. As viewed in the longitudinal direction of the at least one groove, the first and the second curved surfaces respectively have first and second involute profiles. A distance measured between the first and the second curved surfaces continuously increases from the bottom surface to the striking face. | 11-18-2010 |
Patent application number | Description | Published |
20090169045 | Display Device with Hidden Speaker Assemblies - A display device includes a display panel, a frame, and a speaker unit. The frame encloses a periphery of the display panel. The speaker unit includes a speaker housing and a speaker assembly. The speaker housing includes first and second housing parts. The first housing part is connected to the frame, has a front opening, and is formed with a hole. The second housing part is mounted on a rear side of the display panel, defines a chamber, and has an open end. The open end of the second housing part is connected to the first housing part such that the chamber in the second housing part is in spatial communication with the front opening in the first housing part through the hole. The speaker assembly is disposed in the chamber in the second housing part and is coupled electrically to the display panel. | 07-02-2009 |
20090277131 | Clamp Device and Packaging Box Assembly Incorporating Said Clamp Device - A clamp device clamps together two panels having aligned receiving holes, and includes a tubular wall adapted to be inserted into the aligned receiving holes and having a through hole, first and second abutment plates connected hingedly and oppositely to the tubular wall within the through hole, first and second clamping plates projecting transversely and respectively from the first and second abutment plates, two resilient arms projecting from the second abutment plate and respectively having engaging ends, and a locker having two groove sidewalls formed on the first abutment plate and confining a groove therebetween. The clamping plates move away from each other to a clamping position when the abutment plates abut against the tubular wall. The groove receives and locks the engaging ends when the abutment plates abut against the tubular wall, thereby locking the clamping plates in the clamping position. | 11-12-2009 |
Patent application number | Description | Published |
20100196803 | Methods for Cell Boundary Isolation in Double Patterning Design - A method of designing a double patterning mask set for a layout of a chip includes designing standard cells. In each of the standard cells, all left-boundary patterns are assigned with one of a first indicator and a second indicator, and all right-boundary patterns are assigned with an additional one of the first indicator and the second indicator. The method further includes placing the standard cells in a row of the layout of the chip. Starting from one of the standard cells in the row, indicator changes to the standard cells are propagated throughout the row. All patterns in the standard cells having the first indicator are transferred to a first mask of the double patterning mask set. All patterns in the standard cells having the second indicator are transferred to a second mask of the double patterning mask set. | 08-05-2010 |
20100281446 | Integrated Circuit Design using DFM-Enhanced Architecture - Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first active region in the first standard cell has a different length of diffusion than a second active region in the second standard cell. The first active region and the second active region are corresponding active regions represented by a same component of a same circuit diagram representing both the first standard cell and the second standard cell. | 11-04-2010 |
20110193234 | Methods for Double-Patterning-Compliant Standard Cell Design - A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells. | 08-11-2011 |
20120091592 | Double Patterning Technology Using Single-Patterning-Spacer-Technique - A method of forming an integrated circuit structure includes forming a first and a second plurality of tracks parallel to a first direction and on a wafer representation. The first and the second plurality of tracks are allocated in an alternating pattern. A first plurality of patterns is laid out on the first plurality of tracks and not on the second plurality of tracks. A second plurality of patterns is laid out on the second plurality of tracks and not on the first plurality of tracks. The first plurality of patterns is extended in the first direction and in a second direction perpendicular to the first direction, so that each of the second plurality of patterns is surrounded by portions of the first plurality of patterns, and substantially none of neighboring ones of the first plurality of patterns on the wafer representation have spacings greater than a pre-determined spacing. | 04-19-2012 |
20120167021 | Cell Layout for Multiple Patterning Technology - A system and method for providing a cell layout for multiple patterning technology is provided. An area to be patterned is divided into alternating sites corresponding to the various masks. During a layout process, sites located along a boundary of a cell are limited to having patterns in the mask associated with the boundary site. When placed, the individual cells are arranged such that the adjoining cells alternate the sites allocated to the various masks. In this manner, the designer knows when designing each individual cell that the mask pattern for one cell will be too close to the mask pattern for an adjoining cell. | 06-28-2012 |
20120313256 | Non-Hierarchical Metal Layers for Integrated Circuits - An integrated circuit structure includes a semiconductor substrate, and a first metal layer over the semiconductor substrate. The first metal layer has a first minimum pitch. A second metal layer is over the first metal layer. The second metal layer has a second minimum pitch smaller than the first minimum pitch. | 12-13-2012 |
Patent application number | Description | Published |
20100206020 | ELECTRIC STEERING LOCK FOR MOTORCYCLE - An electric steering lock for a motorcycle includes a housing, a transmission assembly, a spindle, a set of sensors and a circuit board. The transmission assembly has an actuator, a first gear, a second gear and a sliding block each arranged within the housing in transmissive engagement with each other. The spindle is assembled with the sliding block and acts in the housing. A primary control chip of the motorcycle controls the circuit board to make the transmission assembly to drive the spindle to move accordingly. The circuit board determines that the spindle is locked and reaches a predetermined position if the sliding block presses the front sensor, and the circuit board determined that the spindle is unlocked and reaches a predetermined position if the sliding block presses the rear sensor. | 08-19-2010 |
20100212378 | ELECTRIC STEERING LOCK FOR MOTORCYCLE - An electric steering lock for a motorcycle includes a housing, a transmission assembly, a spindle, and a circuit board. The transmission assembly has an actuator, a first gear, a second gear and a sliding block each arranged within the housing in transmissive engagement with each other. The spindle is assembled with the sliding block and acts in the second space. The circuit board is arranged on the bottom of the housing. The primary control chip of the motorcycle controls the circuit board to make the transmission assembly to drive the spindle to move accordingly. The sliding block touches an inner wall of the casing to make it unable to move forwards or backwards any more. The current of the actuator at this time is larger than that in its normal operation. The rotation of the actuator is ceased by the circuit board when a variation in current of the actuator is detected by the circuit board. | 08-26-2010 |