Patent application number | Description | Published |
20100052745 | DELAY LOCKED LOOP CIRCUIT - A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock. | 03-04-2010 |
20100054055 | DATA INPUT/OUTPUT CIRCUIT - A data input/output circuit includes an output unit for outputting a first data strobe signal and first data in response to an internal clock generated in a delay locked loop, a first transmission line unit having a clock tree structure for transmitting the internal clock to the output unit, a second transmission line unit for transmitting the internal clock from the delay locked loop to the first transmission line unit, a duty cycle ratio correcting unit interconnected between the first transmission line unit and the second transmission line unit for correcting a duty cycle ratio of the internal clock, a data strobe signal input unit for receiving a second data strobe signal from an outside of a semiconductor memory device and generating an internal data strobe signal, and a plurality of data input units for outputting a second data in response to the internal data strobe signal. | 03-04-2010 |
20100295588 | DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - The present invention relates to a delay locked loop (DLL) circuit. The DLL circuit includes a phase comparator configured to compare a phase of a source clock with a phase of a feedback clock and generate a delay locking signal based on the comparison result, a clock delay configured to delay the source clock in response to the delay locking signal for locking delay, output the delayed source clock as a delay locked clock, and generate a delay end signal when a delay amount has reached a delay limit, a delay replica model configured to reflect a delay time of an output path of the source clock at the delay locked clock and output the reflected clock as the feedback clock, and a delay locking operation controller configured to terminate a delay locking operation in response to the delay locking signal and the delay end signal. | 11-25-2010 |
20110018600 | DELAY LOCKED LOOP CIRCUIT - A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock. | 01-27-2011 |
20110074478 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus for reducing unnecessary current consumption disclosed. The semiconductor apparatus includes: a clock signal transmission unit that selectively transmits a clock signal in accordance with the frequency of the clock signal at an operation standby mode. A delay locked loop generates a DLL clock signal on the basis of the clock signal inputted through the clock signal transmission unit. The delay locked loop generates the DLL clock signal during a period where the clock signal is transmitted. | 03-31-2011 |
20110095797 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes a clock delay section configured to receive an external clock signal, reflect different delay amounts on the external clock signal, and generate a plurality of synchronization clock signals, a clock synchronization section configured to synchronize a clock enable signal with each of the plurality of synchronization clock signals in an order beginning with a synchronization clock signal, on which a largest delay amount is reflected, to a synchronization clock signal, on which a smallest delay amount is reflected, and to generate a synchronized clock enable signal, and an internal clock generation section configured to generate an internal clock signal corresponding to the external clock signal, and to be on/off controlled in its operation in response to the synchronized clock enable signal. | 04-28-2011 |
20120007639 | SEMICONDUCTOR DEVICE - A semiconductor device includes a reset signal generator configured to change the number of activated signals among a plurality of reset signals according to a frequency of an external clock, a plurality of mixing control signal generators configured to generate a plurality of first and second mixing control signals, and a clock mixer configured to generate a mixing clock by mixing a first driving clock and a second driving clock, wherein the first driving clock is generated by driving a positive clock of the external clock according to the plurality of first mixing control signals, and the second driving clock is generated by driving a negative clock of the external clock according to the plurality of second mixing control signals. | 01-12-2012 |
20120007645 | DELAY LOCKED LOOP CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME - A delay locked loop (DLL) circuit includes a timing pulse generating unit configured to generate a plurality of timing pulses, which are sequentially pulsed during delay shifting update periods, in response to a source clock, wherein the number of the generated timing pulses changes according to a frequency of the source clock; a clock delay unit configured to compare a phase of the source clock with a phase of a feedback clock at a time point defined by each of the timing pulses, and delay a phase of an internal clock, corresponding to a rising or falling edge of the source clock, according to the comparison result; and a delay replica modeling unit configured to reflect actual delay conditions of the internal clock path on an output clock of the clock delay unit, and to output the feedback clock. | 01-12-2012 |
20150102838 | SEMICONDUCTOR DEVICE AND METHOD FOR DETECTING STATE OF INPUT SIGNAL OF SEMICONDUCTOR DEVICE - A semiconductor device includes a signal detection unit suitable for detecting a state of an input signal and generating a detection signal based on a detected result, and a signal transmission unit suitable for selectively transmitting the input signal in response to the detection signal, wherein the signal detection unit includes a state signal generation unit suitable for detecting a level shifting time of the input signal, and generating a state signal at a detected level shifting time, and a state determination unit suitable for comparing a voltage level of the input signal with a voltage level of a reference voltage in response to the state signal, and outputting the detection signal. | 04-16-2015 |
20150226786 | SEMICONDUCTOR SYSTEM AND OPERATING METHOD THEREOF - A semiconductor system includes a semiconductor device suitable for generating measuring data, and a controller suitable for comparing the measuring data with a given expected value and controlling a voltage level, which is supplied to the semiconductor device, based on the comparison result. | 08-13-2015 |
Patent application number | Description | Published |
20090177820 | CONTROL BUS FOR CONNECTION OF ELECTRONIC DEVICES - A method and apparatus for a control bus for connection of electronic devices. An embodiment of a method includes coupling a transmitting device to a receiving device, including connecting a control bus between the transmitting device and the receiving device, with the control bus being a bi-directional, single-line bus. The method further includes obtaining control of the control bus for either the transmitting device or the receiving device, with the device obtaining control becoming an initiator and the other device becoming a follower. One or more control signals are converted to one or more data packets, with each of the one or more control signals representing one of multiple different types of control signals. The generated data packets are transmitted from the initiator to the follower via the control bus. | 07-09-2009 |
20090178097 | METHOD, APPARATUS AND SYSTEM FOR GENERATING AND FACILITATING MOBILE HIGH-DEFINITION MULTIMEDIA INTERFACE - A method, apparatus and system are provided for generating and facilitating Mobile High-Definition Multimedia Interface. In one embodiment, an apparatus includes a transmitter configured to merge multiple channels of a high-definition interface into a single channel to generate a mobile high-definition interface, the mobile high-definition interface configured to facilitate carrying of high-definition media content in a mobile device. The apparatus further includes a receiver coupled with the transmitter, the receiver configured to receive the single channel, and to unmerge the single channel into the multiple channels. | 07-09-2009 |
20090219447 | METHOD, APPARATUS, AND SYSTEM FOR DECIPHERING MEDIA CONTENT STREAM - A method, apparatus and system for media content deciphering is disclosed. In one embodiment, a first content stream is received at a receiver device from a transmitter device coupled to the receiver device, wherein the first content stream having media content formatted in a particular package structure, the media content is associated with High-Definition Content Protection (HDCP) values. The first content stream is deciphered into a second content stream by removing the HDCP values from the first content stream, while the package structure of the media content is maintained. | 09-03-2009 |
20090222905 | METHOD, APPARATUS, AND SYSTEM FOR PRE-AUTHENTICATION AND PROCESSING OF DATA STREAMS - A method, apparatus and system for pre-authenticating ports is disclosed. In one embodiment, an active port facilitating communication of media content between a transmitting device and a receiving device is identified, while the active port are associated with a first High-Definition Content Protection (HDCP) engine. Then, inactive ports that are in idle mode serving as backup ports to the active port are identified, while the inactive ports are associated with a second HDCP engine. Pre-authentication of each of the inactive ports is performed so the pre-authenticated inactive ports can subsequently replace the active port if a port switch is performed. | 09-03-2009 |
20100146265 | Method, apparatus and system for employing a secure content protection system - A method, apparatus and system for employing a secure content protection system is disclosed. In one embodiment, a certificate having a unique device identification associated with a first device is received, and, at a second device, a revocation list having unauthorized device identifications is received. The unique device identification is incrementally compared with the unauthorized device identifications of the revocation list, and media content is transmitted from the second device to the first device, if the unique device identification is not matched with the unauthorized device identifications of the revocation list. | 06-10-2010 |
20100177892 | METHOD, APPARATUS, AND SYSTEM FOR PRE-AUTHENTICATION AND KEEP-AUTHENTICATION OF CONTENT PROTECTED PORTS - A method, apparatus and system for providing pre-authentication and keep-authentication of content protected ports system employing a ratio of one decipher processing engine (e.g., HDCP engine) associated with multiple ports is disclosed is disclosed. In one embodiment, a receiving device is pre-authenticated by a transmitting device, wherein the receiving device to receive a data stream from the transmitting device via a first data path. Further, a first High-Definition Content Protection (HDCP) engine is associated with a first port in the first data path, the first HDCP engine coupled with a second HDCP engine. The second HDCP engine is associated with a plurality of ports in a second data path, each of the plurality of ports associated with a memory pipe having state information relating to each of the plurality of ports, the state information being used to pre-authenticate the receiving device. | 07-15-2010 |
20100180115 | METHOD AND SYSTEM FOR DETECTING SUCCESSFUL AUTHENTICATION OF MULTIPLE PORTS IN A TIME-BASED ROVING ARCHITECTURE - In one embodiment of the present invention, a method includes authenticating an HDCP transmitting device at a first port of an HDCP receiving device. A port of the HDCP receiving device is connected to a pipe of an HDCP architecture of the HDCP receiving device at a first time. A synchronization signal is received from the HDCP transmitting device at the port of the HDCP receiving device at a second time. A loss of synchronization between the HDCP transmitting device and the HDCP receiving device is detected when the time-span between the first time and the second time is not greater than the period of time between synchronization signals sent from the HDCP transmitting device. A re-authentication is initiated between the HDCP transmitting device and the HDCP receiving device in response to detecting the loss of synchronization. | 07-15-2010 |
20110149032 | TRANSMISSION AND HANDLING OF THREE-DIMENSIONAL VIDEO CONTENT - Embodiments of the invention are generally directed to transmission and handling of three-dimensional video content. An embodiment of a method includes receiving a multimedia data stream including video data utilizing an interface protocol and determining that the received video data includes three-dimensional (3D) video data, where each frame of the video data includes a first vertical synchronization (Vsync) signal prior to an active data region, the active data region including a first data region and a second data region. The method further includes converting the 3D video data from a 3D data format to a two-dimensional (2D) video format, where converting the 3D video data includes identifying a region between the first data region and the second data region, inserting a second Vsync signal between the first data region and the second data region, and providing an identifier to distinguish between the first data region and the second data region. | 06-23-2011 |
20110157473 | METHOD, APPARATUS, AND SYSTEM FOR SIMULTANEOUSLY PREVIEWING CONTENTS FROM MULTIPLE PROTECTED SOURCES - A method, apparatus and system for simultaneously previewing contents from multiple protected sources. A primary data stream associated with a primary port is generated, the primary data stream having a primary image to be displayed on a display screen. A secondary data stream is generated associated with a plurality of secondary ports coupled with the primary port, the secondary data stream having a plurality of secondary images received from the plurality of secondary ports. The secondary data stream and the primary data stream are merged into a display data stream, the display data stream having the primary image and further having the plurality of secondary images as a plurality of preview images. The primary image and the plurality of preview images are displayed on the display screen, wherein each of the plurality of preview images is displayed through an inset screen on the display screen. | 06-30-2011 |
20110170011 | TRANSMISSION AND DETECTION OF MULTI-CHANNEL SIGNALS IN REDUCED CHANNEL FORMAT - Embodiments of the invention are generally directed to transmission and detection of multi-channel signals in reduced channel format. An embodiment of a method for transmitting data includes determining whether a first type or a second type of content data is to be transmitted, where the first type of content data is to be transmitted at a first multiple of a base frequency and the second type of data is to be transmitted at a second multiple of the base frequency. The method further includes selecting one or more channels from a plurality of channels based on the type of content data, clocking a frequency on the first or second multiple of the base frequency according to the type of content data in the selected channels, modifying the content data to fit within a single output channel, and transmitting the modified data via a single output channel at the chosen multiple of the base frequency. | 07-14-2011 |
20110310301 | MECHANISM FOR MEMORY REDUCTION IN PICTURE-IN-PICTURE VIDEO GENERATION - A mechanism for memory reduction in picture-in-picture video generation is disclosed. A method of embodiments of the invention includes receiving, from a transmitting device, a plurality of video streams at a receiving device coupled to the transmitting device, wherein a first video stream of the plurality of video streams is designated to be displayed as a main video and one or more other video streams of the plurality of video streams are designated to be displayed as one or more sub videos to the main video. The method further includes transforming the one or more other video streams into the one or more sub videos, temporarily holding the one or more sub videos in a compressed frame buffer, and merging, via pixel replacement, the main video and the one or more sub videos into a final video image capable of being displayed on a single screen utilizing a display device, wherein pixel replacement is performed such that the one or more sub videos occupy one or more sections of pixels of screen space pixels occupied by the main video. | 12-22-2011 |
20120092450 | COMBINING VIDEO DATA STREAMS OF DIFFERING DIMENSIONALITY FOR CONCURRENT DISPLAY - Embodiments of the invention are generally directed to combining video data streams of differing dimensionality for concurrent display. An embodiment of an apparatus includes an interface to receive multiple video data streams, a dimensionality of each video stream being either two-dimensional (2D) or three-dimensional (3D). The apparatus further includes a processing module to process a first video data stream as a main video image and one or more video data streams as video sub-images, the processing module including a video combiner to combine the main video data stream and the sub-video data streams to generate a combined video output. The processing module is configured to modify a dimensionality of each of the video sub-images to match a dimensionality of the main video image. | 04-19-2012 |
20120147271 | MULTIMEDIA I/O SYSTEM ARCHITECTURE FOR ADVANCED DIGITAL TELEVISION - Embodiments of the invention are generally directed to a multimedia I/O system architecture for advanced digital television. An embodiment of a multimedia system includes an I/O (input/output) control chip, the I/O control chip including one or more audio/video sub-processing engines for the processing of one or more data streams; a processing core chip for the processing of data, including audio/video data received from the I/O control chip; and one or more shared I/O channels for the transfer of data between the I/O control chip and the processing core chip. | 06-14-2012 |
20120182473 | MECHANISM FOR CLOCK RECOVERY FOR STREAMING CONTENT BEING COMMUNICATED OVER A PACKETIZED COMMUNICATION NETWORK - A mechanism for facilitating clock recovery for streaming content over a packetized network is described. A method of embodiments includes receiving an estimated data stream at a first device. The estimated data stream may include estimated data format information relating to a data stream expected to be received at the first device. The method may further include performing, at the first device, clock regeneration of the estimated data stream based on the estimated data format information. The clock regeneration may include performing clock recovery of the estimated data stream. | 07-19-2012 |
20120188444 | CONVERSION AND PROCESSING OF DEEP COLOR VIDEO IN A SINGLE CLOCK DOMAIN - Embodiments of the invention are generally directed to conversion and processing of deep color video in a single clock domain. An embodiment of a method includes receiving one or more video data streams, the one or more video data streams including a first video data stream, the first video data stream being clocked at a frequency of a link clock signal. The method further includes converting the first video data stream into a converted video data stream having a modified data format, wherein the modified data format includes transfer of a single pixel of data in one cycle of the link clock signal and the insertion of null data to fill empty cycles of the converted video data stream, and generation of a valid data signal to distinguish between valid video data and the null data in the converted video data stream. The method further includes processing the converted video data stream according to the frequency of the link clock signal to generate a processed data stream from the converted video data stream, wherein processing includes using the valid data signal to identify valid video data. | 07-26-2012 |
20120257699 | ADJUSTMENT OF CLOCK SIGNALS REGENERATED FROM A DATA STREAM - Embodiments of the invention are generally directed to adjustment of clock signals regenerated from a data stream. An embodiment of a method includes receiving a data stream from a transmitting device via a communication link, the data stream including stream data, a link clock signal, and timestamps to indicate a relationship between the link clock signal and a stream clock signal. The method further includes adjusting the stream clock based at least in part on one or more measurements related to the data stream, the one or more measurements including a count of a number of pulses of the stream clock during a period of time, or a measurement of a number of data elements from the data stream stored in a buffer at a certain point in time. | 10-11-2012 |
20120287344 | AUDIO AND VIDEO DATA MULTIPLEXING FOR MULTIMEDIA STREAM SWITCH - Embodiments of the invention describe a multimedia stream switch capable of multiplexing the audio and the video data of a multimedia stream separately. The multiplexing features of embodiments of the invention enable a multimedia stream switch to control each multimedia data type separately instead of multiplexing the whole streams (i.e., multiplexing sets of audio/video data together). Furthermore, prior art multimedia stream switches need to regenerate audio clocks by using phase locked loop (PLL) circuitry which incurs manufacturing and development costs. Embodiments of the invention provide the mixing of audio and video data from different sources without the need for PLL circuitry. | 11-15-2012 |
20130336334 | MULTIPLE PROTOCOL TUNNELING USING TIME DIVISION OPERATIONS - Embodiments of the invention are generally directed to multiple protocol tunneling using time division operations. An embodiment of an apparatus includes an interface for communication with a second apparatus, the interface including a shared communication link; and a multiplexer to multiplex data of each of multiple protocols into time slots for transmission, the protocols including a first protocol. The time slots are distributed among the protocols, where the distribution of the time slots among the protocols includes assigning one or more time slots to the first protocol to enable the data of the first protocol to meet one or more performance requirements for the first protocol. | 12-19-2013 |
20140111691 | MECHANISM FOR MEMORY REDUCTION IN PICTURE-IN-PICTURE VIDEO GENERATION - A mechanism for memory reduction in picture-in-picture video generation is disclosed. A method of embodiments of the invention includes receiving, from a transmitting device, a plurality of video streams at a receiving device coupled to the transmitting device, wherein a first video stream of the plurality of video streams is designated to be displayed as a main video and one or more other video streams of the plurality of video streams are designated to be displayed as one or more sub videos to the main video. The method further includes transforming the one or more other video streams into the one or more sub videos, temporarily holding the one or more sub videos in a compressed frame buffer, and merging, via pixel replacement, the main video and the one or more sub videos into a final video image capable of being displayed on a single screen utilizing a display device, wherein pixel replacement is performed such that the one or more sub videos occupy one or more sections of pixels of screen space pixels occupied by the main video. | 04-24-2014 |
20140247889 | Transmission And Detection Of Multi-Channel Signals In Reduced Channel Format - Embodiments of the invention are generally directed to transmission and detection of multi-channel signals in reduced channel format. An embodiment of a method for transmitting data includes determining whether a first type or a second type of content data is to be transmitted, where the first type of content data is to be transmitted at a first multiple of a base frequency and the second type of data is to be transmitted at a second multiple of the base frequency. The method further includes selecting one or more channels from a plurality of channels based on the type of content data, clocking a frequency on the first or second multiple of the base frequency according to the type of content data in the selected channels, modifying the content data to fit within a single output channel, and transmitting the modified data via a single output channel at the chosen multiple of the base frequency. | 09-04-2014 |
20140340579 | Encoding Guard Band Data For Transmission Via A Communications Interface Utilizing Transition-Minimized Differential Signaling (Tmds) Coding - The present disclosure is related to a hardware component for communications over a multimedia communication interface. In one embodiment, a hardware component includes a disparity circuit that stores a disparity value. The disparity value indicates the disparity between the number of “1”s and the number of “0”s previously transmitted by the hardware component. The hardware component also includes circuitry for receiving multimedia data to be scrambled, encoded and transmitted by the hardware component. In one embodiment, the multimedia data includes video data and data island data. In one embodiment, the hardware component generates transition minimized intermediate codes based on values in the guard band data included within the video data and data island data. The hardware component generates encoded guard band codes that are transition minimized as well as direct current balanced. The hardware component transmits the encoded guard band codes over a differential pair of the multimedia communication device. | 11-20-2014 |
20150036756 | Radio Frequency Interference Reduction In Multimedia Interfaces - A device for communications over a multimedia communication interface. The device can be a source device including a scrambling circuit that receives control data associated with multimedia data to be transmitted over the multimedia channel of the multimedia communication interface, and generates scrambled control codes based on the control data. An encoding circuit generates transition minimized control codes based on the scrambled control codes. The device transmits the transition minimized control codes to a sink device via the multimedia channel. The sink device may also decode and de-scramble the transition minimized control codes received from the source device via the multimedia channel. | 02-05-2015 |
20150181157 | APPARATUS, SYSTEM AND METHOD FOR FORMATTING AUDIO-VIDEO INFORMATION - Techniques and mechanisms for formatting digital audio-video (“AV”) information. In an embodiment, interface logic includes circuitry to receive digital AV information which, in one or more respects, is according to or otherwise compatible with a first interface specification. The interface logic changes a format of the digital AV information to allow for subsequent physical layer processing which is according to a second interface specification. In another embodiment, conversion logic receives analog signals according to the second interface specification and, based on such analog signals, performs digital information processing for subsequent generation of other analog signals to be transmitted according to the first interface specification. | 06-25-2015 |
20150256842 | Compressed Video Transfer over a Multimedia Link - A transmitting device for communicating via a multimedia communication link includes link layer circuitry to receive video data and to compress the video data into compressed video data. The transmitting device also includes a compression information circuit that generates video compression control information describing compression of the video data. The transmitting device further includes an interface that transmits signals corresponding to the compressed video data via one or more multimedia channels of the multimedia communication link and to transmit signals corresponding to the video compression control information via the multimedia communication link. | 09-10-2015 |
20150256863 | Compressed Blanking Period Transfer over a Multimedia Link - A transmitting device for communicating via a multimedia communication link includes a compression circuitry that receives blanking period data corresponding to blanking states of video blanking periods. The compression circuitry compresses the blanking period data into compressed blanking period data. The transmitting device also includes an interface that transmits signals corresponding to the compressed blanking period data via one or more multimedia channels of the multimedia communication link. | 09-10-2015 |
20150293879 | Bidirectional Transmission Of USB Data Using Audio/Video Data Channel - Embodiments relate to half-duplex bidirectional transmission of data compliant with a first standard (e.g., Universal Serial Bus (USB) standard) over a physical channel of a multimedia link for transmitting audio/video (“A/V”) data compliant with a second standard (e.g., Mobile High-Definition Link (MHL) standard) between a source device and a sink device using time division multiplexing (TDM). The source device sends units of data including A/V data and forward data compliant with the first standard at first times whereas the sink device sends units of data including backward data compliant with the first standard at second times between transmissions from the source device. The first times do not overlap with the second times. Synchronization signals may be added to the first and second units of data to align character symbols embedded in the first and second units of data. | 10-15-2015 |
20150295903 | Efficient Routing of Streams Encrypted Using Point-to-Point Authentication Protocol - Embodiments relate to routing encrypted data from a source to a sink via a router without decrypting the data in the router. The source authenticates with the router, the result of which produces a session key and a pseudo-random number. The router authenticates with the sink using the same session key and pseudo-random number. The router passes encrypted data received from the source to the sink without decryption and re-encryption. | 10-15-2015 |
20150295978 | Communication of Multimedia Data Streams over Multiple Communication Lanes - A transmitter and receiver for communication of multimedia streams across a multi-lane communications link. The transmitter packetizes multimedia streams according to a link layer protocol and distributes the packets across multiple lanes of a communications link. The entire packet, including the header and payload, can be distributed across the lanes in an ordered sequence to increase utilization of the communication lanes. The transmitter may also packetize multiple multimedia streams and intermix the packets across the lanes of the communication lane. The receiver extracts the packets that are distributed across the multiple lanes and decodes the packets into the multimedia streams. | 10-15-2015 |
20150326884 | Error Detection and Mitigation in Video Channels - A system for detecting and mitigating bit errors in transmitted media is described herein. A source device encodes a frame of video, and generates an error code representative of a portion of the encoded frame of video. The portion of encoded frame and the error code are provided to a sink device via a communication channel, such as an HDMI or MHL3 channel. A second error code is generated by the sink device based on the portion of encoded frame, and the error code and second error code are compared to determine if the portion of encoded frame includes an error. If no error is detected, the portion of encoded frame is decoded and outputted. If an error is detected, the portion is replaced with frame data based on at least one other portion of encoded frame to produce a mitigated frame, and the mitigated frame is outputted. | 11-12-2015 |
20160072601 | Enhanced Communication Link Using Synchronization Signal as Link Command - A system communicating over a full duplex control channel of a multimedia communication link by using synchronization signals that may also function as a logical link command. Synchronization indicators are exchanged between two communicating devices for maintaining synchronization of a logical link. At least two different types of synchronization signals may be sent between the two devices as synchronization indicators. A first synchronization signal is used by default to maintain synchronization of a logical link. A second synchronization signal is used in place of the first synchronization signal to maintain synchronization of the logical link. The second synchronization signal may be used to imply a virtual link command to indicate that a device is ready to receive data or has successfully received data over the virtual link. | 03-10-2016 |
20160105714 | Secure Internal Control for Encrypting Video Data - In one aspect, a video processing device includes a processor and a transmitter, for example implemented as separate integrated circuits on a printed circuit board. Pins on the processor are coupled to pins on the transmitter via a data channel, for example conductive leads on the printed circuit board. Video data is transmitted from the processor to the transmitter via this data channel, which is high speed enough to accommodate video data. The transmitter also includes an encryption engine used to encrypt the video data. Encryption control data, which determines the encryption to be applied, is transmitted from the processor to the transmitter over the same data channel as the video data. This is more secure than transmitting the encryption control data over a slower separate data channel, because the high speed video channel is harder to tamper with. | 04-14-2016 |
Patent application number | Description | Published |
20080252666 | DISPLAY APPARATUS AND METHOD FOR ADJUSTING BRIGHTNESS THEREOF - A display apparatus and a method for adjusting brightness thereof are provided. The display apparatus includes a panel unit which displays a video signal, a light emitting unit which provides the panel unit with a ray of light and causes the video signal to be visualized, a light emission control unit which controls the light emitting unit so that the ray of light is provided to each of local areas of the panel unit, and a panel control unit which compensates pixels of the video signal in each of local areas, to remove an artifact which is generated due to the ray of light provided to local areas of the panel unit. Because brightness of a screen is adjusted in each of local areas, contrast ratio is enhanced, and improved image quality is provided. | 10-16-2008 |
20090141049 | DISPLAY APPARATUS FOR COMPENSATING OPTICAL PARAMETER USING FORWARD VOLTAGE OF LED AND METHOD THEREOF - A display apparatus for compensating an optical parameter, and a display method thereof are disclosed, the display apparatus including a display, an optical source unit, a voltage detection unit which measures the forward voltage of an optical source, and a control unit which controls driving of the optical source unit using a forward voltage of the at least one optical source. Accordingly, the variation of optical parameter is accurately compensated, and the cost for fabricating a temperature sensor and the time for measuring the temperature are reduced. | 06-04-2009 |
20110116218 | DISPLAY APPARATUS - Disclosed is a display apparatus with an improved structure of its display unit and main body. The display apparatus includes: a display unit which includes a display connector and displays an image; and a main body which includes a power supply unit for supplying power to the display unit, an image processing unit for outputting image signals, and a main body connector which is directly or indirectly connected to the display connector in order to supply the power and the image signals output from the power supply unit and the image processing unit, respectively, to the display unit. | 05-19-2011 |
20110148869 | DISPLAY APPARATUS - A display apparatus in which a user can view a 3D image using shutter glasses is provided. The display apparatus, in which a user can view a three-dimensional (3D) image using shutter glasses, may include: a cover; a display module which is disposed in the cover and displays an image; and a transmitter which is disposed in the cover and transmits a synchronization signal to the shutter glasses to synchronize the image displayed by the display module with the shutter glasses. | 06-23-2011 |
20110164401 | BACKLIGHT APPARATUS AND DISPLAY APPARATUS INCLUDING THE SAME - A backlight apparatus includes a substrate which includes a plurality of layers. A plurality of light emitting modules are arranged on a top layer of the plurality of layers closest to a light guide panel, and a plurality of wires penetrates through the plurality of layers to electrically connect the light emitting modules and a plurality of driving units. Accordingly, the width of the substrate of an edge type backlight apparatus which can provide local dimming is reduced. Therefore, the display apparatus using the edge type backlight apparatus can be slim even if it is designed to provide local dimming. | 07-07-2011 |
20110248969 | LCD DISPLAY APPARATUS AND LCD DRIVING METHOD - A liquid crystal display (LCD) apparatus and an LCD driving method are provided. The LCD apparatus drives an LCD module by applying temperature compensation to change driving timing according to temperature of the LCD module. Accordingly, the LCD apparatus may reduce a cross-talk occurrence rate in low temperature. | 10-13-2011 |
20120268449 | DISPLAY APPARATUS - Disclosed is a display apparatus with an improved structure of its display unit and main body. The display apparatus includes: a display unit which includes a display connector and displays an image; and a main body which includes a power supply unit for supplying power to the display unit, an image processing unit for outputting image signals, and a main body connector which is directly or indirectly connected to the display connector in order to supply the power and the image signals output from the power supply unit and the image processing unit, respectively, to the display unit. | 10-25-2012 |
20130342788 | BACKLIGHT APPARATUS AND DISPLAY APPARATUS INCLUDING THE SAME - A backlight apparatus includes a substrate which includes a plurality of layers. A plurality of light emitting modules are arranged on a top layer of the plurality of layers closest to a light guide panel, and a plurality of wires penetrates through the plurality of layers to electrically connect the light emitting modules and a plurality of driving units. Accordingly, the width of the substrate of an edge type backlight apparatus which can provide local dimming is reduced. Therefore, the display apparatus using the edge type backlight apparatus can be slim even if it is designed to provide local dimming. | 12-26-2013 |
20150289390 | DISPLAY APPARATUS - Disclosed is a display apparatus with an improved structure of its display unit and main body. The display apparatus includes: a display unit which includes a display connector and displays an image; and a main body which includes a power supply unit for supplying power to the display unit, an image processing unit for outputting image signals, and a main body connector which is directly or indirectly connected to the display connector in order to supply the power and the image signals output from the power supply unit and the image processing unit, respectively, to the display unit. | 10-08-2015 |
20150350631 | DISPLAY APPARATUS WITH A 3D SYNCHRONIZATION SIGNAL TRANSMITTER DISPOSED THEREIN - A display apparatus in which a user can view a 3D image using shutter glasses is provided. The display apparatus, in which a user can view a three-dimensional (3D) image using shutter glasses, may include: a cover; a display module which is disposed in the cover and displays. an image; and a transmitter which is disposed in the cover and transmits a synchronization signal to the shutter glasses to synchronize the image displayed by the display module with the shutter glasses. | 12-03-2015 |
Patent application number | Description | Published |
20110255047 | DISPLAY APPARATUS INCLUDING TEMPERATURE COMPENSATION UNIT, DISPLAY MODULE APPLIED THEREIN, AND METHOD FOR CONTROLLING TEMPERATURE OF DISPLAY MODULE - A display apparatus, a display module applied to the display apparatus, and a method for controlling a temperature of the display module are provided. The display apparatus includes a temperature compensation unit for compensating for the temperature of a liquid crystal panel. | 10-20-2011 |
20120113079 | DISPLAY APPARATUS - Provided is a display apparatus including an image processing module and a display main body, wherein the image processing module includes: an image signal processor processing an image signal; a module terminal transmitting the processed image signal in a wired manner; and a module wireless communication unit transmitting wirelessly the processed image signal, and wherein the display main body includes: a main body terminal receiving the image signal from the module terminal which is detachably connected to the main body terminal; a main body wireless communication unit receiving the image signal from the module wireless communication unit; and a display unit displaying an image corresponding to the image signal; and a controller controlling the image signal to be transmitted selectively from the module terminal to the main body terminal or from the module wireless communication unit to the main body wireless communication unit. | 05-10-2012 |
20120127141 | DISPLAY DEVICE - A display device having an infrared receiver module. The display device includes a display part on which an image is displayed, a bezel part formed along an outer edge of the display part, an infrared receiving part provided on the bezel part, and the infrared receiver module disposed at a rear surface of the infrared receiving part and including an infrared sensor to receive an infrared signal and a plate-shaped printed circuit board on which the infrared sensor is mounted, and a distance from the outer edge of a side surface of the display part to a most distant portion of the infrared receiver module mounted on the printed circuit board in the sideward direction is shorter than a length from the outer edge of the side surface of the display part to a most distant portion of the printed circuit board. | 05-24-2012 |
20130113710 | DISPLAY APPARATUS AND CONTROL METHOD THEREOF - Exemplary embodiments include a wireless transmitter and wireless receiver. The wireless transmitter and wireless receiver wirelessly transmit and receive data, respectively. The wireless transmitter and the wireless receiver each include a controller which outputs a power mode changing control signal to a power supply unit and a communication unit in response to a wakeup event, wherein the power supply unit changes a power mode from a standby mode to a normal mode in response to the power mode changing control signal. Both the wireless transmitter and receiver include a transmitter which transmits the power mode changing control signal to the other. With this configuration, there are provided an apparatus and a control method thereof which enable a wireless transmission of multimedia and consumes minimal power when in a standby mode. | 05-09-2013 |
20130169620 | DISPLAY APPARATUS, GLASSES APPARATUS LINKED WITH DISPLAY APPARATUS AND CONTROLLING METHOD THEREOF - A display apparatus, glasses apparatus linked with the display apparatus, and control method thereof are provided. The glasses apparatus which is linked with the display apparatus alternately displays a plurality of content in image frame units includes: an input button, and a controller which performs a turn on operation when the input button is selected in a state where the glasses apparatus is turned off and which performs different control operations corresponding to a duration that the input button is pushed, a number of times the input button is pushed, or both the duration and the number of times the input button is pushed. | 07-04-2013 |
20130169625 | IMAGE PROCESSING APPARATUS, UPGRADE APPARATUS, DISPLAY SYSTEM INCLUDING THE SAME, AND CONTROL METHOD THEREOF - An image processing apparatus, upgrade apparatus, display system and control method are provided. The image processing apparatus includes a signal input unit; a first image processing unit which processes an input signal input by the signal input unit to output a first output signal; an upgrade apparatus connection unit connected to an upgrade apparatus which includes a second image processing unit; and a first controller which controls at least one of the input signal processed by the first image processing unit and the first output signal to be transmitted to the upgrade apparatus and processed by the second image processing unit if the upgrade apparatus is connected to the upgrade apparatus connection unit. | 07-04-2013 |
20130169652 | IMAGE PROCESSING APPARATUS, UPGRADE APPARATUS, DISPLAY SYSTEM INCLUDING THE SAME, AND CONTROL METHOD THEREOF - An image processing apparatus, upgrade apparatus, display system and control method are provided. The image processing apparatus includes a signal input unit; a first image processing unit which processes an input signal input by the signal input unit to output a first output signal; an upgrade apparatus connection unit connected to an upgrade apparatus which includes a second image processing unit; and a first controller which controls at least one of the input signal processed by the first image processing unit and the first output signal to be transmitted to the upgrade apparatus and processed by the second image processing unit if the upgrade apparatus is connected to the upgrade apparatus connection unit | 07-04-2013 |
20130169763 | DISPLAY APPARATUS, CONTROL METHOD THEREOF, AND INPUT APPARATUS USED IN THE SAME - A display apparatus and a method of controlling the same are provided. The display apparatus includes a plurality of reception units configured to receive a plurality of different contents, a signal processing unit configured to process each of the plurality of contents, an output unit configured to output contents processed in the signal processing unit, a remote controller signal reception unit configured to receive a selection signal from a remote controller, and, if the selection signal is received, a control unit configured to perform different control operations according to a current operation state of the display apparatus. | 07-04-2013 |
20130169767 | DISPLAY APPARATUS AND METHOD FOR CONTROLLING THEREOF - A display apparatus and a method for controlling thereof are provided. A display apparatus having a multi-view mode to concurrently provide different contents to different viewers includes a plurality of receivers operable in the multi-view mode to receive a plurality of different contents selected by multiple viewers, a video processor operable in the multi-view mode to process video data of the plurality of different contents received by the plurality of receivers; a video output which receives the video data processed by the video processor to display the plurality of different contents, an audio processor operable in the multi-view mode to process audio data corresponding to the selected contents, received by the receivers, and an audio output which outputs the processed audio data to a plurality of eyeglasses apparatuses for viewing the plurality of different contents, wherein a number of channels associated with the processed audio data output to the eyeglasses apparatus is different from a number of channels associated with the audio data received by the receivers. | 07-04-2013 |
20130169878 | APPARATUS AND METHOD FOR DISPLAYING - A display apparatus and method thereof are provided. The display apparatus may include a plurality of receiving units which receive a plurality of different contents, a signal processing unit which processes the contents received at the plurality of receiving units to construct a plurality of contents views, an output unit which displays each content view constructed at the signal processing unit, an input unit which receives a command to display an on-screen display (OSD), and a control unit which determines a content view to display OSD information from among the plurality of contents views, when an OSD display command is inputted, and an OSD processing unit which displays OSD information on the determined content view. | 07-04-2013 |
20130222400 | IMAGE PROCESSING APPARATUS, UPGRADE APPARATUS, DISPLAY SYSTEM INCLUDING THE SAME, AND CONTROL METHOD THEREOF - An image processing apparatus, upgrade apparatus, display system and control method are provided. The image processing apparatus includes a signal input unit; a first image processing unit which processes an input signal input by the signal input unit to output a first output signal; an upgrade apparatus connection unit connected to an upgrade apparatus which includes a second image processing unit; and a first controller which controls at least one of the input signal processed by the first image processing unit and the first output signal to be transmitted to the upgrade apparatus and processed by the second image processing unit if the upgrade apparatus is connected to the upgrade apparatus connection unit. | 08-29-2013 |
20150035958 | APPARATUS AND METHOD FOR CONCURRENTLY DISPLAYING MULTIPLE VIEWS - A display apparatus and method thereof are provided. The display apparatus may include a plurality of receiving units which receive a plurality of different contents, a signal processing unit which processes the contents received at the plurality of receiving units to construct a plurality of contents views, an output unit which displays each content view constructed at the signal processing unit, an input unit which receives a command to display an on-screen display (OSD), and a control unit which determines a content view to display OSD information from among the plurality of contents views, when an OSD display command is inputted, and an OSD processing unit which displays OSD information on the determined content view. | 02-05-2015 |
20150058885 | DISPLAY APPARATUS AND CONTROL METHOD THEREOF - A display apparatus and a method of controlling a display apparatus are disclosed. The display apparatus includes: a display configured to display an image based on a video signal; a sound output section configured to output a first sound based on a sound signal; a first sound receiver configured to receive a first mixed sound including the first sound and a second sound of a user; a second sound receiver which is spaced apart at a distance from the first sound receiver and is configured to receive a second mixed sound comprising the first sound and the second sound; and a controller configured to perform control in accordance with the second sound of the user, the second sound being acquired based on the first mixed sound and the second mixed sound. | 02-26-2015 |
Patent application number | Description | Published |
20120140869 | OUTPUT TIMING CONTROL CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME - An output timing control circuit of a semiconductor apparatus includes a delay amount counter block configured to count a delay amount of an output reset pulse signal based on an external clock signal and output a first counting code, wherein the delay amount counter block is configured to control the delay amount of the output reset pulse signal depending upon a frequency of the external clock signal; an operation block configured to subtract a code value of the first counting code from a code value of a data output delay code, and output a delay control code; and a phase control block configured to control a phase of a read command signal by the number of clocks of a DLL clock signal corresponding to a code value of the delay control code, and output an output enable flag signal. | 06-07-2012 |
20130106472 | INTEGRATED CIRCUIT | 05-02-2013 |
20130314135 | DELAY-LOCKED LOOP - A semiconductor apparatus includes a DLL clock generation unit configured to compare phases of a clock and a feedback clock, determine a delay time of a delay line, delay the clock by the delay time through the delay line, and generate a DLL clock; a delay detection unit configured to detect the delay time of the delay line and enable a delay detection signal when the delay time is greater than or equal to a predetermined time; and a power-down control unit configured to prevent the DLL clock generation unit from being reset when the delay detection signal is enabled and reset the DLL clock generation unit when the delay detection signal is disabled, in a self-refresh operation under a power-down mode. | 11-28-2013 |
20130321046 | POWER TRACKING CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - A semiconductor device having a power tracking circuit configured for activating a power tracking signal for a period corresponding to a period during which an external voltage retains a level lower than a level of a low power mode reference voltage if the external voltage retains the level lower than the level of the low power mode reference voltage for at least a preselected time. | 12-05-2013 |
20130329507 | OUTPUT ENABLE SIGNAL GENERATION CIRCUIT - An output enable signal generation circuit includes an output enable reset signal generation unit configured to enable an output enable reset signal in response to an external clock signal, a DLL locking signal, and a reset signal, an output enable reset signal delay unit configured to delay the output enable reset signal and output the delayed output enable reset signal, a counter unit configured to output the count of the external clock signal as a value in response to the output enable reset signal and the delayed output enable reset signal, a read command delay unit configured to delay a read command and output the delayed read command, and an output enable signal output unit configured to shift the delayed read command in synchronization with a DLL clock signal and output an output enable signal, according to control of CL and the count value. | 12-12-2013 |
20140062552 | DLL CIRCUIT AND DELAY-LOCKED METHOD USING THE SAME - A delay-locked loop (DLL) circuit having improved phase correction performance includes a variable delay unit configured to generate a DLL clock signal by delaying an input clock signal by a varied delay time in response to a delay control signal at timing corresponding to an update cycle signal, a delay model configured to generate a feedback clock signal by delaying the DLL clock signal for a predetermined delay time, a phase detection unit configured to output a result of the detection of the phase of the feedback clock signal based on a reference clock signal as the delay control signal, and an update cycle control unit configured to determine whether a cycle has been shifted or not in response to an external clock signal and the delay control signal and shift a cycle where the update cycle signal is generated based on a result of the determination. | 03-06-2014 |
20150187401 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus may include a clock buffer configured to receive an external clock signal, buffer the external clock signal in response to an activation control signal, and the clock buffer configured to output an internal clock signal in response to an activation control signal. The semiconductor memory apparatus may also include a delay-locked loop block configured to receive the internal clock signal outputted from the clock buffer and compare phases of the internal clock signal and a feedback clock signal, and responsively generate a delay-locked clock signal. The semiconductor memory apparatus may also include an operation control block configured to responsively generate the activation control signal which is received by the clock buffer in accordance with a result of comparing the phases of the internal clock signal and the feedback clock signal, in response to receiving a read signal. | 07-02-2015 |
20150213845 | SYSTEM USING MINIMUM OPERATION POWER AND POWER SUPPLY VOLTAGE SETTING METHOD OF MEMORY DEVICE - A system includes a memory device, a controller, and a power supply. The controller stores a write data in the memory device, and generates a voltage control signal by comparing a read data outputted from the memory device with the write data. The power supply controls a level of a power supply voltage supplied to the memory device in response to the voltage control signal. | 07-30-2015 |