Patent application number | Description | Published |
20100042765 | Dynamically Migrating Channels - In one embodiment, the present invention includes a method of determining a relative priority between a first agent and a second agent, and assigning the first agent to a first channel and the second agent to a second channel according to the relative priority. Depending on the currently programmed status of the channels, information stored in at least one of the channels may be dynamically migrated to another channel based on the assignments. Other embodiments are described and claimed. | 02-18-2010 |
20100281471 | METHODS AND APPARATUSES FOR COMPILER-CREATING HELPER THREADS FOR MULTI-THREADING - Methods and apparatuses for compiler-created helper thread for multi-threading are described herein. In one embodiment, exemplary process includes identifying a region of a main thread that likely has one or more delinquent loads, the one or more delinquent loads representing loads which likely suffer cache misses during an execution of the main thread, analyzing the region for one or more helper threads with respect to the main thread, and generating code for the one or more helper threads, the one or more helper threads being speculatively executed in parallel with the main thread to perform one or more tasks for the region of the main thread. Other methods and apparatuses are also described. | 11-04-2010 |
20100299479 | OBSCURING MEMORY ACCESS PATTERNS - For each memory location in a set of memory locations associated with a thread, setting an indication associated with the memory location to request a signal if data from the memory location is evicted from a cache; and in response to the signal, reloading the set of memory locations into the cache. | 11-25-2010 |
20110106522 | VIRTUAL PLATFORM FOR PROTOTYPING SYSTEM-ON-CHIP DESIGNS - A system to prototype a system-on-chip design is presented. In one embodiment, the system includes an electronic board comprising a logic device programmable to emulate system components. The system further comprises a processor to execute a virtual machine monitor which redirects an input/output request to the system components via an interconnect. | 05-05-2011 |
20110153529 | METHOD AND APPARATUS TO EFFICIENTLY GENERATE A PROCESSOR ARCHITECTURE MODEL - A method and apparatus for efficiently generating a processor architecture model that accurately predicts performance of the processor for minimizing simulation time are described. In one embodiment, the method comprises: identifying a performance benchmark of a processor; sampling a portion of a design space for the identified performance benchmark; simulating the sampled portion of the design space to generate training data; generating a processor performance model from the training data by modifying the training data to predict an entire design space; and predicting performance of the processor for the entire design space by executing the processor performance model. | 06-23-2011 |
20110153990 | SYSTEM, APPARATUS, AND METHOD FOR SUPPORTING CONDITION CODES - An apparatus is described having decode circuitry to decode a first instruction, wherein the first instruction indicates that a copy of a plurality of condition codes bits is to be copied from a first register to a second register. The apparatus also has first execution circuitry to copy a plurality of condition code bits from a first register to a second register. | 06-23-2011 |
20110258632 | Dynamically Migrating Channels - In one embodiment, the present invention includes a method of determining a relative priority between a first agent and a second agent, and assigning the first agent to a first channel and the second agent to a second channel according to the relative priority. Depending on the currently programmed status of the channels, information stored in at least one of the channels may be dynamically migrated to another channel based on the assignments. Other embodiments are described and claimed. | 10-20-2011 |
20110307876 | REGISTER MAPPING TECHNIQUES FOR EFFICIENT DYNAMIC BINARY TRANSLATION - Generally, the present disclosure provides a system and method for mapping registers from a system with more registers to a system with fewer registers. Regions may be formed that include one or more blocks of code with relatively frequent register accesses. The most frequently accessed source registers may be mapped to target registers. Each block in the region may be bounded by a prologue and at least one epilogue. The prologue may be configured to implement register mapping and the epilogue(s) may be configured to manage program flow from a block in the region to another block in the region or to a block not in the region. | 12-15-2011 |
20110314480 | Apparatus, System, And Method For Persistent User-Level Thread - Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof. | 12-22-2011 |
20130073835 | PRIMITIVES TO ENHANCE THREAD-LEVEL SPECULATION - A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed. | 03-21-2013 |
20130111194 | METHOD AND SYSTEM TO PROVIDE USER-LEVEL MULTITHREADING | 05-02-2013 |
20130205122 | INSTRUCTION SET ARCHITECTURE-BASED INTER-SEQUENCER COMMUNICATIONS WITH A HETEROGENEOUS RESOURCE - In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed. | 08-08-2013 |
20130219096 | PROGRAMMABLE EVENT DRIVEN YIELD MECHANISM WHICH MAY ACTIVATE OTHER THREADS - Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors. | 08-22-2013 |
20130219399 | MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION OF A PLURALITY OF INSTRUCTION SEQUENCERS - In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed. | 08-22-2013 |
20130275735 | Apparatus, System, And Method For Persistent User-Level Thread - Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof. | 10-17-2013 |
20140089942 | SYSTEM TO PROFILE AND OPTIMIZE USER SOFTWARE IN A MANAGED RUN-TIME ENVIRONMENT - Method, apparatus, and system for monitoring performance within a processing resource, which may be used to modify user-level software. Some embodiments of the invention pertain to an architecture to allow a user to improve software running on a processing resources on a per-thread basis in real-time and without incurring significant processing overhead. | 03-27-2014 |
20140208042 | PROVIDING HARDWARE SUPPORT FOR SHARED VIRTUAL MEMORY BETWEEN LOCAL AND REMOTE PHYSICAL MEMORY - In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed. | 07-24-2014 |
20140258757 | Methods And Apparatuses For Reducing Power Consumption Of Processor Switch Operations - Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions. | 09-11-2014 |
20150070368 | Instruction Set Architecture-Based Inter-Sequencer Communications With A Heterogeneous Resource - In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed. | 03-12-2015 |