Hong-June
Hong-June Kim, Seoul KR
Patent application number | Description | Published |
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20140149078 | PERFORMANCE MEASUREMENT UNIT, PROCESSOR CORE INCLUDING THE SAME AND PROCESS PROFILING METHOD - A performance measurement unit includes an event counter configured to record a counter value indicating a number of events occurring in a processor core, and a shadowed event counter configured to copy the counter value recorded in the event counter to the shadowed event counter. The performance measurement unit is configured to determine a number of effective events occurring in the processor core using the event counter and the shadowed event counter. Effective events correspond to events occurring when a selected process is executed. | 05-29-2014 |
20140149968 | DYNAMIC LIBRARY PROFILING METHOD AND DYNAMIC LIBRARY PROFILING SYSTEM - A dynamic library profiling method and a dynamic library profiling system including writing a first break point instruction at a start address of a dynamic library function, recording a first event count value that is a process performance management unit (PMU) count when a target process executes the first break point instruction, writing a second break point instruction to a return address of the dynamic library function, and calculating a PMU count generated in a processor core while the dynamic library function is executed, by comparing the recorded first event count value with a second event count value that is a process PMU count when the target process executes the second break point instruction, wherein the process PMU count is a cumulative value of PMU counts generated in the processor core while the target process is executed. | 05-29-2014 |
Hong-June Park, Seoul KR
Patent application number | Description | Published |
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20080272815 | DUTY CYCLE CORRECTION CIRCUITS INCLUDING A TRANSITION GENERATOR CIRCUIT FOR GENERATING TRANSITIONS IN A DUTY CYCLE CORRECTED SIGNAL RESPONSIVE TO AN INPUT SIGNAL AND A DELAYED VERSION OF THE INPUT SIGNAL AND METHODS OF OPERATING THE SAME - A duty cycle correction circuit is operated by maintaining a state of a duty cycle corrected signal, generating a first transition in the state of the duty cycle corrected signal responsive to an input signal, and generating a second transition in the state of the duty cycle corrected signal responsive to a delayed version of the input signal. | 11-06-2008 |
Hong-June Park, Kyungbuk KR
Patent application number | Description | Published |
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20080252340 | DELAY LOCKED LOOP (DLL) CIRCUITS HAVING AN EXPANDED OPERATION RANGE AND METHODS OF OPERATING THE SAME - Delay locked loop (DLL) circuits have a phase detector circuit that can detect a phase difference between an input clock signal and an output clock signal over a time period of 0T-2T. The delay applied to generate the output signal is adjusted based on the detected phase difference. A middle clock signal can be generated that has a phase that is between the input clock signal and the output clock signal. The phase detector circuit may be configured to detect the phase difference between the input clock signal and the output clock signal over the time period 0T-2T responsive to the middle clock signal. | 10-16-2008 |