Patent application number | Description | Published |
20120099392 | STORAGE DEVICE INCLUDING RESET CIRCUIT AND METHOD OF RESETTING THEREOF - A data storage device including a reset circuit and a method of resetting thereof includes a memory device to receive a driving voltage through a power terminal thereof, a voltage regulator to adjust an external voltage to provide the adjusted voltage to the power terminal of the memory device, and a reset circuit to discharge an enable terminal of the voltage regulator or the power terminal of the memory device according to a change of the external voltage. | 04-26-2012 |
20120102310 | MEMORY SYSTEM AND RESET METHOD THEREOF - Provided is a memory system that includes at least one nonvolatile memory device, a plurality of power lines and a plurality of power domains. The power lines receive a power source voltage. The power domains are respectively connected to the power lines. A reset signal is generated by using voltages which are detected from the power lines. The memory system and a reset method thereof detect the voltages of all power lines to generate a reset signal, and thus enhance reliability of data when a power is shut off. | 04-26-2012 |
20130097366 | STORAGE DEVICE AND USER DEVICE USING THE SAME - Provided are a storage device and a user device used by connecting to the user device. The storage device may include a nonvolatile memory and a control unit configured to control the nonvolatile memory. When write data is received from the host, the control unit outputs a first response signal including information indicating whether the write data is successfully received. When the write data is stored in the nonvolatile memory, the control unit outputs a second response signal including on whether the write data is successfully stored in the nonvolatile memory. Since the storage device does not require a program backup memory, it may be implemented in a small area. | 04-18-2013 |
20130151759 | STORAGE DEVICE AND OPERATING METHOD ELIMINATING DUPLICATE DATA STORAGE - A storage device includes storage media and a controller. The controller includes a de-duplication table that manages hash information for data stored in the storage media, and compares hash information for received write-requested data with hash information managed by the de-duplication table to determine whether the write-requested data is duplicate data. | 06-13-2013 |
20130151760 | NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF - Disclosed is a memory system which includes a nonvolatile memory device configured to store data information; and a memory controller configured to control the nonvolatile memory device. The memory controller provides the nonvolatile memory device with a program command sequence including program speed information according to an urgency level of an internally requested program operation. | 06-13-2013 |
20140149607 | STORAGE DEVICE, COMPUTING SYSTEM INCLUDING THE SAME AND DATA TRANSFERRING METHOD THEREOF - A data transfer method of a storage device which includes a host bus adaptor to communicate with an external host via a first interface and to communicate internally via a second interface is provided. The data transfer method may include issuing a write command and a read command to the host bus adaptor; performing a read direct memory access operation using the first interface in response to the write command and simultaneously performing a write direct memory access operation using the second interface in response to the read command; and generating frame information structure (FIS) sequences according to the second interface in response to the issued write command and the issued read command. The first interface may perform a full duplex data transfer and the second interface may perform a half-duplex data transfer. | 05-29-2014 |
20140149608 | MEMORY CONTROLLER AND OPERATING METHOD THEREOF - A memory controller is provided. The memory controller may comprise a first interface configured to provide an interface for communications with a host, and a second interface configured to communicate with the host through the first interface and to provide an interface for communications with a memory. The second interface may include an emulation engine configured to generate a Direct Memory Access (DMA) setup Frame Information Structure (FIS) including ready state information for data communications with the host in response to a command transferred from the host. The second interface may include a storage engine configured to access the host to fetch a physical region descriptor (PRD) before the DMA setup FIS is received from the emulation engine. | 05-29-2014 |
20140149692 | MEMORY CONTROLLER AND OPERATING METHOD OF MEMORY CONTROLLER - A memory controller and an operating method of a memory controller are provided. The operating method includes receiving a command issue from the external host; fetching a command corresponding to the command issue from a memory of the external host in response to the command issue; and controlling the external memory to perform the fetched command. The command is fetched immediately after the command issue is received independently from an execution of a previously fetched command. The memory controller includes a first interface which communicates with a host; and a second interface which communicates with the first interface and with an external memory and is recognized as storage by the host. The memory controller performs the operating method, | 05-29-2014 |
20140149706 | STORAGE DEVICE AND DATA TRANSFERING METHOD THEREOF - A data transferring method of a storage device is provided. The method may include transferring a first data to a first outbound area, transferring the first data sent to the first outbound area to a first area of a main memory corresponding to a first address programmed by an address translation unit, transferring a second data to a second outbound area in response to an indication that the address translation unit is to be reprogrammed, and transferring the second data sent to the second outbound area to the first outbound area. | 05-29-2014 |
20140149767 | MEMORY CONTROLLER AND OPERATING METHOD OF MEMORY CONTROLLER - A memory controller and an operating method of a memory controller are provided. The operating method includes detecting that a bus of an external host connected with the memory controller enters a first power saving mode; entering a second power saving mode of the memory controller according to a result of the detecting; detecting a wake-up process of the bus of the external host; and waking up the memory controller while the bus of the external host executes the wake-up process. The waking up of the memory controller is ended before the wake-up process of the bus of the external host is completed. | 05-29-2014 |
20140156880 | MEMORY CONTROLLER AND OPERATING METHOD THEREOF - A memory controller is provided which includes a host interface configured to provide an interface for communication with a host; a buffer memory configured to store user data and metadata of the user data; and a DMA controller configured to access the buffer memory to check the metadata and to provide user data corresponding to a logical block address requested from a host to the host interface according to the checking result. The metadata includes status information of the user data stored at the buffer memory. Before providing the host interface with user data corresponding to a first logical block address requested from the host, the DMA controller checks metadata of user data corresponding to a second logical block address requested from the host. | 06-05-2014 |