Patent application number | Description | Published |
20110261615 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM HAVING THE SAME, AND METHOD FOR OPERATING THE SEMICONDUCTOR DEVICE - A semiconductor device includes phase-change memory cells and an access circuit. The access circuit generates a plurality of bitwise comparison signals indicating different comparison events for respective write and read bit groups. At least a portion of the write data is then written to the phase-change memory cells according to a number of activated comparison signals for each comparison event, as well as according to a ratio of a set current pulse width and a reset current pulse width as applied to the of phase-change memory cells. | 10-27-2011 |
20110267876 | NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT - A nonvolatile memory device that employs a variable resistive element includes: a memory cell array having a plurality of memory cells; a first circuit block that is disposed at one side of the memory cell array and performs a first operation on the memory cells; a second circuit block that is disposed at the other side of the memory cell array and performs a second operation on the memory cells, wherein the second operation is different from the first operation; and a redundancy block that is disposed closer to the second circuit block than the first circuit block, and which compares a repair address of a repaired memory cell among the plurality of memory cells with an input address to then generate a redundancy control signal, and to supply the redundancy control signal to the first circuit block and the second circuit block. | 11-03-2011 |
20120173956 | MEMORY DEVICE USING ERROR CORRECTING CODE AND SYSTEM THEREOF - A memory device using error correcting code and a system including the same are provided. The memory system includes a memory device, and a storage block connected to the memory device. The memory device includes a normal cell region including a first plurality of memory cells for storing data bits, and an error correcting code (ECC) cell region including a second plurality of memory cells for storing first through mth sets of ECC bits. The storage block includes a third plurality of memory cells for storing first through nth sets of the ECC bits. Each memory cell of the first and second plurality of memory cells is a first type of memory cell and each memory cell of the third plurality of memory cells is a second type of memory cell different from the first type of memory cell. | 07-05-2012 |
20120182815 | Memory Devices Having Controllers that Divide Command Signals Into Two Signals and Systems Including Such Memory Devices - A memory device using error correcting code and a system including the same are provided. The memory device includes a memory cell array including a plurality of bit lines and a plurality of memory cells; an access block for accessing the memory cell array; and a controller block for receiving a first operation command signal, dividing the first operation command signal into at least two paths pulse signals corresponding to at least two paths, based on a pre-determined criterion, and then supplying the at least two path pulse signals to the access block. The access block operates based on an output signal of the controller block. | 07-19-2012 |
20120311407 | METHODS OF OPERATING NON-VOLATILE MEMORY DEVICES DURING WRITE OPERATION INTERRUPTION, NON-VOLATILE MEMORY DEVICES, MEMORIES AND ELECTRONIC SYSTEMS OPERATING THE SAME - A non-volatile memory device may operate by writing a portion of a new codeword to an address in the device that stores an old codeword, as part of a write operation. An interruption of the write operation can be detected before completion, which indicates that the address stores the portion of the new codeword and a portion of the old codeword. The portion of the old codeword can be combined with the portion of the new codeword to provide an updated codeword. Error correction bits can be generated using the updated codeword and the error correction bits can be written to the address. | 12-06-2012 |
20130010550 | Nonvolatile Memory Devices Including Selective RWW and RMW Decoding - A nonvolatile memory device is provided, which includes a memory core including a plurality of nonvolatile memory cells, a first read circuit that reads a first codeword from the memory core during a Read While Write (RWW) operation, a second read circuit that reads a second codeword from the memory core during a Read Modification Write (RMW) operation, and a common decoder that is shared by the first read circuit and the second read circuit and selectively decodes the first codeword or the second codeword. | 01-10-2013 |
20140245105 | SEMICONDUCTOR MEMORY DEVICES INCLUDING ERROR CORRECTION CIRCUITS AND METHODS OF OPERATING THE SEMICONDUCTOR MEMORY DEVICES - A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data. | 08-28-2014 |
20140247645 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD FOR REDUCING ACCESS LATENCY - A nonvolatile memory device comprises a memory core comprising a plurality of variable resistance memory cells, an input/output (I/O) circuit configured to receive a first packet signal and a second packet signal in sequence, the first and second packet signals collectively comprising information for a memory access operation, and further configured to initiate a core access operation upon decoding the first packet signal and to selectively continue or discontinue the core access operation upon decoding the second packet signal, and a read circuit configured to perform part of the core access operation in response to the first packet signal before the second packet signal is decoded. | 09-04-2014 |
20140247646 | NONVOLATILE MEMORY DEVICE HAVING MULTIPLE READ CIRCUITS AND USING VARIABLE RESISTIVE MATERIALS - A nonvolatile memory device includes a memory array having multiple nonvolatile memory cells, a first read circuit and a second read circuit. The first read circuit is configured to read first data from the memory array during a first read operation and to provide one or more protection signals indicating a victim period during the first read operation. The second read circuit is configured to read second data from the memory array during a second read operation and to provide one or more check signals indicating an aggressor period during the second read operation. | 09-04-2014 |
20140310481 | MEMORY SYSTEM - A memory system includes a memory controller to control a first memory device and a second memory device. The first and second memory devices are different in terms of at least one of physical distance from the memory controller, a manner of connection to the memory controller, error correction capability, or memory supply voltage. The first and second memory devices also have different latencies. | 10-16-2014 |
20140317469 | MEMORY DEVICE FOR PERFORMING ERROR CORRECTION CODE OPERATION AND REDUNDANCY REPAIR OPERATION - Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword. | 10-23-2014 |
20140317470 | MEMORY DEVICES THAT PERFORM MASKED WRITE OPERATIONS AND METHODS OF OPERATING THE SAME - A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells. | 10-23-2014 |
20140317471 | SEMICONDUCTOR MEMORY DEVICES INCLUDING SEPARATELY DISPOSED ERROR-CORRECTING CODE (ECC) CIRCUITS - A semiconductor memory device may comprise: at least one bank, each of the at least one bank including a plurality of memory cells; an error-correcting code (ECC) calculator configured to generate syndrome data for detecting an error bit from among parallel data bits read out from the plurality of memory cells of each of the at least one bank; an ECC corrector separated from the ECC calculator, the ECC corrector configured to correct the error bit from among the parallel data bits by using the syndrome data and configured to output error-corrected parallel data bits; and/or a data serializer configured to receive the error-corrected parallel data bits and configured to convert the error-corrected parallel data bits into serial data bits. | 10-23-2014 |
20140331006 | SEMICONDUCTOR MEMORY DEVICES - A semiconductor memory device includes a memory cell array, a data inversion/mask interface and a write circuit. The data inversion/mask interface receives a data block including a plurality of unit data, each of the plurality of unit data having a first data size, and the data inversion/mask interface selectively enables each data mask signal associated with each of the plurality of unit data based on a number of first data bits in a second data size of each unit data. The second data size is smaller than a first data size of the unit data. The write circuit receives the data block and performs a masked write operation that selectively writes each of the plurality of unit data in the memory cell array in response to the data mask signal. | 11-06-2014 |
20140331101 | SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHOD OF WRITING DATA IN THE SAME - In one embodiment, the semiconductor device includes a memory array and a control architecture configured to control reading data from and writing data to the memory array. The control architecture is configured to receive data and a codeword location in the memory array, select one or more data units in the received data based on a data mask, read a codeword currently stored at the codeword location in the memory array, error correct the read codeword to generate a corrected read codeword, form a new codeword from the selected data units of the received data and data units in the corrected read codeword that do not correspond to the selected data units, and write the new codeword to the memory array. | 11-06-2014 |