Patent application number | Description | Published |
20110180813 | INSULATED GATE BIPOLAR TRANSISTOR - An IGBT, which is capable of reducing on resistance by reducing channel mobility, includes: an n type substrate made of SiC and having a main surface with an off angle of not less than 50° and not more than 65° relative to a plane orientation of {0001}; a p type reverse breakdown voltage holding layer made of SiC and formed on the main surface of the substrate; an n type well region formed to include a second main surface of the reverse breakdown voltage holding layer; an emitter region formed in the well region to include the second main surface and including a p type impurity at a concentration higher than that of the reverse breakdown voltage holding layer; a gate oxide film formed on the reverse breakdown voltage holding layer; and a gate electrode formed on the gate oxide film. In a region including an interface between the well region and the gate oxide film, a high-concentration nitrogen region is formed to have a nitrogen concentration higher than those of the well region and the gate oxide film. | 07-28-2011 |
20110180814 | INSULATED GATE FIELD EFFECT TRANSISTOR - A MOSFET, which is capable of reducing on resistance by reducing channel mobility even when a gate voltage is high, includes: an n type substrate made of SiC and having a main surface with an off angle of 50°-65° relative to a {0001} plane; an n type reverse breakdown voltage holding layer made of SiC and formed on the main surface of the substrate; a p type well region formed in the reverse breakdown voltage holding layer distant away from a first main surface thereof; a gate oxide film formed on the well region; an n type contact region disposed between the well region and the gate oxide film; a channel region connecting the n type contact region and the reverse breakdown voltage holding layer; and a gate electrode disposed on the gate oxide film. In a region including an interface between the channel region and the gate oxide film, a high-concentration nitrogen region is formed. | 07-28-2011 |
20110260175 | SEMICONDUCTOR DEVICE - A silicon carbide layer is provided on a substrate, has a hexagonal single-crystal structure, and has a surface at which a depletion layer is formed. A protective film is insulative and provided on the silicon carbide layer to directly cover the surface. The surface thus directly covered with the protective film includes a portion having an off angle of not more than 10° relative to the {0-33-8} plane of the silicon carbide layer. This results in reduced leakage current flowing in an interface between the protective film and the semiconductor layer. | 10-27-2011 |
20110309376 | METHOD OF CLEANING SILICON CARBIDE SEMICONDUCTOR, SILICON CARBIDE SEMICONDUCTOR, AND SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of cleaning an SiC semiconductor capable of exhibiting an effect of cleaning an SiC semiconductor is provided. An SiC semiconductor and an SiC semiconductor device capable of achieving improved characteristics are provided. The method of cleaning an SiC semiconductor includes the steps of forming an oxide film on a surface of an SiC semiconductor (step S | 12-22-2011 |
20120018743 | SEMICONDUCTOR DEVICE - A MOSFET includes a silicon carbide substrate including a main surface having an off angle of not less than 50° and not more than 65° with respect to a {0001} plane, a buffer layer and a drift layer formed on the main surface, a gate oxide film formed on and in contact with the drift layer, and a p type body region of a p conductivity type formed in the drift layer to include a region in contact with the gate oxide film. The p type body region has a p type impurity density of not less than 5×10 | 01-26-2012 |
20120149175 | METHOD OF CLEANING SILICON CARBIDE SEMICONDUCTOR - A method of cleaning a SiC semiconductor includes the steps of forming an oxide film at the surface of a SiC semiconductor, and removing the oxide film. At the step of forming an oxide film, an oxide film is formed using ozone water having a concentration greater than or equal to 30 ppm. The forming step preferably includes the step of heating at least one of the surface of the SiC semiconductor and the ozone water. Thus, there can be obtained a method of cleaning a SiC semiconductor that can exhibit cleaning effect on the SiC semiconductor. | 06-14-2012 |
20120174944 | CLEANING METHOD FOR SILICON CARBIDE SEMICONDUCTOR AND CLEANING APPARATUS FOR SILICON CARBIDE SEMICONDUCTOR - A cleaning method for a SiC semiconductor includes the step of forming an oxide film on a front surface of a SiC semiconductor, and the step of removing the oxide film, and oxygen plasma is used in the step of forming the oxide film. Hydrogen fluoride may be used in the step of removing the oxide film. Thereby, a cleaning effect on the SiC semiconductor can be exhibited. | 07-12-2012 |
20120175638 | SEMICONDUCTOR DEVICE - A MOSFET includes: a silicon carbide substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; an active layer; a gate oxide film; a p type body region having p type conductivity and formed to include a region of the active layer, the region being in contact with the gate oxide film; an n | 07-12-2012 |
20120178259 | METHOD OF CLEANING SILICON CARBIDE SEMICONDUCTOR AND APPARATUS FOR CLEANING SILICON CARBIDE SEMICONDUCTOR - A method of cleaning an SiC semiconductor includes the steps of forming an oxide film on a surface of an SiC semiconductor and removing the oxide film. In the step of removing the oxide film, the oxide film is removed with halogen plasma or hydrogen plasma. In the step of removing the oxide film, fluorine plasma is preferably employed as halogen plasma. The SiC semiconductor can be cleaned such that good surface characteristics are achieved. | 07-12-2012 |
20120193643 | SEMICONDUCTOR DEVICE - A MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a p type body region in which an inversion layer is formed when the gate electrode is fed with a voltage. The inversion layer has an electron mobility μ dependent more strongly on an acceptor concentration N | 08-02-2012 |
20120208302 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - There is provided a method for manufacturing a SiC semiconductor device achieving improved performance. The method for manufacturing the SiC semiconductor device includes the following steps. That is, a SiC semiconductor is prepared which has a first surface having at least a portion into which impurities are implanted. By cleaning the first surface of the SiC semiconductor, a second surface is formed. On the second surface, a Si-containing film is formed. By oxidizing the Si-containing film, an oxide film constituting the SiC semiconductor device is formed. | 08-16-2012 |
20120208368 | METHOD AND APPARATUS FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of manufacturing an SiC semiconductor device includes the steps of forming a first oxide film on a first surface of an SiC semiconductor, removing the first oxide film, and forming a second oxide film constituting the SiC semiconductor device on a second surface exposed as a result of removal of the first oxide film in the SiC semiconductor. Between the step of removing the first oxide film and the step of forming a second oxide film, the SiC semiconductor is arranged in an atmosphere cut off from an ambient atmosphere. | 08-16-2012 |
20120214309 | METHOD AND APPARATUS OF FABRICATING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of fabricating a SiC semiconductor device includes the steps of preparing a silicon carbide semiconductor including a first surface having impurities implanted at least partially, forming a second surface by dry etching the first surface of the silicon carbide semiconductor using gas including hydrogen gas, and forming an oxide film constituting the silicon carbide semiconductor device on the second surface. | 08-23-2012 |
20120228640 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes: a substrate having a main surface; and a silicon carbide layer formed on the main surface of the substrate and including a side surface inclined relative to the main surface. The side surface substantially includes a {03-3-8} plane. The side surface includes a channel region. | 09-13-2012 |
20120235165 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a substrate made of silicon carbide and having a main surface having an off angle of not less than −° and not more than +5° relative to a (0-33-8) plane in a <01-10> direction; a p type layer made of silicon carbide and formed on the main surface of the substrate by means of epitaxial growth; and an oxide film formed in contact with a surface of the p type layer. A maximum value of nitrogen atom concentration is 1×10 | 09-20-2012 |
20120248461 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide layer is epitaxially formed on a main surface of a substrate. The silicon carbide layer is provided with a trench having a side wall inclined relative to the main surface. The side wall has an off angle of not less than 50° and not more than 65° relative to a {0001} plane. A gate insulating film is provided on the side wall of the silicon carbide layer. The silicon carbide layer includes: a body region having a first conductivity type and facing a gate electrode with the gate insulating film being interposed therebetween; and a pair of regions separated from each other by the body region and having a second conductivity type. The body region has an impurity density of 5×10 | 10-04-2012 |
20120248462 | IGBT - An IGBT includes a groove provided in a silicon carbide semiconductor layer, a body region of a first conductivity type provided in the silicon carbide semiconductor layer, and an insulating film covering at least a sidewall surface of the groove, the sidewall surface of the groove being a surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, the sidewall surface of the groove including a surface of the body region, the insulating film being in contact with at least the surface of the body region at the sidewall surface of the groove, and a first conductivity type impurity concentration in the body region being 5×10 | 10-04-2012 |
20120280255 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - An MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a body region where an inversion layer is formed at a region in contact with the gate oxide film by application of voltage to the gate electrode. The body region includes a low concentration region arranged at a region where an inversion layer is formed, and containing impurities of low concentration, and a high concentration region adjacent to the low concentration region in the carrier mobile direction in the inversion layer, arranged in a region where the inversion layer is formed, and containing impurities higher in concentration than in the low concentration region. | 11-08-2012 |
20120286291 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A silicon carbide semiconductor device having excellent electrical characteristics including channel mobility and a method for manufacturing the same are provided. The method for manufacturing a silicon carbide semiconductor device includes: an epitaxial layer forming step of preparing a semiconductor film of silicon carbide; a gate insulating film forming step of forming an oxide film on a surface of the semiconductor film; a nitrogen annealing step of performing heat treatment on the semiconductor film on which the oxide film is formed, in a nitrogen-containing atmosphere; and a post heat treatment step of performing, after the nitrogen annealing step, post heat treatment on the semiconductor film on which the oxide film is formed, in an atmosphere containing an inert gas. The heat treatment temperature in the post heat treatment step is higher than that in the nitrogen annealing step and lower than a melting point of the oxide film. | 11-15-2012 |
20120305943 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A drift layer has a thickness direction throughout which a current flows and has an impurity concentration N | 12-06-2012 |
20120309174 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a MOSFET includes the steps of preparing a silicon carbide substrate, forming an active layer on the silicon carbide substrate, forming a gate oxide film on the active layer, forming a gate electrode on the gate oxide film, forming a source contact electrode on the active layer, and forming a source interconnection on the source contact electrode. The step of forming the source interconnection includes the steps of forming a conductor film on the source contact electrode and processing the conductor film by etching the conductor film with reactive ion etching. Then, the method of manufacturing a MOSFET further includes the step of performing annealing of heating the silicon carbide substrate to a temperature not lower than 50° C. after the step of processing the conductor film. | 12-06-2012 |
20120313112 | SEMICONDUCTOR DEVICE - A MOSFET includes a silicon carbide substrate, a drift layer made of silicon carbide and including a main surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, and a gate oxide film formed on and in contact with the main surface of the drift layer. The drift layer includes a p type body region formed to include a region in contact with the gate oxide film. The p type body region has an impurity density of 5×10 | 12-13-2012 |
20120326166 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A substrate has a surface made of a semiconductor having a hexagonal single-crystal structure of polytype 4H. The surface of the substrate is constructed by alternately providing a first plane having a plane orientation of (0-33-8), and a second plane connected to the first plane and having a plane orientation different from the plane orientation of the first plane. A gate insulating film is provided on the surface of the substrate. A gate electrode is provided on the gate insulating film. | 12-27-2012 |
20130062629 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A substrate is provided with a main surface having an off angle of 5° or smaller relative to a reference plane. The reference plane is a {000-1} plane in the case of hexagonal system and is a {111} plane in the case of cubic system. A silicon carbide layer is epitaxially formed on the main surface of the substrate. The silicon carbide layer is provided with a trench having first and second side walls opposite to each other. Each of the first and second side walls includes a channel region. Further, each of the first and second side walls substantially includes one of a {0-33-8} plane and a {01-1-4} plane in the case of the hexagonal system and substantially includes a {100} plane in the case of the cubic system. | 03-14-2013 |
20130065384 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A mask layer is formed on a silicon carbide layer by a deposition method. The mask layer is patterned. A gate trench having a side wall is formed by removing a portion of the silicon carbide layer by etching using the patterned mask layer as a mask. A gate insulating film is formed on the side wall of the gate trench. A gate electrode is formed on the gate insulating film. The silicon carbide layer has one of hexagonal and cubic crystal types, and the side wall of the gate trench substantially includes one of a{0-33-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type. | 03-14-2013 |
20130075758 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A MOSFET includes a semiconductor substrate having a trench formed in a main surface, a gate oxide film, a gate electrode, and a source interconnection. A semiconductor substrate includes an n-type drift layer and a p-type body layer. The trench is formed to penetrate the body layer and to reach the drift layer. The trench includes an outer peripheral trench arranged to surround an active region when viewed two-dimensionally. On the main surface opposite to the active region when viewed from the outer peripheral trench, a potential fixing region where the body layer is exposed is formed. The source interconnection is arranged to lie over the active region when viewed two-dimensionally. The potential fixing region is electrically connected to the source interconnection. | 03-28-2013 |
20130075759 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A first layer has n type conductivity. A second layer is epitaxially formed on the first layer and having p type conductivity. A third layer is on the second layer and having n type conductivity. ND is defined to represent a concentration of a donor type impurity. NA is defined to represent a concentration of an acceptor type impurity. D | 03-28-2013 |
20130078771 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A collector layer having p type is formed on a silicon carbide substrate having n type. A drift layer having n type is formed on a top surface side of the collector layer. A body region provided on the drift layer and having p type, and an emitter region provided on the body region to be separated from the drift layer by the body region and having n type are formed. A bottom surface side of the collector layer is exposed by removing the silicon carbide substrate. | 03-28-2013 |
20130099251 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - When viewed in a plan view, a termination region (TM) surrounds an element region (CL). A first side of a silicon carbide substrate (SB) is thermally etched to form a side wall (ST) and a bottom surface (BT) in the silicon carbide substrate (SB) at the termination region (TM). The side wall (ST) has a plane orientation of one of {0-33-8} and {0-11-4}. The bottom surface (BT) has a plane orientation of {000-1}. On the side wall (ST) and the bottom surface (BT), an insulating film ( | 04-25-2013 |
20130119407 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes the steps of: preparing a substrate made of silicon carbide; forming, in the substrate, a trench opened on one main surface side of the substrate; and forming an oxide film in a region including a surface of the trench. In the step of forming the oxide film, the substrate is heated at a temperature of not less than 1250° C. in an atmosphere containing oxygen. | 05-16-2013 |
20130134442 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A MOSFET includes: a substrate provided with a trench having a side wall surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; an oxide film; and a gate electrode. The substrate includes a source region, a body region, and a drift region formed to sandwich the body region between the source region and the drift region. The source region and the body region are formed by means of ion implantation. The body region has an internal region sandwiched between the source region and the drift region and having a thickness of 1 μm or smaller in a direction perpendicular to a main surface thereof. The body region has an impurity concentration of 3×10 | 05-30-2013 |
20130153926 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A MOSFET includes: a substrate made of silicon carbide and having a first trench and a second trench formed therein, the first trench having an opening at the main surface side, the second trench having an opening at the main surface side and being shallower than the first trench; a gate insulating film; a gate electrode; and a source electrode disposed on and in contact with a wall surface of the second trench. The substrate includes a source region, a body region, and a drift region. The first trench is formed to extend through the source region and the body region and reach the drift region. The second trench is formed to extend through the source region and reach the body region. | 06-20-2013 |
20130161619 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A silicon carbide substrate includes: an n type drift layer having a first surface and a second surface opposite to each other; a p type body region provided in the first surface of the n type drift layer; and an n type emitter region provided on the p type body region and separated from the n type drift layer by the p type body region. A gate insulating film is provided on the p type body region so as to connect the n type drift layer and the n type emitter region to each other. A p type Si collector layer is directly provided on the silicon carbide substrate to face the second surface of the n type drift layer. | 06-27-2013 |
20130181229 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A MOSFET includes: a substrate having a first trench formed therein, the first trench opening on a side of one main surface; a gate insulating film; and a gate electrode. The substrate includes an n type source region, a p type body region, an n type drift region, and a p type deep region making contact with the body region and extending to a region deeper than the first trench. The first trench is formed such that a distance between the wall surface and the deep region increases with increasing distance from the main surface of the substrate. | 07-18-2013 |
20130183820 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide layer is thermally etched by supplying the silicon carbide layer with a process gas that can chemically react with silicon carbide, while heating the silicon carbide layer. With this thermal etching, a carbon film is formed on the silicon carbide layer. Heat treatment is provided to the silicon carbide layer to diffuse carbon from the carbon film into the silicon carbide layer. | 07-18-2013 |
20130193447 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes an insulation film, and a silicon carbide layer having a surface covered with the insulation film. The surface includes a first region. The first region has a first plane orientation at least partially. The first plane orientation is any of a (0-33-8) plane, (30-3-8) plane, (-330-8) plane, (03-3-8) plane, (-303-8) plane, and (3-30-8) plane. | 08-01-2013 |
20130270576 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device has a planar layout configured by periodically arranging unit cells. The unit cells include valid cells and invalid cells. Each of the valid cells has a switchable channel surface. The invalid cells are to relax electric field in the valid cells. At least one of the valid cells is disposed between adjacent ones of the invalid cells. | 10-17-2013 |
20130306986 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide substrate includes a first layer of a first conductivity type, a second layer of a second conductivity type provided on the first layer, and a third layer provided on the second layer and doped with an impurity for providing the first conductivity type. The silicon carbide substrate has a trench formed through the third layer and the second layer to reach the first layer. The first layer has a concentration peak of the impurity in a position away from the trench in the first layer. As a result, a silicon carbide semiconductor device having an electric field relaxation structure that can be readily formed is provided. | 11-21-2013 |
20130306987 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A first layer is of a first conductivity type. A second layer is provided on the first layer and is of a second conductivity type. A third layer is provided on the second layer and isolated from the first layer by the second layer, and is of the first conductivity type. A trench is formed through the third layer and the second layer to reach the first layer. The first layer includes a relaxation region sandwiching a gate insulating film between itself and a gate electrode. The relaxation region is doped with a first impurity for providing the first conductivity type. The relaxation region is also doped with a second impurity for providing the second conductivity type in a concentration lower than that of the first impurity. As a result, an electric field relaxation structure for improving the breakdown voltage can be readily formed. | 11-21-2013 |
20130307061 | SEMICONDUCTOR DEVICE - The substrate is made of a compound semiconductor, and has a recess, which opens at one main surface and has side wall surfaces when viewed in a cross section along a thickness direction. The gate insulating film is disposed on and in contact with each of the side wall surfaces. The substrate includes a source region having first conductivity type and disposed to be exposed at the side wall surface; and a body region having second conductivity type and disposed in contact with the source region at a side opposite to the one main surface so as to be exposed at the side wall surface, when viewed from the source region. The recess has a closed shape when viewed in a plan view. The side wall surfaces provide an outwardly projecting shape in every direction when viewed from an arbitrary location in the recess. | 11-21-2013 |
20130307065 | SEMICONDUCTOR DEVICE - The substrate is made of a compound semiconductor and has a plurality of first recesses, each of which opens at one main surface thereof and has a first side wall surface. The gate insulating film is disposed on and in contact with the first side wall surface. The gate electrode is disposed on and in contact with the gate insulating film. The substrate include: a source region having first conductivity type and disposed to face itself with a first recess interposed therebetween, when viewed in a cross section along the thickness direction; and a body region having second conductivity type and disposed to face itself with the first recess interposed therebetween. Portions of the source region facing each other are connected to each other in a region interposed between the first recess and another first recess adjacent to the first recess, when viewed in a plan view. | 11-21-2013 |
20140027784 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A drift layer forms a first main surface of a silicon carbide layer and has a first conductivity type. A source region is provided to be spaced apart from the drift layer by a body region, forms a second main surface, and has the first conductivity type. A relaxing region is provided within the drift layer and has a distance L | 01-30-2014 |
20140042453 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first heating step of heating the silicon carbide substrate in an atmosphere of oxygen is performed. A second heating step of heating the silicon carbide substrate to a temperature of 1300° C. or more and 1500° C. or less in an atmosphere of gas containing nitrogen atoms or phosphorus atoms is performed after the first heating step. A third heating step of heating the silicon carbide substrate in an atmosphere of a first inert gas is performed after the second heating step. Thus, the silicon carbide semiconductor device in which threshold voltage variation is small, and a method for manufacturing the same can be provided. | 02-13-2014 |
20140042460 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide substrate has a first surface and a second surface, and includes a first region and a third region each having first conductivity type, as well as a second region and a fourth region each having second conductivity type. The third region surrounds the second region on the second surface. The fourth region has an impurity concentration higher than that of the second region, is in contact with the second region, and surrounds the third region on the second surface. A first main electrode is provided on the first surface. A second main electrode is in contact with each of the third and fourth regions. A gate insulating film is provided on the second region. | 02-13-2014 |
20140061671 | WIDE GAP SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A wide gap semiconductor device includes a substrate and a Schottky electrode. The substrate formed of a wide gap semiconductor material has a main face, and includes a first-conductivity-type region and a second-conductivity-type region. The Schottky electrode is arranged adjoining the main face of the substrate. At the substrate, there is foamed a trench having a side face continuous with the main face and a bottom continuous with the side face. The Schottky electrode adjoins the first-conductivity-type region at the side face of the trench and the main face, and adjoins the second-conductivity-type region at the bottom of the trench. The side face of the trench is inclined relative to the main face of the substrate. | 03-06-2014 |
20140070233 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A gate insulating film is provided on a trench. The gate insulating film has a trench insulating film and a bottom insulating film. The trench insulating film covers each of a side wall and a bottom portion. The bottom insulating film is provided on the bottom portion with a trench insulating film being interposed therebetween. The bottom insulating film has a carbon atom concentration lower than that of the trench insulating film. The gate electrode is in contact with a portion of the trench insulating film on the side wall. Accordingly, a low threshold voltage and a large breakdown voltage can be attained. | 03-13-2014 |
20140073121 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A MOSFET includes a semiconductor substrate having a trench formed in a main surface, a gate oxide film, a gate electrode, and a source interconnection. A semiconductor substrate includes an n-type drift layer and a p-type body layer. The trench is formed to penetrate the body layer and to reach the drift layer. The trench includes an outer peripheral trench arranged to surround an active region when viewed two-dimensionally. On the main surface opposite to the active region when viewed from the outer peripheral trench, a potential fixing region where the body layer is exposed is formed. The source interconnection is arranged to lie over the active region when viewed two-dimensionally. The potential fixing region is electrically connected to the source interconnection. | 03-13-2014 |
20140162439 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide layer is epitaxially formed on a main surface of a substrate. The silicon carbide layer is provided with a trench having a side wall inclined relative to the main surface. The side wall has an off angle of not less than 50° and not more than 65° relative to a {0001} plane. A gate insulating film is provided on the side wall of the silicon carbide layer. The silicon carbide layer includes: a body region having a first conductivity type and facing a gate electrode with the gate insulating film being interposed therebetween; and a pair of regions separated from each other by the body region and having a second conductivity type. The body region has an impurity density of 5×10 | 06-12-2014 |
20140197422 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes a silicon carbide substrate. The silicon carbide substrate is composed of an element region provided with a semiconductor element portion and a termination region surrounding the element region as viewed in a plan view. The semiconductor element portion includes a drift region having a first conductivity type. The termination region includes a first electric field relaxing region contacting the element region and having a second conductivity type different from the first conductivity type, and a second electric field relaxing region arranged outside the first electric field relaxing region as viewed in the plan view, having the second conductivity type, and spaced from the first electric field relaxing region. A ratio calculated by dividing a width of the first electric field relaxing region by a thickness of the drift region is not less than 0.5 and not more than 1.83. | 07-17-2014 |
20140252374 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A first drift layer has a first surface facing a first electrode and electrically connected to a first electrode, and a second surface opposite to the first surface. The first drift layer has an impurity concentration N | 09-11-2014 |
20150179765 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - An MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a body region where an inversion layer is formed at a region in contact with the gate oxide film by application of voltage to the gate electrode. The body region includes a low concentration region arranged at a region where an inversion layer is formed, and containing impurities of low concentration, and a high concentration region adjacent to the low concentration region in the carrier mobile direction in the inversion layer, arranged in a region where the inversion layer is formed, and containing impurities higher in concentration than in the low concentration region. | 06-25-2015 |
20150214353 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes an element region and a guard ring region. A semiconductor element is provided in the element region. The guard ring region surrounds the element region in a plan view and has a first conductivity type. The semiconductor element includes a drift region having a second conductivity type different from the first conductivity type. The guard ring region includes a linear region and a curvature region continuously connected to the linear region. A value obtained by dividing a radius of curvature of an inner circumference portion of the curvature region by a thickness of the drift region is not less than 5 and not more than 10. Accordingly, there can be provided a silicon carbide semiconductor device capable of improving a breakdown voltage while suppressing decrease of on-state current. | 07-30-2015 |
20150263115 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A silicon carbide substrate includes a first impurity region, a well region in contact with the first impurity region, and a second impurity region separated from the first impurity region by the well region. A first main surface includes a first region in contact with a channel region, and a second region different from the first region. A silicon-containing material is formed on the second region. A first silicon dioxide region is formed on the first region. A second silicon dioxide region is formed by oxidizing the silicon-containing material. A gate runner is electrically connected to a gate electrode and formed in a position facing the second silicon dioxide region. Consequently, a silicon carbide semiconductor device capable of achieving improved insulation performance between the gate runner and the substrate while the surface roughness of the substrate is suppressed, and a method of manufacturing the same can be provided. | 09-17-2015 |
20150279926 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - Each of first to third impurity regions of a silicon carbide substrate has a portion located on a flat surface of a first main surface. On the flat surface, a gate insulating film connects the first and third impurity regions to each other. On the flat surface, a first main electrode is in contact with the third impurity region. A second main electrode is provided on a second main surface. A side wall insulating film covers a side wall surface of the first main surface. The side wall surface is inclined by not less than 50° and not more than 80° relative to a {000-1} plane. In this way, a leakage current is suppressed in a silicon carbide semiconductor device. | 10-01-2015 |
20150287817 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A first portion of a silicon carbide substrate having an impurity of a first conductivity type is disposed deeper than a first depth position. A second portion is disposed to extend from the first depth position to a second depth position shallower than the first depth position. A third portion is disposed to extend from the second depth position to a main surface. The second portion has a second impurity concentration higher than a first impurity concentration of the first portion. The third portion has a third impurity concentration not less than the first impurity concentration and less than the second impurity concentration. A body region having an impurity of a second conductivity type has an impurity concentration peak at a depth position shallower than the first depth position and deeper than the second depth position. | 10-08-2015 |
20150295048 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes a silicon carbide layer, a body region, a source region, a gate insulating film, a gate electrode, a source electrode, a first impurity region, and a second impurity region. The second impurity region is disposed within the silicon carbide layer so as to connect the body region and the first impurity region to each other, and has a second conductivity type. An impurity concentration in the second impurity region is equal to or higher than an impurity concentration in the silicon carbide layer and equal to or lower than a lower limit of an impurity concentration in the body region. | 10-15-2015 |
20150295095 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A first main surface of a silicon carbide substrate has a flat surface located in an element portion and a side wall surface located in a termination portion. The silicon carbide substrate has an impurity layer having a portion located at each of the flat surface of the first main surface and a second main surface. On the flat surface, a Schottky electrode is in contact with the impurity layer. On the second main surface, a counter electrode is in contact with the impurity layer. An insulating film covers the side wall surface. The side wall surface is inclined by not less than 50° and not more than 80° relative to a {000-1} plane. This suppresses the leakage current of a silicon carbide semiconductor device. | 10-15-2015 |
20150303266 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device has a silicon carbide substrate, a gate insulating film, and a gate electrode. Silicon carbide substrate includes a first impurity region having a first conductivity type, a well region being in contact with the first impurity region and having a second conductivity type which is different from the first conductivity type, and a second impurity region separated from the first impurity region by the well region and having the first conductivity type. The gate insulating film is in contact with the first impurity region and the well region. The gate electrode is in contact with the gate insulating film and is arranged opposite to the well region with respect to the gate insulating film. A specific on-resistance at a voltage which is half a gate driving voltage applied to the gate electrode is smaller than twice the specific on-resistance at the gate driving voltage. | 10-22-2015 |
20150311076 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A silicon carbide substrate including a first impurity region, a well region, and a second impurity region separated from the first impurity region by the well region is prepared. A silicon dioxide layer is formed in contact with the first impurity region and the well region. A gate electrode is formed on the silicon dioxide layer. A silicon-containing material is formed on the first impurity region. The silicon-containing material is oxidized. The silicon dioxide layer includes a first silicon dioxide region on the first impurity region and a second silicon dioxide region on the well region. The thickness of the first silicon dioxide region is greater than the thickness of the second silicon dioxide region. Consequently, a silicon carbide semiconductor device capable of achieving improved switching characteristics while suppressing a decrease in drain current, and a method of manufacturing the same can be provided. | 10-29-2015 |
20150325657 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first heating step of heating the silicon carbide substrate in an atmosphere of oxygen is performed. A second heating step of heating the silicon carbide substrate to a temperature of 1300° C. or more and 1500° C. or less in an atmosphere of gas containing nitrogen atoms or phosphorus atoms is performed after the first heating step. A third heating step of heating the silicon carbide substrate in an atmosphere of a first inert gas is performed after the second heating step. Thus, the silicon carbide semiconductor device in which threshold voltage variation is small, and a method for manufacturing the same can be provided. | 11-12-2015 |
20150340443 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes a silicon carbide layer, an element region including a semiconductor element portion formed in the silicon carbide layer, a JTE region (first electric field relaxing region), an insulating film disposed on a first main surface and covering the JTE region, and a pad electrode electrically connected to the JTE region. The pad electrode includes an extension portion extending from an end of the JTE region close to the element region in a peripheral direction from the element region toward the JTE region, the extension portion being disposed on the insulating film. The extension portion overlies at least a portion of the JTE region. | 11-26-2015 |
20150372092 | SEMICONDUCTOR DEVICE - A MOSFET includes a silicon carbide substrate including a main surface having an off angle with respect to a {0001} plane and a source electrode formed in contact with the main surface. A base surface is exposed at at least a part of a contact interface of the silicon carbide substrate with the source electrode. With such a construction, the MOSFET achieves suppressed variation in threshold voltage. | 12-24-2015 |
20150372128 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A silicon carbide film includes a first range having a first breakdown voltage holding layer, a charge compensation region, a first junction terminal region, and a first guard ring region. The silicon carbide film includes a second range having a second breakdown voltage holding layer, a channel forming region, and a source region. The first and second breakdown voltage holding layers constitutes a breakdown voltage holding region having a thickness in an element portion. When voltage is applied to attain a maximum electric field strength of 0.4 MV/cm or more in the breakdown voltage holding region during an OFF state, a maximum electric field strength in the second range within the element portion is configured to be less than ⅔ of a maximum electric field strength in the first range. | 12-24-2015 |
20160027878 | SILICON CARBIDE SEMICONDUCTOR DEVICE - There is provided a silicon carbide semiconductor device allowing for suppression of breakage of an element upon short circuit of load. A MOSFET includes a silicon carbide layer, a gate insulating film, a gate electrode, a source electrode, and a drain electrode. The silicon carbide layer includes a drift region, a body region, and a source region. The MOSFET is configured such that a relational expression of n<−0.02R | 01-28-2016 |
20160027910 | SILICON CARBIDE SEMICONDUCTOR DEVICE - There is provided a silicon carbide semiconductor device having an improved switching characteristic. A MOSFET includes a silicon carbide layer, a gate insulating film, a gate electrode, and a source electrode. The silicon carbide layer includes a drift region, a body region, and a contact region. The source electrode is in contact with the contact region in a main surface. The MOSFET is configured such that contact resistance of the source electrode with respect to the contact region is not less than 1×10 | 01-28-2016 |
20160071949 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide semiconductor device includes the following steps. When viewed in a direction perpendicular to a main surface, a silicon carbide substrate has a connection region provided to include an end portion of one side, an apex of a first body region nearest to the end portion, and an apex of a second body region nearest to the end portion, the connection region being electrically connected to both the first body region and the second body region, the connection region having the second conductivity type. When viewed in a direction parallel to the main surface, the first drift region and the second drift region are provided between a gate insulating film and the connection region. The connection region, the first body region, and the second body region are formed by ion implantation. | 03-10-2016 |
20160079349 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes a silicon carbide layer, an element region including a semiconductor element portion formed in the silicon carbide layer, a JTE region (first electric field relaxing region), an insulating film disposed on a first main surface and covering the JTE region, and a pad electrode electrically connected to the JTE region. The pad electrode includes an extension portion extending from an end of the JTE region close to the element region in a peripheral direction from the element region toward the JTE region, the extension portion being disposed on the insulating film. The extension portion overlies at least a portion of the JTE region. | 03-17-2016 |
20160086799 | Method of Producing Silicon Carbide Epitaxial Substrate, Silicon Carbide Epitaxial Substrate, and Silicon Carbide Semiconductor Device - A method of producing a silicon carbide epitaxial substrate includes steps of: preparing a silicon carbide substrate; and forming a silicon carbide layer on the silicon carbide substrate. In this production method, in the step of forming the silicon carbide layer, a step of growing an epitaxial layer and a step of polishing a surface of the epitaxial layer are repeated twice or more. | 03-24-2016 |
20160087032 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide semiconductor device includes the steps of preparing a silicon carbide substrate having a first main surface and a second main surface located on a side opposite to the first main surface, forming an epitaxial layer on the first main surface, the epitaxial layer having a first conductivity type and having a third main surface located on a side opposite to a side on which the silicon carbide substrate is located, forming a trench, which includes side walls intersecting with the third main surface and a bottom portion connected to the side walls, in the epitaxial layer, widening an opening of the trench, and forming an embedded region, which has a second conductivity type different from the first conductivity type, in the trench. The epitaxial layer adjacent to the embedded region and the embedded region constitute a superjunction structure. | 03-24-2016 |
20160087065 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A gate insulating film is provided on a trench. The gate insulating film has a trench insulating film and a bottom insulating film. The trench insulating film covers each of a side wall and a bottom portion. The bottom insulating film is provided on the bottom portion with a trench insulating film being interposed therebetween. The bottom insulating film has a carbon atom concentration lower than that of the trench insulating film. The gate electrode is in contact with a portion of the trench insulating film on the side wall. Accordingly, a low threshold voltage and a large breakdown voltage can be attained. | 03-24-2016 |