Patent application number | Description | Published |
20090049348 | SEMICONDUCTOR STORAGE DEVICE - This semiconductor storage device comprises a test mode based on test data input from the outside. A test data register temporarily retains the test data, while a test code register temporarily retains a test code corresponding to the test data. A test-code-match detection circuit detects a match between a test code retained in the test code register and a desired test code to output a match signal. When the match signal is output, a control circuit outputs the test data retained in the test data register to the first one of a plurality of shift registers in a test data latch circuit. Further, the control circuit inputs the test data returned from the last one of the plurality of shift registers in the test data latch circuit. | 02-19-2009 |
20090300261 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a memory unit having a first and a second port and including plural banks; a bank address conversion circuit operative to convert a first bank address fed from external into a second bank address different from the first bank address and operative to supply the first bank address to one of the first and second ports and supply the second bank address to the other of the first and second ports; and a write data conversion circuit operative to convert input data fed from external into write data different from the input data and operative to supply the input data to one of the first and second ports and supply the converted write data to the other of the first and second ports. | 12-03-2009 |
20120057405 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device comprises a cell array, voltage generation circuits, and a control circuit. The cell array comprises memory cell strings. The voltage generation circuits are arranged below the cell array. Each of the memory cell strings comprises a semiconductor layer, control gates, and memory cell transistors. The semiconductor layer comprises a pair of pillar portions, and a connecting portion. The control gates intersect the pillar portion. The memory cell transistors are formed at intersections of the pillar portion and the control gates. In a write operation and a read operation, the control circuit does not drive voltage generation circuits which give noise to memory cell strings as a write target and a read target, and drives voltage generation circuits which do not give noise to the memory cell strings as the write target and the read target. | 03-08-2012 |
20120069655 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory string is configured by a plurality of memory transistors and a spare memory transistor connected in series. Word lines are connected to gates of the memory transistors. A spare word line is connected to a gate of the spare memory transistor. The memory string comprises a first semiconductor layer, a charge storage layer, a plurality of first conductive layers, and a second conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a substrate. The charge storage layer surrounds a side surface of the first semiconductor layer. The plurality of first conductive layers surround a side surface of the first semiconductor layer with the charge storage layer interposed therebetween, and function as the word lines. The second conductive layer surrounds a side surface of the first semiconductor layer with the charge storage layer interposed therebetween, and functions as the spare word line. | 03-22-2012 |
20120069660 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type. | 03-22-2012 |
20120069661 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit during an erase operation sets a voltage of a first line connected to a selected cell unit to a voltage larger than a voltage of a gate of a first transistor included in the selected cell unit by an amount of a first voltage, sets a voltage difference between a voltage of a first line connected to an unselected cell unit and a voltage of a gate of a first transistor included in the unselected cell unit to a second voltage which differs from the first voltage, applies in the selected cell unit and the unselected cell unit a third voltage to a gate of at least one of dummy memory transistors in a dummy memory string, and applies a fourth voltage to a gate of another one of the dummy memory transistors in the dummy memory string, the fourth voltage being lower than the third voltage. | 03-22-2012 |
20120069663 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit. | 03-22-2012 |
20120195120 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit controls erase operation to erase data of memory transistors, correction write operation, and correction write verify operation. In the correction write operation, a erase threshold level of a memory transistor is moved to a positive threshold level after the erase operation. In the correction write verify operation, whether or not a threshold level of the result of the correction write operation reaches a first value is determined. In the correction write operation, the control circuit executes the correction write operation with respect to plural memory units connected to a common one of the bit lines as a group. The control circuit sequentially executes the correction write verify operation with respect to plural memory units in which the correction write operation is executed. | 08-02-2012 |
20130021848 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DATA WRITE THEREIN - A memory cell comprises a first semiconductor layer, and a first conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a semiconductor substrate. The first conductive layer sandwiches a charge storage layer with the first semiconductor layer. A control circuit executes a first program operation and then executes a second program operation. The first program operation supplies a first voltage to the body of the memory cell and supplies a second voltage larger than the first voltage to the gate of the memory cell. The second program operation renders the body of the memory cell in a floating state and supplies a third voltage which is positive to the gate of the memory cell. | 01-24-2013 |
20130229876 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type. | 09-05-2013 |
20130308386 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit is configured to, during an erase operation, set a voltage of a first line connected to a selected cell unit to a voltage larger than a voltage of a gate of a first transistor included in the selected cell unit by an amount of a first voltage; set a voltage difference between a voltage of a first line connected to an unselected cell unit and a voltage of a gate of a first transistor included in the unselected cell unit to a second voltage, the first and second voltages being different; apply in the selected and unselected cell units a third voltage to a gate of at least one of dummy transistors in a dummy memory string; and apply a fourth voltage to a gate of another one of the dummy transistors in the dummy memory string, the fourth voltage being lower than the third voltage. | 11-21-2013 |
20130314994 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit. | 11-28-2013 |
20140071756 | SEMICONDUCTOR MEMORY DEVICE AND CONTROLLER - According to one embodiment, a semiconductor memory device includes a plurality of blocks. The blocks includes a first selection transistor, a second selection transistor, a plurality of memory cell transistors, a first selection gate line and a second selection gate line, and word lines. One of the blocks holds information on a word line, a first selection gate line and/or a second selection gate line including a short-circuiting defect. | 03-13-2014 |
20140085991 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type. | 03-27-2014 |
20140233323 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit is configured to, during an erase operation, set a voltage of a first line connected to a selected cell unit to a voltage larger than a voltage of a gate of a first transistor included in the selected cell unit by an amount of a first voltage. The control circuit is configured to, during the erase operation, set a voltage difference between a voltage of a first line connected to an unselected cell unit and a voltage of a gate of a first transistor included in the unselected cell unit to a second voltage, the second voltage differing from the first voltage. In addition, the control circuit is configured to, during the erase operation, apply in the selected cell unit and the unselected cell unit a third voltage to a gate of at least one of dummy memory transistors in a dummy memory string, and apply a fourth voltage to a gate of another one of the dummy memory transistors in the dummy memory string, the fourth voltage being lower than the third voltage. | 08-21-2014 |
20140313829 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type. | 10-23-2014 |
20140369127 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first string; a second string; and a controller. The first string is coupled with a first bit line and includes first memory cells. The second string is coupled with a second bit line and includes second memory cells. The controller executes writing first data into the first memory cells and writing second data into the second memory cells simultaneously. The controller reads data from the first and second strings after writing the first and second data. | 12-18-2014 |
20150029791 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit. | 01-29-2015 |
20150036434 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device reads data in units of page. The device includes: a memory cell array; a plurality of latch circuits; and an arithmetic operation circuit. The memory cell array holds data multiplexed in at least three pages. The latch circuits read and hold the multiplexed data at a startup. The arithmetic operation circuit performs operations by use of the multiplexed data. | 02-05-2015 |