Hiroyuki Mizuno
Hiroyuki Mizuno, Kokubunji JP
Patent application number | Description | Published |
---|---|---|
20110025409 | Semiconductor integrated circuit device - A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication. | 02-03-2011 |
Hiroyuki Mizuno, Toyota-Shi JP
Patent application number | Description | Published |
---|---|---|
20090287390 | CONTROL SYSTEM FOR INTERNAL COMBUSTION ENGINE AND CONTROL METHOD FOR INTERNAL COMBUSTION ENGINE - A control system for an internal combustion engine includes: a fuel amount detector; a smoothing calculation unit that calculates a smooth output value, which is obtained by smoothing an output value of the fuel amount detector in a temporal direction; a continuous low speed condition detection unit that detects a continuous low speed condition in which the vehicle speed remains in the low speed region continuously beyond a predetermined time period; a calculation processing unit that successively calculates a maximum value and a minimum value of the smooth output value; a reference setting unit that updates and stores a reference value in response to the engine stoppage and in accordance with the current minimum value calculated by the calculation processing unit; and a fuel supply determination unit that detects a fuel supply to the fuel tank during the continuous low speed condition. | 11-19-2009 |
20110017176 | ABNORMALITY DIAGNOSING SYSTEM FOR INTERNAL COMBUSTION ENGINE - An abnormality diagnosing system for an internal combustion engine including a first fuel injection valve that injects fuel into a cylinder, and a second fuel injection valve that injects fuel into an intake passage is provided which has a control device controls an injection pattern of the first fuel injection valve and the second fuel injection valve. The control device stores engine operating conditions when an abnormality occurs in the engine, and make a return-to-normal determination as to whether the engine returns to a normal operating state when similar operation conditions that are the same as or within predetermined ranges of the stored operating conditions are established. The injection pattern is selected from patterns in which the fuel is injected solely from the first fuel injection valve, solely from the second fuel injection valve, and from both of the first and second fuel injection valves. The control device stores the injection pattern when the abnormality occurs, and makes a return-to-normal determination on condition that the engine is operating in an injection pattern that is the same as the stored injection pattern. | 01-27-2011 |
Hiroyuki Mizuno, Kokubunji-Shi JP
Patent application number | Description | Published |
---|---|---|
20080297220 | Method of forming a CMOS structure having gate insulation films of different thicknesses - The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units. | 12-04-2008 |
20110012180 | METHOD OF FORMING A CMOS STRUCTURE HAVING GATE INSULATION FILMS OF DIFFERENT THICKNESSES - The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units. | 01-20-2011 |
20140252495 | METHOD OF FORMING A CMOS STRUCTURE HAVING GATE INSULATION FILMS OF DIFFERENT THICKNESSES - The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units. | 09-11-2014 |
Hiroyuki Mizuno, Musashino JP
Patent application number | Description | Published |
---|---|---|
20100017775 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided. | 01-21-2010 |
20100078635 | SEMICONDUCTOR DEVICE - As the transfer between a processor LSI and a memory has been increasing year by year, there is a demand for increasing the traffic amount and reducing the power required for communication. With this being the condition, a method of stacking LSIs thereby reducing the communication distance is being contemplated. However, the inventors have found that the reduction of cost in the stacking process and the increase in the degree of freedom of selecting the memory LSI to be stacked are required for a simple stacking of processor LSIs and memory LSIs as so far practiced. An external communication LSI including a circuit for performing the communication with the outside of the stacked LSI at a high rate of more than 1 GHz; a processor LSI including a general purpose CPU etc.; and a memory LSI including a DRAM etc. are stacked in this order and those LSIs are connected with one another with a through silicon via to enable a high speed and high volume communication at a shortest path. Further, an interposer for facilitating the connection with the processor LSI is connected to the input terminal of the memory LSI to be stacked thereby increasing the degree of freedom in selecting memories. | 04-01-2010 |
20100083011 | INFORMATION PROCESSING DEVICE - In a configuration provided with, for example, sixty four pieces of processor cores, an on-chip-memory, a bus commonly connected thereto, and others, the processor cores are operated by a power supply with low voltage and a clock with low frequency, and the bus is operated by a power supply with high voltage and a clock with high frequency. Each of the processor cores is provided with a bus interface and a frequency divider in order to absorb a power supply voltage difference and a frequency difference between the bus and each of them. The frequency divider generates the clock with low frequency from the clock with high frequency, and the bus interface is provided with a level shifting function, a data width converting function, a hand shaking function between the bus and the bus interface, and the like. | 04-01-2010 |
20100182076 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device achieving an active state in which a high speed operation is performed and an inactive state in which a low leakage state is retained while an internal logical state is retained, and a transition between the two states can be achieved at high speed with low noise and low power. A power control circuit provided between a first power-supply line for providing a first external power-supply voltage and a second power-supply line for providing a second external power-supply voltage includes an output MOSFET. A constant OFF current flows in the MOSFET even if a gate and a source of the output MOSFET are put in the same voltage, and a threshold voltage of the output MOSFET is smaller than that of an internal circuit MOSFET. | 07-22-2010 |
20110316620 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided. | 12-29-2011 |
20120025892 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device provided with a first circuit block BLK | 02-02-2012 |
20120187981 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided. | 07-26-2012 |
20120294081 | SEMICONDUCTOR DEVICE - In a sense circuit for DRAM memory cell a switch is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL. | 11-22-2012 |
20130228939 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided. | 09-05-2013 |
20140167819 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH INDEPENDENT POWER DOMAINS - A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided. | 06-19-2014 |
20150295572 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided. | 10-15-2015 |
Hiroyuki Mizuno, Kolubunji JP
Patent application number | Description | Published |
---|---|---|
20100156522 | Semiconductor integrated circuit device - A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication. | 06-24-2010 |
Hiroyuki Mizuno, Yokohama-Shi JP
Patent application number | Description | Published |
---|---|---|
20090095711 | MICROFABRICATION APPARATUS AND DEVICE MANUFACTURING METHOD - A microfabrication apparatus for pressing an original plate including a pattern down on a substrate to transfer the pattern on the substrate includes a first measurement unit for measuring relative positional displacement between the substrate and the plate above the substrate, a position correction unit for correcting relative position between the substrate and the plate such that the pattern is to be transferred on a first predetermined position of the substrate based on the relative positional displacement measured by the first measurement unit, a pressing unit for pressing the plate above the substrate down on the substrate to transfer the pattern on the substrate in a state that the relative positional displacement between the substrate and the plate is corrected by the position correction unit, and a second measurement unit for measuring relative positional relationship between the pattern transferred on the substrate and a pattern previously formed on the substrate. | 04-16-2009 |
20090206280 | CHARGED-BEAM EXPOSURE APPARATUS HAVING AN IMPROVED ALIGNMENT PRECISION AND EXPOSURE METHOD - The first charged-beam optical system, which is one of the charged-beam optical systems, detects first marks provided on the chips formed in the wafer. The positions of the chips made in the wafer are calculated from position data about the first marks detected. The charged-beam optical systems detect the second mark provided on a stage. The position of the beam generated by each charged-beam optical system is adjusted in accordance with position data about the second mark detected. The charged-beam optical systems are used in accordance with the positions of the chips, to thereby draw a pattern. | 08-20-2009 |
20150319845 | PRINTED WIRING BOARD AND PRINTED CIRCUIT BOARD - A main wire | 11-05-2015 |
20150371698 | PRINTED CIRCUIT BOARD, AND PRINTED WIRING BOARD - A motherboard includes a main wiring as a transmission line for a signal transmitted by a memory controller, and a branching wiring branched from a branching point of the main wiring and connected to the memory device. Furthermore, the motherboard includes a branching wiring including a land to which a memory device may be joined and branched from a branching point, and an open stub formed extending from the land. According to such a structure, ringing in the waveform of a signal received by the receiving circuit may be suppressed at the time of both single-side mounting and double-side mounting, and also, ringing of a signal may be sufficiently suppressed in the case where the number of DIMMs used by the same substrate is changed. | 12-24-2015 |
Hiroyuki Mizuno, Kashiwa City JP
Patent application number | Description | Published |
---|---|---|
20090106541 | PROCESSORS WITH BRANCH INSTRUCTION, CIRCUITS, SYSTEMS AND PROCESSES OF MANUFACTURE AND OPERATION - An electronic processor is provided for use with a memory ( | 04-23-2009 |
Hiroyuki Mizuno US
Patent application number | Description | Published |
---|---|---|
20090027984 | SEMICONDUCTOR DEVICE - The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to bit line LBL. | 01-29-2009 |
20110133827 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device provided with a first circuit block BLK | 06-09-2011 |
Hiroyuki Mizuno, Kashiwa-Shi JP
Patent application number | Description | Published |
---|---|---|
20090019262 | PROCESSOR MICRO-ARCHITECTURE FOR COMPUTE, SAVE OR RESTORE MULTIPLE REGISTERS, DEVICES, SYSTEMS, METHODS AND PROCESSES OF MANUFACTURE - An electronic circuit ( | 01-15-2009 |
Hiroyuki Mizuno, Aichi-Ken JP
Patent application number | Description | Published |
---|---|---|
20110163512 | STEERING TIE ROD END MADE OF STEEL AND METHOD OF MANUFACTURING THE SAME - A steel tie rod end includes a shaft portion and first and second fitting portions. A minimum area portion having a small radially cross-sectional area is provided for the shaft portion, and 90% or above of a steel structure of the minimum area portion is formed of martensite or tempered martensite. The surface hardness of the minimum area portion and the average hardness of the radial cross section of the minimum area portion are 600 Hv or below, and the average hardness of the radial cross section of the first fitting portion and the average hardness of the radial cross section of the second fitting portion are 300 Hv or below. A method of manufacturing a steel tie rod end includes a quenching process of heating only a prospective shaft portion by high frequency to an austenitizing temperature and then rapidly cooling the prospective shaft portion by water or cooling medium. | 07-07-2011 |
Hiroyuki Mizuno, Kashiwa JP
Patent application number | Description | Published |
---|---|---|
20120023313 | PROCESSOR MICRO-ARCHITECTURE FOR COMPUTE, SAVE OR RESTORE MULTIPLE REGISTERS, DEVICES, SYSTEMS, METHODS AND PROCESSES OF MANUFACTURE - An electronic circuit ( | 01-26-2012 |
20140201503 | PROCESSOR MICRO-ARCHITECTURE FOR COMPUTE, SAVE OR RESTORE MULTIPLE REGISTERS, DEVICES, SYSTEMS, METHODS AND PROCESSES OF MANUFACTURE - An electronic circuit ( | 07-17-2014 |
Hiroyuki Mizuno, Uji-Shi JP
Patent application number | Description | Published |
---|---|---|
20120247861 | WORK VEHICLE - In a work vehicle, a second processing device, disposed over a hydraulic pump, is configured to process the hydraulic gas from an engine. A first processing device is disposed closer to the engine than the second processing device is Further, the first processing device is positioned higher the second processing device. The first processing device is partially overlapped with the second processing device in a top plan view. | 10-04-2012 |
Hiroyuki Mizuno, Tokai-Shi JP
Patent application number | Description | Published |
---|---|---|
20120318409 | SOLID STABILIZER, STEEL MATERIAL FOR SOLID STABILIZER, AND MANUFACTURING METHOD OF SOLID STABILIZER - A steel material for a solid stabilizer which has high bendability, high hardenability, and high quenching crack resistance, a solid stabilizer having high strength, and a manufacturing method of the solid stabilizer. The steel material for the solid stabilizer contains, in mass %, 0.24 to 0.40% of C, 0.15 to 0.40% of Si, 0.50 to 1.20% of Mn, 0.03% or less of P, 0.30% or less of Cr, 0.01 to 0.03% of Ti, and 0.0010 to 0.0030% of B. The steel material for the solid stabilizer satisfies a condition of formula (1) below. Hardness in a radial center portion of the steel material for the solid stabilizer after tempering is 400 HV or more, and a martensite ratio in the radial center portion after the tempering is 80% or more. | 12-20-2012 |
Hiroyuki Mizuno, Kariya JP
Patent application number | Description | Published |
---|---|---|
20130018538 | EVALUATION INDICATION SYSTEM, EVALUATION INDICATION METHOD AND COMPUTER-READABLE STORAGE MEDIUMAANM MIURA; NaokiAACI ToyokawaAACO JPAAGP MIURA; Naoki Toyokawa JPAANM NONOMURA; JunichiAACI OkazakiAACO JPAAGP NONOMURA; Junichi Okazaki JPAANM YAMAKAWA; JunkiAACI OkazakiAACO JPAAGP YAMAKAWA; Junki Okazaki JPAANM MIZUNO; HiroyukiAACI KariyaAACO JPAAGP MIZUNO; Hiroyuki Kariya JP - Evaluation indication systems, methods, and programs are provided for a hybrid vehicle that is configured to travel in an HV mode with an internal combustion engine or in an EV mode without the internal combustion engine. The systems, methods, and programs display a current position of the hybrid vehicle on a map, acquire current evaluations of fuel consumption of the hybrid vehicle in current travel by unit sections, acquire previous evaluations of fuel consumption of the hybrid vehicle in previous travel by unit sections, and indicate current evaluation icons on the map, each of the icons being an EV icon or art HV icon. Each EV icon indicates that the hybrid vehicle has travelled within the corresponding unit section in the EV mode and each HV icon indicates that the hybrid vehicle has travelled within the corresponding unit section in the HV mode. | 01-17-2013 |
20130018573 | EVALUATION INDICATION SYSTEM, EVALUATION INDICATION METHOD AND COMPUTER-READABLE STORAGE MEDIUMAANM MIURA; NaokiAACI ToyokahaAACO JPAAGP MIURA; Naoki Toyokaha JPAANM NONOMURA; JunichiAACI OkazakiAACO JPAAGP NONOMURA; Junichi Okazaki JPAANM YAMAKAWA; JunkiAACI OkazakiAACO JPAAGP YAMAKAWA; Junki Okazaki JPAANM MIZUNO; HiroyukiAACI KariyaAACO JPAAGP MIZUNO; Hiroyuki Kariya JP - Evaluation indication systems, methods, and programs display a current position of a vehicle and a map around the current position on a display unit, acquire current evaluations that indicate evaluations of fuel consumption in current travel of the vehicle by unit sections, and acquire previous evaluations that indicate evaluations of fuel consumption of the vehicle in a past prior to the current travel by unit sections. The systems, methods, and programs indicate the current evaluations and the previous evaluations together by unit sections on the map. | 01-17-2013 |
20130035847 | NAVIGATION SYSTEM, NAVIGATION METHOD, AND COMPUTER-READABLE STORAGE MEDIUM - Navigation systems, methods, and programs acquire evaluation information for evaluating the driving of a vehicle, evaluate the driver's driving operation for each evaluation interval having a predetermined travel distance based on the evaluation information, and display a past evaluation result and a current evaluation result at a position corresponding to each evaluation interval on a map in a mode that differs between the past evaluation result and the current evaluation result. When the vehicle arrives at an end point of the evaluation interval of the past travel from the same direction as during the past travel time, the systems, methods, and programs evaluate the driver's driving operation for a current evaluation interval along a travel track of the current travel and display the current evaluation result on the current evaluation interval at a position which corresponds to the current evaluation interval and at which the past evaluation result is displayed. | 02-07-2013 |
Hiroyuki Mizuno, Kanagawa JP
Patent application number | Description | Published |
---|---|---|
20130026956 | INJECTION MOLDING MACHINE - An injection molding machine according to the invention includes a motor, a driver circuit that drives the motor; and a rectifying part that supplies electric power to the driver circuit. A regenerative line for regenerative electric power of the motor is connected to the rectifying part in parallel. A converting part and a harmonics component reducing part are provided in the regenerative line. The converting part converts direct electric power between the driver circuit and the rectifying part into alternating electric power which is input to the harmonics component reducing part. | 01-31-2013 |
20130026961 | INJECTION MOLDING MACHINE - An injection molding machine includes a motor; a driver circuit; a rectifying part; a capacitor provided between the driver circuit and the rectifying part; a bridge circuit that converts direct electric power between the driver circuit and the rectifying part into alternating electric power; a harmonics component reducing part connected to an alternating side of the bridge circuit; and a regenerative line connected to the rectifying part in parallel, wherein the bridge circuit and the harmonics component reducing part are provided in the regenerative line, and plural switching elements of the bridge circuit are turned on or off such that electric power of the motor is regenerated when a voltage of the capacitor is greater than or equal to a predetermined value, and all the switching elements are turned off when the voltage of the capacitor is less than the predetermined value. | 01-31-2013 |
Hiroyuki Mizuno, Mie-Ken JP
Patent application number | Description | Published |
---|---|---|
20130252176 | METHOD FOR MAKING CORRECTION MAP OF DOSE AMOUNT, EXPOSURE METHOD, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method for making a correction map of a dose amount of EUV light used when exposing with the EUV light, includes estimating an exposure result based on an initial correction map of the dose amount and flare of the EUV light, determining a goodness of the exposure result, and correcting the initial correction map in the case where the exposure result is unacceptable. And, the correcting of the initial correction map, the estimating of the exposure result, and the determining of the goodness are repeated until the exposure result is good. | 09-26-2013 |
Hiroyuki Mizuno, Kuwana-Shi JP
Patent application number | Description | Published |
---|---|---|
20140349219 | EXPOSURE METHOD, REFLECTION TYPE MASK, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to embodiments, an exposure method is provided. In the exposure method, a transmittance of a pellicle is adjusted every position of a mask pattern included in a reflection type mask. And when adjusting the transmittance of the pellicle, a film thickness of the pellicle is adjusted on the basis of a transmittance correction amount. Thereafter, exposure is conducted onto a substrate by using the reflection type mask with the pellicle stuck thereon. | 11-27-2014 |
20150062570 | INSPECTING APPARATUS AND INSPECTING METHOD - According to one embodiment, an inspecting apparatus is provided with a contact position obtaining unit and an inspection status determining unit. The contact position obtaining unit obtains, by using an inspection result of whether there is a particle on an inspection surface of a holding object and coordinate information of a convex portion in an electrostatic chuck holding mechanism, a contact position of the inspection surface with the convex portion. The inspection status determining unit determines whether a size of the particle adhering to a contact region with the convex portion of the inspection surface is within an allowable range by using a first determining criterion value and determines whether the size of the particle adhering to a non-contact region with the convex portion of the inspection surface is within an allowable range by using a second determining criterion value larger than the first determining criterion value. | 03-05-2015 |
Hiroyuki Mizuno, Aichi JP
Patent application number | Description | Published |
---|---|---|
20150159247 | STEEL MATERIAL FOR FRICTION WELDING, AND METHOD FOR PRODUCING SAME - A chemical composition includes, in mass percent, C: 0.30 to 0.55%, Si: 0.05 to 1.0%, Mn: 0.05 to 0.9%, P: 0.001 to 0.030%, S: 0.005 to 0.12%, Cr: 0.05 to 2.0%, Al: 0.005 to 0.05%, N: 0.0050 to 0.0200%, and the balance being Fe and unavoidable impurities, an amount of N in solid solution being not less than 0.0020%, wherein the contents of Mn and S satisfy relationships expressed by the following expressions: | 06-11-2015 |
Hiroyuki Mizuno, Osaka JP
Patent application number | Description | Published |
---|---|---|
20150380768 | ELECTROLYTE SOLUTION AND LITHIUM ION SECONDARY BATTERY PROVIDED WITH SAME - The objective of the present invention is to provide an electrolyte solution of which electrolyte salt concentration is high and by which cycle characteristics hardly deteriorate and battery lifetime can be extended, and a lithium ion secondary battery which contains the above electrolyte solution. The electrolyte solution of the present invention comprises an electrolyte salt and a solvent, wherein a concentration of the electrolyte salt is more than 1.1 mol/L, the electrolyte salt contains a compound represented by the following formula (1): (XSO | 12-31-2015 |