Patent application number | Description | Published |
20140281144 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile memory including first blocks configured to store an address indicating a data storage position, and second blocks configured to store the data, a first table configured to store a first address including first information and second information, the second information indicating a data storage position in the first block, and a second table configured to convert the first information into third information, the first information having a first data size by which one entry of the second table can be identified, the third information having a second data size which is larger than the first data size and by which one of the first blocks and the second blocks can be identified. | 09-18-2014 |
20140281160 | NON-VOLATILE SEMICONDUCTOR STORAGE APPARATUS - According to one embodiment, apparatus includes non-volatile memory chips, and a first controller which executes processing for reading first valid data stored in a first storage region of a first non-volatile memory chip in the non-volatile memory chips, processing for storing the first valid data in a buffer memory, processing for writing the first valid data stored in the buffer memory in a second storage region of the first non-volatile memory chip, and processing for erasing data stored in the first storage region. Each of the non-volatile memory chips comprises erase blocks. Each erase block includes write blocks. Each of the first storage region and the second storage region includes at least one erase block. | 09-18-2014 |
20150067415 | MEMORY SYSTEM AND CONSTRUCTING METHOD OF LOGICAL BLOCK - According to one embodiment, a memory system includes a bit-error-rate manager configured to manage information associated with a bit error rate for each physical block, a logical-block constructing unit configured to construct a logical block based on the information associated with the bit error rate, and a block manager configured to manage the correspondence between the logical block constructed by the logical-block constructing unit and the physical blocks. The logical block is a collection of a plurality of physical blocks. | 03-05-2015 |
20150074333 | MEMORY CONTROLLER AND MEMORY SYSTEM - According to an embodiment, an access controller refers to state information upon an erase operation, causes the erase operation to be performed on all the collection of physical blocks included in a first logical block, and causes the erase operation to be performed on a part of the collection of physical blocks included in a second logical block and does not causes the erase operation to be performed on rest of the collection of the physical blocks in the second logical block. | 03-12-2015 |
20150261444 | MEMORY SYSTEM AND INFORMATION PROCESSING DEVICE - According to one embodiment, a memory system includes a first memory, an interface, and a control unit. The first memory can operate in first mode in which n (n≧2) pieces of unit data are written per word line and in second mode in which one piece of unit data is written per word line. When n pieces of unit data to be written to the first word line exist in the second memory, the control unit writes the first unit data to the first word line, using the n pieces of unit data to be written to the first word line. When receiving a flush request, the control unit writes a second unit data to a second word line, the second unit data being unit data stored in the second memory, based on the second mode. | 09-17-2015 |
Patent application number | Description | Published |
20150193301 | MEMORY CONTROLLER AND MEMORY SYSTEM - A controller according to one embodiment controls a memory, the memory including blocks and configured to erase data in the blocks with each of the blocks as a minimum unit. Each of the blocks includes unit memory areas each specified by an address. The controller is configured to add a code for error correction to received data to generate a data unit, divide the data unit into data unit sections, and write the data unit sections in unit memory areas of respective blocks, the unit memory areas having different addresses. | 07-09-2015 |
20150206590 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile semiconductor memory device and a controller. The system includes the nonvolatile semiconductor memory device including a plurality of memory cells; and the controller configured to control one of read operation, write operation, and a use frequency of the read operation or the write operation on the nonvolatile semiconductor memory device, and configured to change controlling for a memory cell belonging to a first group of the memory cells and to change controlling for a memory cell belonging to a second group located on an upper side or a lower side of the memory cell belonging to the first group. | 07-23-2015 |
20150212884 | MEMORY CONTROLLER, STORAGE DEVICE, AND MEMORY CONTROL METHOD - According to one embodiment, a storage device includes an encoder, a nonvolatile memory that stores user data and a parity, a magnetic disk, and a management unit that holds correspondence between a logical address and a first physical address as first conversion information, and holds correspondence between the first physical address and a second physical address as second conversion information, with the second physical address including media information indicating a medium of a storage destination and information indicating a storage position. When the user data stored in the nonvolatile memory is to be moved to the magnetic disk, the management unit updates the second physical address of the user date in the second conversion information, to a value indicating a storage destination after the movement. | 07-30-2015 |
20150254134 | MEMORY CONTROLLER, MEMORY SYSTEM, AND MEMORY CONTROL METHOD - According to one embodiment, a memory controller includes a writing destination management unit which determines a writing destination of user data, an encoding unit which generates a parity of the user data, and an ECC management unit which measures a fatigue degree of each certain memory area of a nonvolatile memory, selects an encoding method to instruct the encoding unit to be performed according to the encoding method, and changes the encoding method to an encoding method having a high error correction capability in a case where the fatigue degree corresponding to the writing destination is equal to or higher than a threshold and a total sum of parities is equal to or less than a predetermined amount. | 09-10-2015 |