Patent application number | Description | Published |
20080253011 | Signal Processing Device and Signal Processing Method - There is provided a signal processing apparatus and a signal processing method, which can simultaneously perform reduction in jitter components and reduction in error rate. | 10-16-2008 |
20090060451 | Timing Extraction Device and Video Display Device - An asynchronous timing detector | 03-05-2009 |
20090086588 | Timing extractor, and information playback apparatus and dvd device using the timing extractor - In a feedforward timing extractor for extracting timing information from a playback signal, a frequency ratio calculation section | 04-02-2009 |
20100020250 | REPRODUCED SIGNAL PROCESSOR AND VIDEO DISPLAY - In a feedforward control type reproduced signal processor, a clock generator | 01-28-2010 |
20100066722 | INFORMATION REPRODUCTION APPARTUS AND VIDEO DISPLAY APPARATUS - In an asynchronous read channel system, a reference value interpolation-type maximum likelihood decoder ASML having a small circuit scale (e.g., seven taps) is employed. A nonlinear waveform the equalizer SEQ is provided before the maximum likelihood decoder ASML. The nonlinear waveform the equalizer SEQ includes an FIR filter having, for example, four taps, and performs nonlinear waveform equalization with respect to an input digital signal so that only signal components having small amplitudes and high frequencies are amplified. After the nonlinear waveform equalization, the signal is input to the reference value interpolation-type maximum likelihood decoder ASML, which performs maximum likelihood decoding with respect to the signal. Therefore, even when the reference value interpolation-type maximum likelihood decoder includes a smaller number of taps and thus has a small circuit scale, maximum likelihood decoding with a high error correction function can be performed. | 03-18-2010 |
20100194618 | ANALOG-TO-DIGITAL CONVERTER, OPTICAL DISK REPRODUCTION DEVICE, AND RECEIVER DEVICE - A plurality of comparators (CMP | 08-05-2010 |
20110095786 | PHASE COMPARATOR, PLL CIRCUIT, INFORMATION REPRODUCTION PROCESSING DEVICE, OPTICAL DISK PLAYBACK DEVICE AND MAGNETIC DISK PLAYBACK DEVICE - In a phase comparator used for a sync clock extraction circuit for extracting a clock synchronizing with reproduction data, a zero cross detection section | 04-28-2011 |
20120081339 | DIGITAL PLL CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND DISPLAY APPARATUS - In a digital PLL circuit, a phase comparison circuit counts the numbers of transitions of a reference clock and an oscillation clock, sets a time taken until the number of transitions of the reference clock reaches a reference count value as a phase comparison time period, and detects, as a phase error value, a difference between a target count value, obtained based on a magnification value of a desired oscillating frequency with respect to the frequency of the reference clock and the reference count value, and the number of transitions of the oscillation clock in the phase comparison time period. A smoothing circuit smoothes the phase error value. A digitally-controlled oscillation circuit controls the frequency of the oscillation clock in accordance with the phase error value smoothed by the smoothing circuit. | 04-05-2012 |
20140301516 | ORTHOGONAL TRANSFORM ERROR CORRECTOR - A phase adjuster arranges phases of waveforms of a complex signal after orthogonal transform. An edge detector detects an edge of the complex signal after phase adjustment. A phase shift detector detects phase shift of an output signal of the edge detector between the in-phase signal and the quadrature signal after the orthogonal transform, and outputs a phase error signal (PE). The oscillator connected to mixers and a shifter to perform the orthogonal transform includes a phase adjustment section adjusting an edge of a voltage controlled oscillator (VCO) clock based on the phase error signal (PE) and correcting the phase shift of an original signal. | 10-09-2014 |