Patent application number | Description | Published |
20090045526 | Stacked memory without unbalanced temperature distributions - A stacked memory without unbalanced temperature distributions is disclosed. According to one aspect of the invention, a through electrode in each layer is connected one after the other such that regions to be activated in neighboring layers do not overlap in a vertical direction. According to another aspect of the invention, each layer comprises an activation region distribution circuit for outputting an activation signal to, among the regions of the layer, a region having an address different from an address of a region to be activated in a layer adjacent to the layer in question. | 02-19-2009 |
20090109641 | Wafer of circuit board and joining structure of wafer or circuit board - A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusion | 04-30-2009 |
20090134498 | SEMICONDUCTOR APPARATUS - The present invention includes a semiconductor element provided with an electrode passing through front and back sides. The electrode is formed as a cylinder including a hollow portion, and stress relaxing material is provided in the hollow portion, which is used to reduce stress that is induced between the semiconductor element and the electrode. The stress relaxing material is an elastic body made of resin material. | 05-28-2009 |
20090219745 | MEMORY MODULE AND MEMORY DEVICE - In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip. | 09-03-2009 |
20090220025 | Transmission method, transmission circuit and transmission system - A transmission method for transmitting transmission data via a single line, includes: transmitting, as the transmission data, data that has one rising or falling transition of the amplitude of the data in each clock cycle of a clock and that carries a 2- or greater-bit value, making use of the phase from the edge of the clock to the transition in amplitude of the data. | 09-03-2009 |
20090294990 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips. | 12-03-2009 |
20090315147 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - A wire embedded in a semiconductor substrate is covered with an insulating film, and a bias voltage is applied to the semiconductor substrate or to the wire to form a depletion layer extending from an edge of the insulating film. Alternatively, a semiconductor layer having a different conductivity type from the semiconductor substrate is formed within the semiconductor substrate to surround the insulating film. | 12-24-2009 |
20090315872 | LIQUID CRYSTAL DISPLAY APPARATUS AND LIQUID CRYSTAL PANEL DRIVING MEHTOD - A liquid crystal display apparatus includes common voltage generator circuit ( | 12-24-2009 |
20100193962 | SEMICONDUCTOR DEVICE - A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups. | 08-05-2010 |
20100232201 | STACKED SEMICONDUCTOR MEMORY DEVICE - A stacked semiconductor memory device includes an interface chip and a plurality of core chips, in which the interface chip and the plurality of core chips are stacked. The core chips are mutually connected by a plurality of data through electrodes. The core chips each include a plurality of memory arrays. In response to an access request, the plurality of memory arrays corresponding to a predetermined data through electrode are activated, and the plurality of activated memory arrays and the predetermined data through electrode are sequentially connected. Thereby, even though it requires approximately ten-odd ns for transferring the first data, similarly to the conventional case, it is possible to transfer the subsequent data at high speed determined by the reaction rate (1 to 2 ns) of the through electrode. As a result, it becomes possible to increase a bandwidth while suppressing the number of through electrodes. | 09-16-2010 |
20110059229 | METHOD OF MANUFACTURING GLASS SUBSTRATE AND INFORMATION RECORDING MEDIUM - In a method of manufacturing a glass substrate for an information recording medium including a step for chemically strengthening the glass substrate by contacting the glass substrate with chemical strengthening processing liquid containing chemical strengthening salt, concentration of Fe and Cr is 500 ppb or less in said chemical strengthening salt, respectively. The concentration may be detected by the use of an ICP (Inductively Coupled Plasma) emission spectrometry analyzing method or a fluorescent X-ray spectroscopy analyzing method. | 03-10-2011 |
20110104852 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips. | 05-05-2011 |
20110141789 | MEMORY MODULE AND MEMORY SYSTEM - In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip. | 06-16-2011 |
20110234645 | IMAGE DISPLAY APPARATUS, PICTURE SIGNAL PROCESSING METHOD, AND PROGRAM - An image display apparatus includes: a panel ( | 09-29-2011 |
20110244628 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: supplying a supercritical fluid mixed with an under-fill material to a stacked unit, which has a plurality of stacked semiconductor chips; and filling the under-fill material in the space between the plurality of the semiconductor chips, by heating the stacked unit placed in the inside of the high-pressure vessel and curing the under-fill material flowing in the space between the plurality of the semiconductor chips by a polymerization reaction, while the supercritical fluid is being supplied. | 10-06-2011 |
20120019507 | IMAGE DISPLAY APPARATUS AND IMAGE CORRECTION METHOD - The present invention is aimed at appropriately suppressing display failure such as a tailing phenomenon and the like in a normally white type liquid crystal panel. A driver ( | 01-26-2012 |
20120069057 | LIQUID CRYSTAL DISPLAY DEVICE AND DRIVING METHOD FOR LIQUID CRYSTAL PANEL - A liquid crystal display device having a liquid crystal panel includes a common voltage generating section ( | 03-22-2012 |
20120122251 | STACKED TYPE SEMICONDUCTOR MEMORY DEVICE AND CHIP SELECTION CIRCUIT - A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them. | 05-17-2012 |
20120187402 | SEMICONDUCTOR DEVICE AND STACKED SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip having first and second surfaces. A first through electrode extends through the semiconductor chip. A first surface electrode is positioned on the first surface of the semiconductor chip and coupled to a first end of the first through electrode. A second surface electrode is positioned on the second surface of the semiconductor chip. The second surface electrode is coupled to a second end of the first through electrode. A second through electrode extends through the semiconductor chip and has third and fourth ends. A third surface electrode is positioned on the second surface of the semiconductor chip and is coupled to the fourth end of the second through electrode. The semiconductor device is free of a surface electrode on the first surface of the semiconductor chip and is coupled to the third end of the second through electrode. | 07-26-2012 |
20120262974 | MEMORY MODULE AND MEMORY SYSTEM - In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip. | 10-18-2012 |
20130011967 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips. | 01-10-2013 |
20130140067 | WAFER OR CIRCUIT BOARD AND JOINING STRUCTURE OF WAFER OR CIRCUIT BOARD - A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusion | 06-06-2013 |
20130187294 | SEMICONDUCTOR DEVICE INCLUDING STACKED SEMICONDUCTOR CHIPS - A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups. | 07-25-2013 |
20130213091 | METHOD OF MANUFACTURING GLASS SUBSTRATE AND INFORMATION RECORDING MEDIUM - In a method of manufacturing a glass substrate for an information recording medium including a step for chemically strengthening the glass substrate by contacting the glass substrate with chemical strengthening processing liquid containing chemical strengthening salt, concentration of Fe and Cr is 500 ppb or less in said chemical strengthening salt, respectively. The concentration may be detected by the use of an ICP (Inductively Coupled Plasma) emission spectrometry analyzing method or a fluorescent X-ray spectroscopy analyzing method. | 08-22-2013 |
20140021978 | TEST METHOD FOR SEMICONDUCTOR DEVICE HAVING STACKED PLURAL SEMICONDUCTOR CHIPS - Disclosed herein is a method for testing a semiconductor device, the method includes: preparing a first semiconductor chip having a first bump electrode and a first driver circuit that drives the first bump electrode, and a second semiconductor chip having a second bump electrode and a second driver circuit that drives the second bump electrode; staking the first and second semiconductor chips so that the first bump electrode and the second bump electrode are electrically connected to each other to form a current path including the first and second bump electrodes; and driving, in a test mode, the current path to a first potential by the first driver circuit while driving the current path to a second potential different from the first potential by the second driver circuit. | 01-23-2014 |
20140087518 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: supplying a supercritical fluid mixed with an under-fill material to a stacked unit, which has a plurality of stacked semiconductor chips; and filling the under-fill material in the space between the plurality of the semiconductor chips, by heating the stacked unit placed in the inside of the high-pressure vessel and curing the under-fill material flowing in the space between the plurality of the semiconductor chips by a polymerization reaction, while the supercritical fluid is being supplied. | 03-27-2014 |
20140183730 | SEMICONDUCTOR DEVICE HAVING A LIQUID COOLING MODULE - A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate. | 07-03-2014 |
20140299878 | SEMICONDUCTOR DEVICE AND STACKED SEMICONDUCTOR DEVICE - A semiconductor device includes a package substrate, and a stack of semiconductor chips over the package substrate, each of the semiconductor chips including first and second surfaces, each of the semiconductor chips including a first through electrode that extends through each of the semiconductor chips, a first surface electrode positioned on the first surface of each of the semiconductor chips, the first surface electrode being coupled to a first end of the first through electrode, a second surface electrode positioned on the second surface of each of the semiconductor chips, the second surface electrode being coupled to a second end of the first through electrode, a second through electrode that extends through each of the semiconductor chips, the second through electrode having third and fourth ends, and a third surface electrode positioned on the second surface of the first semiconductor chip. | 10-09-2014 |
20140369148 | MEMORY MODULE AND MEMORY SYSTEM - In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip. | 12-18-2014 |
20150041990 | WIRING SUBSTRATE AND MANUFACTURING METHOD THEREFOR - A wiring substrate includes a semiconductor substrate, an insulator and a plurality of columnar conductors. The insulator is made of an insulating material filled in a groove or hole provided in the semiconductor substrate. The plurality of columnar conductors are filled in grooves or holes provided in the insulator. The grooves or holes are arranged at a narrow pitch in a plane of the insulator. The insulating material has a Si—O bond obtained by reacting Si particles with an organic Si compound. | 02-12-2015 |