Hily
Sebastien Hily, Hillsboro, OR US
Patent application number | Description | Published |
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20100169582 | Obtaining data for redundant multithreading (RMT) execution - In one embodiment, the present invention includes a method for providing a cache block in an exclusive state to a first cache and providing the same cache block in the exclusive state to a second cache when cores accessing the two caches are executing redundant threads. Other embodiments are described and claimed. | 07-01-2010 |
20100169628 | Controlling non-redundant execution in a redundant multithreading (RMT) processor - In one embodiment, the present invention includes a method for controlling redundant execution such that if an exceptional event occurs, the redundant execution is stopped, non-redundant execution is performed in one of the threads until the exceptional event has been-resolved, after which a state of the threads is synchronized, and redundant execution is continued. Other embodiments are described and claimed. | 07-01-2010 |
Sebastien Hily, Portland, OR US
Patent application number | Description | Published |
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20110307894 | Redundant Multithreading Processor - A redundant multithreading processor is presented. In one embodiment, the processor performs execution of a thread and its duplicate thread in parallel and determines, when in a redundant multithreading mode, whether or not to synchronize an operation of the thread and an operation of the duplicate thread. | 12-15-2011 |
20140223105 | METHOD AND APPARATUS FOR CUTTING SENIOR STORE LATENCY USING STORE PREFETCHING - In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for cutting senior store latency using store prefetching. For example, in one embodiment, such means may include an integrated circuit or an out of order processor means that processes out of order instructions and enforces in-order requirements for a cache. Such an integrated circuit or out of order processor means further includes means for receiving a store instruction; means for performing address generation and translation for the store instruction to calculate a physical address of the memory to be accessed by the store instruction; and means for executing a pre-fetch for a cache line based on the store instruction and the calculated physical address before the store instruction retires. | 08-07-2014 |
Serge Hily, Bayeux FR
Patent application number | Description | Published |
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20110055532 | METHOD FOR CONFIGURING AN ELECTRONIC ORGANIZER - This method for configuring an electronic organizer installed in an item of electronic equipment comprises: a step of obtaining, based on digital data resulting from a digitization of a representation of a code, data encoded in this code and comprising at least one item of date information associated with a content; and a step of configuring said electronic organizer in order to program, on at least one date or at at least one time defined by this item of date information, an execution of a function relating to said content. | 03-03-2011 |