Patent application number | Description | Published |
20080224774 | Method and Apparatus for Systematic and Random Variation and Mismatch Compensation for Multilevel Flash Memory Operation - Method and means for random or systematic mismatch compensation for a memory sensing system are disclosed. A sense amplifier includes a bulk voltage source to set the bulk of the sensing transistor to be a voltage different than the voltage driving the sensing transistor. For an NMOS sensing transistor, a triple well is used with the variable bulk voltage. Differential sense amplifiers with various offset compensation are included. Intentional offset creation for useful purpose is also included. | 09-18-2008 |
20080239834 | SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING - A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node. | 10-02-2008 |
20080278986 | High-Speed and Low-Power Differential Non-Volatile Content Addressable Memory Cell and Array - A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors. A match line connects to the first terminal of each of the pair of non-volatile floating gate transistors to a first voltage. Finally, the second terminals of each storage element is connected to a second voltage, different from the first voltage. A current passing through the memory cell is indicative of a mis-match between the contents of the compare data lines and the contents of the storage elements. | 11-13-2008 |
20080290931 | Charge pump systems and methods - Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry. | 11-27-2008 |
20090016106 | SUB VOLT FLASH MEMORY SYSTEM - Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system. | 01-15-2009 |
20090052248 | FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL - A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included. | 02-26-2009 |
20090067235 | Test circuit and method for multilevel cell flash memory - A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system. | 03-12-2009 |
20090067239 | FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL - A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included. | 03-12-2009 |
20090073770 | Independent Bi-Directional Margin Control Per Level And Independently Expandable Reference Cell Levels For Flash Memory Sensing - A memory system includes reference level generators that may provide programmable margins, and programmable verify voltage levels. The reference levels may be shifted within a range of voltages with varying differences between reference voltage levels and with different margins and verify levels. | 03-19-2009 |
20090096507 | Integrated Semiconductor Metal-Insulator-Semiconductor Capacitor - An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and spaced apart from the channel region of the first capacitor. The second capacitor is substantially identical to the first capacitor and is formed in the same semiconductor substrate. The gate electrode of the first capacitor is electrically connected to the first region of the second capacitor and the gate electrode of the second capacitor is electrically connected to the first region of the first capacitor. In this manner, the capacitors are connected in an anti-parallel configuration. A capacitor which has high capacitance densities, low process complexity, ambipolar operation, low voltage and temperature coefficient, low external parasitic resistance and capacitance and good matching characteristics for use in analog designs that can be integrated with existing semiconductor processes results. | 04-16-2009 |
20090147579 | NON-VOLATILE MEMORY SYSTEMS AND METHODS INCLUDING PAGE READ AND/OR CONFIGURATION FEATURES - A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described. | 06-11-2009 |
20090160411 | FAST VOLTAGE REGULATORS FOR CHARGE PUMPS - A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping. | 06-25-2009 |
20090303803 | Independent Bi-Directional Margin Control Per Level and Independently Expandable Reference Cell Levels for Voltage Mode Sensing - A memory system includes reference level generators that may provide programmable margins, and programmable verify voltage levels. The reference levels may be shifted within a range of voltages with varying differences between reference voltage levels and with different margins and verify levels. | 12-10-2009 |
20090323415 | FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL - A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included. | 12-31-2009 |
20100001765 | SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING - A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node. | 01-07-2010 |
20100002509 | INTEGRATED FLASH MEMORY SYSTEMS AND METHODS FOR LOAD COMPENSATION - Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the load can be tuned to dynamically compensate for variations in supply voltage. In certain aspects, a compensation circuit may employ an operational amplifier configured as a voltage follower. The voltage follower compensates for any variations in supply voltage, forcing a constant voltage drop across the load element(s), thus maintaining a constant load. Other circuits may also be included, such as precharge circuits, clamp circuits, buffer circuits, trimming circuit, and sense amplifier circuits with sensed body effect. System-On-Chip integrated system aspects may include a microcontroller, a mixed IP, and a flash memory system having functionality and blocks that interface and interoperate with each other for load compensation. | 01-07-2010 |
20100067308 | Sub Volt Flash Memory System - Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system. | 03-18-2010 |
20100091567 | Test Circuit and Method for Multilevel Cell Flash Memory - A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system. | 04-15-2010 |
20100142272 | METHOD AND APPARATUS FOR TESTING THE CONNECTIVITY OF A FLASH MEMORY CHIP - In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan cell connected to each bond pad, allowing for rapid connectivity testing of flash memory chips in accordance with testing standards such as the JTAG standard. The invention further includes methods in which the pins and/or memory cells of a flash memory chip are sequentially sent a series of data so as to test the connectivity of portions of the IC. The sequentially-sent data is then retrieved and compared to the original data. Discrepancies between these sets of data thus highlight connectivity problems in the IC. | 06-10-2010 |
20100188138 | Fast Start Charge Pump for Voltage Regulators - A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping. | 07-29-2010 |
20100188900 | ARRAY AND PITCH OF NON-VOLATILE MEMORY CELLS - An array of non-volatile memory cells is arranged in a plurality of rows and columns, wherein each memory cell has at least three terminals: a first terminal for the read out of the signal from the memory cell, a second terminal to which high voltage is supplied during certain operation, and a third terminal to which low voltage is supplied in all operations. The cells in the same column have a common bit line connected to the first terminal of memory cells in the same column. The array comprises a first and second sub arrays of memory cells arranged adjacent to one another in the same row. A first decoder is positioned to one side of the first sub array in the same row as the first sub array. A second decoder is positioned to another side of the second sub array in the same row as the second sub array. A first high voltage line is connected to the second decoder and to only the second terminal of the memory cells in the same row in the first sub array. A second high voltage line, different from the first high voltage line, is connected to the second decoder and to only the second terminal of the memory cells in the same row in the second sub array. A low voltage line is connected to the first decoder and to the thirds terminal of the memory cells in the same row of the first and second sub arrays. | 07-29-2010 |
20100202200 | Power Line Compensation for Flash Memory Sense Amplifiers - In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to multilevel memory sense amplifiers. As another example, compensation can be accomplished by application of a bias voltage to the power supply. Another example is a sense amplifier configured with improved input common mode voltage range. Such sense amplifiers can be two-pair and three-pair sense amplifiers. Further examples of the invention include more simplified sense amplifier configurations, and sense amplifiers having reduced leakage current. | 08-12-2010 |
20100226181 | Array Of Non-volatile Memory Cells Including Embedded Local And Global Reference Cells And System - A non-volatile memory device comprises an array of non-volatile memory cells arranged in a plurality of rows and columns. Each memory cell has a bit terminal for connection to a bit line, a high voltage terminal for connection to a high voltage source, and a low voltage terminal for connection to a low voltage source. The array has a first side adjacent to a first column of memory cells, and a second side opposite the first side, a third side adjacent to a first row of memory cells, and a fourth side opposite the third side. The memory device further comprises a plurality of columns of reference memory cells embedded in the memory array, with a plurality of reference cells in each row of the array of non-volatile memory cells, substantially evenly spaced apart from one another. Each of the reference memory cells is substantially the same as the non-volatile memory cells, and has a bit terminal for connection to a bit line, a high voltage terminal for connection to a high voltage source and a low voltage terminal for connection to a low voltage source. A high voltage decoder is positioned on the first side, and has a plurality of high voltage lines, with each high voltage line connected to the high voltage terminal of the memory cells and reference cells in the same row. A low voltage row decoder is positioned on the second side, and has a plurality of low voltage lines, with each low voltage line connected to the low voltage terminal of the memory cells and reference cells in the same row. A plurality of sense amplifiers are positioned on the third side, with each sense amplifier connected to the bit terminal of one column of non-volatile memory cells and to the bit terminal of a column of reference memory cells. This invention also includes N-of-M selective reference scheme, distributed source line pull down, source line resistance strap compensation, replica-data-pattern current consumption, data current compensation, and bit line voltage error compensation. | 09-09-2010 |
20110018634 | Method and Apparatus for Systematic and Random Variation and Mismatch Compensation for Multilevel Flash Memory Operation - Method and means for random or systematic mismatch compensation for a memory sensing system are disclosed. A sense amplifier includes a bulk voltage source to set the bulk of the sensing transistor to be a voltage different than the voltage driving the sensing transistor. For an NMOS sensing transistor, a triple well is used with the variable bulk voltage. Differential sense amplifiers with various offset compensation are included. Intentional offset creation for useful purpose is also included. | 01-27-2011 |
20110022905 | Test Circuit and Method for Multilevel Cell Flash Memory - A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system. | 01-27-2011 |
20110058425 | Integrated Flash Memory Systems And Methods For Load Compensation - Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the load can be tuned to dynamically compensate for variations in supply voltage. In certain aspects, a compensation circuit may employ an operational amplifier configured as a voltage follower. The voltage follower compensates for any variations in supply voltage, forcing a constant voltage drop across the load element(s), thus maintaining a constant load. Other circuits may also be included, such as precharge circuits, clamp circuits, buffer circuits, trimming circuit, and sense amplifier circuits with sensed body effect. System-On-Chip integrated system aspects may include a microcontroller, a mixed IP, and a flash memory system having functionality and blocks that interface and interoperate with each other for load compensation. | 03-10-2011 |
20110074492 | Charge Pump Circuit And A Novel Capacitor For A Memory Integrated Circuit - A novel capacitor for use in a charge pump circuit has a substrate with a planar surface. A first electrode is in a first plane spaced apart from the planar surface. A second electrode is adjacent to and is spaced apart from the first electrode in the first plane and is capacitively coupled thereto. A third electrode is in a second plane, spaced apart from the first plane and is capacitively coupled to the first electrode. A fourth electrode is adjacent to and spaced apart from the third electrode in the second plane and is capacitively coupled to the third electrode and capacitively coupled to the second electrode. The first and fourth electrodes are electrically connected together and the second and third electrodes are electrically connected together. In addition, a cylindrical shape electrode, and a great wall electrode, and charge pump capacitor-by-pattern-filling is disclosed. A charge pump circuit using the foregoing described capacitor has a plurality of transistors for charging the capacitor and discharging the capacitor thereby increasing the voltage of the charge pump circuit. | 03-31-2011 |
20110080790 | Array Of Non-volatile Memory Cells Including Embedded Local And Global Reference Cells And System - An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a low voltage source. Reference cells, substantially the same as the memory cells, evenly spaced apart, are embedded in the array. A high voltage decoder is on the first side, connected to the memory cells and reference cells in the same row. A low voltage row decoder is on the second side, connected to the memory cells and reference cells in the same row. Sense amplifiers are on the third side, connected to the memory cells and to the reference cells. | 04-07-2011 |
20110090743 | Sub Volt Flash Memory System - Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system. | 04-21-2011 |
20110110170 | Non-volatile memory systems and methods including page read and/or configuration features - A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described. | 05-12-2011 |
20110121799 | Fast Voltage Regulators For Charge Pumps - A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping. | 05-26-2011 |
20110121863 | SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING - A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node. | 05-26-2011 |
20110122693 | FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL - A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included. | 05-26-2011 |
20110169558 | CHARGE PUMP SYSTEMS AND METHODS - Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry. | 07-14-2011 |
20110242921 | Systems And Methods Of Non-Volatile Memory Sensing Including Selective/Differential Threshold Voltage Features - Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them. | 10-06-2011 |
20110255346 | SUB VOLT FLASH MEMORY SYSTEM - Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system. | 10-20-2011 |
20120044774 | SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING - A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node. | 02-23-2012 |
20120074923 | Fast Voltage Regulators For Charge Pumps - A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping. | 03-29-2012 |
20130106391 | Low Voltage, Low Power Bandgap Circuit | 05-02-2013 |
20130107632 | Mixed Voltage Non-volatile Memory Integrated Circuit With Power Saving | 05-02-2013 |
20130126958 | Array Of Split Gate Non-volatile Floating Gate Memory Cells Having Improved Strapping Of The Coupling Gates - An array of non-volatile memory cells with spaced apart first regions extending in a row direction and second regions extending in a column direction, with a channel region defined between each second region and its associated first region. A plurality of spaced apart word line gates each extending in the row direction and positioned over a first portion of a channel region. A plurality of spaced apart floating gates are positioned over second portions of the channel regions. A plurality of spaced apart coupling gates each extending in the row direction and over the floating gates. A plurality of spaced apart metal strapping lines each extending in the row direction and overlying a coupling gate. A plurality of spaced apart erase gates each extending in the row direction and positioned over a first region and adjacent to a floating gate and coupling gate. | 05-23-2013 |
20130148428 | Non-volatile Memory Device And A Method Of Programming Such Device - A non-volatile memory device has a charge pump for providing a programming current and an array of non-volatile memory cells. Each memory cell of the array is programmed by the programming current from the charge pump. The array of non-volatile memory cells is partitioned into a plurality of units, with each unit comprising a plurality of memory cells. An indicator memory cell is associated with each unit of non-volatile memory cells. A programming circuit programs the memory cells of each unit using the programming current, when fifty percent or less of the memory cells of each unit is to be programmed, and programs the inverse of the memory cells of each unit and the indicator memory cell associated with each unit, using the programming current, when more than fifty percent of the memory cells of each unit is to be programmed. | 06-13-2013 |
20130163363 | SYSTEMS AND METHODS OF NON-VOLATILE MEMORY SENSING INCLUDING SELECTIVE/DIFFERENTIAL THRESHOLD VOLTAGE FEATURES - Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them. | 06-27-2013 |
20130187707 | Charge Pump Systems and Methods - Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry. | 07-25-2013 |
20130235664 | Non-Volatile Memory Systems and Methods - A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described. | 09-12-2013 |
20130242672 | Non-volatile Memory Device And A Method Of Operating Same - An array of non-volatile memory cells in a semiconductor substrate of a first conductivity type. Each memory cell comprises first and second regions of a second conductivity type on a surface of the substrate, with a channel region therebetween. A word line overlies one portion of the channel region, is adjacent to the first region, and has little or no overlap with the first region. A floating gate overlies another portion of the channel region, and is adjacent to the first portion and the second region. A coupling gate overlies the floating gate. An erase gate overlies the second region. A bit line is connected to the first region. A negative charge pump circuit generates a negative voltage. A control circuit generates a plurality of control signals in response to receiving a command signal, and applies the negative voltage to the word line of unselected memory cells. | 09-19-2013 |
20140094011 | Self-Aligned Method Of Forming A Semiconductor Memory Array Of Floating Gate Memory Cells With Single Poly Layer - A method of forming a semiconductor memory cell that includes forming the floating and control gates from the same poly layer. Layers of insulation, conductive and second insulation material are formed over a substrate. A trench is formed in the second insulation material extending down to and exposing the conductive layer. Spacers are formed in the trench, separated by a small and defined gap at a bottom of the trench that exposes a portion of the conductive layer. A trench is then formed through the exposed portion of the conductive layer by performing an anisotropic etch through the gap. The trench is filled with third insulation material. Selected portions of the conductive layer are removed, leaving two blocks thereof separated by the third insulation material. | 04-03-2014 |
20140104965 | Non-volatile Memory Array And Method Of Using Same For Fractional Word Programming - A non-volatile memory device that includes N planes of non-volatile memory cells (where N is an integer greater than 1). Each plane of non-volatile memory cells includes a plurality of memory cells configured in rows and columns. Each of the N planes includes gate lines that extend across the rows of the memory cells therein but do not extend to others of the N planes of non-volatile memory cells. A controller is configured to divide each of a plurality of words of data into N fractional-words, and program each of the N fractional-words of each word of data into a different one of the N planes of non-volatile memory cells. The controller uses a programming current and a program time period for the programming, and can be configured to vary the programming current by a factor and inversely vary the program time period by the factor. | 04-17-2014 |
20140140138 | Three-Dimensional Flash Memory System - A three-dimensional flash memory system is disclosed. | 05-22-2014 |
20140198568 | NON-VOLATILE MEMORY SYSTEMS AND METHODS - A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described. | 07-17-2014 |
20140264539 | Non-volatile Memory Cells With Enhanced Channel Region Effective Width, And Method Of Making Same - A memory device array with spaced apart parallel isolation regions formed in a semiconductor substrate, with an active region between each pair of adjacent isolation regions. Each isolation region includes a trench formed into the substrate surface and an insulation material formed in the trench. Portions of a top surface of the insulation material are recessed below the surface of the substrate. Each active region includes a column of memory cells each having spaced apart first and second regions with a channel region therebetween, a floating gate over a first channel region portion, and a select gate over a second channel region portion. The select gates are formed as continuous word lines extending perpendicular to the isolation regions and each forming the select gates for one row of the memory cells. Portions of each word line extend down into the trenches and disposed laterally adjacent to sidewalls of the trenches. | 09-18-2014 |
20140269049 | Hybrid Chargepump And Regulation Means And Method For Flash Memory Device - A hybrid charge pump and control circuit for use in a memory device is disclosed. | 09-18-2014 |
20140269061 | High Speed Sensing For Advanced Nanometer Flash Memory Device - Improved sensing circuits and improved bit line layouts for advanced nanometer flash memory devices are disclosed. | 09-18-2014 |
20140269098 | DYNAMIC PROGRAMMING OF ADVANCED NANOMETER FLASH MEMORY - An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed. | 09-18-2014 |
20140281611 | POWER MANAGEMENT FOR A MEMORY DEVICE - An improved method and apparatus for performing power management in a memory device is disclosed. | 09-18-2014 |
20140282348 | TRANSISTOR DESIGN FOR USE IN ADVANCED NANOMETER FLASH MEMORY DEVICES - Improved PMOS and NMOS transistor designs for sensing circuitry use in advanced nanometer flash memory devices are disclosed. | 09-18-2014 |
20140293724 | SYSTEMS AND METHODS OF NON-VOLATILE MEMORY SENSING INCLUDING SELECTIVE/DIFFERENTIAL THRESHOLD VOLTAGE FEATURES - Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them. | 10-02-2014 |