Patent application number | Description | Published |
20140101516 | Encoding and Decoding Data to Accommodate Memory Cells Having Stuck-At Faults - A data storage system includes a memory circuit that has memory cells and a control circuit that is operable to receive data bits provided for storage in the memory cells. The control circuit is operable to receive a first matrix. Each row of the first matrix corresponds to a unique one of the data bits. The control circuit is operable to generate a second matrix having only the rows of the first matrix that correspond to the data bits provided for storage in a subset of the memory cells having stuck-at faults. The control circuit is operable to generate a third matrix having linearly independent columns of the second matrix. The control circuit is operable to encode the data bits to generate encoded data bits and redundant bits using the third matrix. | 04-10-2014 |
20140101517 | Encoding and Decoding Redundant Bits to Accommodate Memory Cells Having Stuck-At Faults - A data storage system has a memory circuit that comprises memory cells and a control circuit that receives data bits provided for storage in the memory cells. The control circuit encodes the data bits to generate a first set of redundant bits and encoded data bits, such that the encoded data bits selected for storage in a first subset of the memory cells with first stuck-at faults have digital values of corresponding ones of the first stuck-at faults. The control circuit encodes the first set of redundant bits to generate a second set of redundant bits. The control circuit performs logic functions on the second set of redundant bits and the encoded data bits to generate a third set of redundant bits, such that redundant bits in the third set of redundant bits selected for storage in a second subset of the memory cells with second stuck-at faults have digital values of corresponding ones of the second stuck-at faults. | 04-10-2014 |
20140164821 | Techniques For Encoding and Decoding Using a Combinatorial Number System - A data storage system includes a memory circuit having memory cells and a control circuit. The control circuit is operable to receive data bits provided for storage in the memory cells. A subset of the memory cells have predetermined stuck-at faults. The control circuit is operable to compute a binomial coefficient for each of the predetermined stuck-at faults based on a bit position of a corresponding one of the predetermined stuck-at faults within the memory cells. The control circuit is operable to add together the binomial coefficients to generate an encoded number using a combinatorial number system. The control circuit is operable to generate a first set of redundant bits that indicate the encoded number. The first set of redundant bits are used to decode bits read from the memory cells to regenerate the data bits. | 06-12-2014 |
20140169492 | COMMUNICATION SYSTEM WITH COMPUND CODING MECHANISM AND METHOD OF OPERATION THEREOF - A communication system includes: an antenna for receiving a receiver signal for communicating a transmitter signal corresponding to the receiver signal over transmission channels according to a polar coding scheme; a communication unit including: an arrangement module for generating a sequenced-signal based on the receiver signal according to a permutation mechanism; and a decoder module for determining a communication content based on the sequenced-signal for communicating the communication content intended by the transmitter signal with a device. | 06-19-2014 |
20140208183 | METHOD AND SYSTEM FOR ENCODING AND DECODING DATA USING CONCATENATED POLAR CODES - A concatenated encoder is provided that includes an outer encoder, a symbol interleaver and a polar inner encoder. The outer encoder is configured to encode a data stream using an outer code to generate outer codewords. The symbol interleaver is configured to interleave symbols of the outer codewords and generate a binary stream. The polar inner encoder is configured to encode the binary stream using a polar inner code to generate an encoded stream. A concatenated decoder is provided that includes a polar inner decoder, a symbol de-interleaver and an outer decoder. The polar inner decoder is configured to decode an encoded stream using a polar inner code to generate a binary stream. The symbol de-interleaver is configured to de-interleave symbols in the binary stream to generate outer codewords. The outer decoder is configured to decode the outer codewords using an outer code to generate a decoded stream. | 07-24-2014 |
20150016563 | COMPUTING SYSTEM WITH COORDINATED MULTIPLE-ACCESS MECHANISM AND METHOD OF OPERATION THEREOF - A computing system includes: an interface configured to communicate a coordination profile for coordinating a second transmitter device with a first transmitter device; and a unit, coupled to the interface, configured to generate a first encoded message using a message polarization mechanism based on the coordination profile for coordinating the first encoded message with a second encoded message concurrently transmitting through the second transmitter device. | 01-15-2015 |