Patent application number | Description | Published |
20130265732 | INTERCHIP COMMUNICATION USING A DIELECTRIC WAVEGUIDE - An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide. | 10-10-2013 |
20130265733 | INTERCHIP COMMUNICATION USING AN EMBEDDED DIELECTRIC WAVEGUIDE - An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide. | 10-10-2013 |
20130265734 | INTERCHIP COMMUNICATION USING EMBEDDED DIELECTRIC AND METAL WAVEGUIDES - An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide. | 10-10-2013 |
20140103508 | ENCAPSULATING PACKAGE FOR AN INTEGRATED CIRCUIT - An apparatus is provided. An integrated circuit or IC is secured to a package housing. The IC has an IC substrate and an epitaxial layer formed over the substrate and having an active region and an upper surface. The upper surface is substantially exposed, and bond pads are formed over the epitaxial layer. Bond fixtures are each secured to and in electrical contact with at least one of the bond pads and with the package housing. A fill formed over at least a portion of the epitaxial layer so as to substantially encapsulate the active region, where the fill has a dielectric constant that is substantially equivalent to the dielectric constant of air. Additionally, the fill has a thickness, where the thickness is sufficiently large enough to confine parasitics of the active region at the upper surface of the epitaxial layer. | 04-17-2014 |
20140245598 | FABRICATING A POWER SUPPLY CONVERTER WITH LOAD INDUCTOR STRUCTURED AS HEAT SINK - A method for fabricating a power supply converter comprises a load inductor wrapped by a metal sleeve structured to transform the inductor into a heat sink positioned to deposit layers of solder paste on a sleeve surface and on the inductor leads. A metal carrier having a portion of a first thickness and portions of a greater second thickness is placed on the solder layers of the inductor. The carrier portion of first thickness is aligned with the inductor sleeve. The carrier portions of second thickness are aligned with the inductor leads. A sync and a control FET are placed side-by-side on solder layers deposited on the carrier portion of first thickness opposite the inductor sleeve. Reflowing is preformed and the solder layers are solidified. The FETs, the carrier and the inductor become integrated and the un-soldered surfaces of the FETs and the carrier portions of second thickness become coplanar. | 09-04-2014 |
20140247562 | DC-DC CONVERTER VERTICALLY INTEGRATED WITH LOAD INDUCTOR STRUCTURED AS HEAT SINK - An apparatus includes a heat-generating component and a thermally inert component positioned in close proximity to the heat-generating component. A housing for the thermally inert component is in touch with the heat-generating component and is structured to transform the thermally inert component into a heat sink for the heat-generating component | 09-04-2014 |
Patent application number | Description | Published |
20100171543 | PACKAGED POWER SWITCHING DEVICE - A packaged switching device for power applications includes at least one pair of power MOSFET transistor dies connected between upper and lower power source rail leads, a high side one of the pair of MOSFET transistor dies being connected to the upper power source rail lead and a low side one of the pair of MOSFET transistor dies being connected to the lower power source rail lead. At least one of the MOSFET transistor dies is configured for vertical current flow therethrough and has a source electrode at a backside thereof. | 07-08-2010 |
20100176508 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF ASSEMBLY THEREOF - A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip structure; and a molding material partially encapsulating the assembly, wherein an upper surface of the heat sink is exposed through the molding material. | 07-15-2010 |
20110074007 | THERMALLY ENHANCED LOW PARASITIC POWER SEMICONDUCTOR PACKAGE - A method and structure for a dual heat dissipating semiconductor device. A method includes attaching a drain region on a first side of a die, such as a power metal oxide semiconductor field effect transistor (MOSFET) to a first leadframe subassembly. A source region and a gate region on a second side of the die are attached to a second leadframe subassembly. The first leadframe subassembly is attached to a third leadframe subassembly, then the device is encapsulated or otherwise packaged. An exposed portion of the first leadframe subassembly provides an external heat sink for the drain region, and the second leadframe subassembly provides external heat sinks for the source region and the gate region, as well as output leads for the gate region. The third leadframe subassembly provides output leads for the drain region. | 03-31-2011 |
20110095411 | Wirebond-less Semiconductor Package - A wirebond-less packaged semiconductor device includes a plurality of I/O contacts, at least one semiconductor die, the semiconductor die having a bottom major surface and a top major surface, the top major surface having at least two electrically isolated electrodes, and a conductive clip system disposed over the top major surface, the clip system comprising at least two electrically isolated sections coupling the electrodes to respective I/O contacts. | 04-28-2011 |
20110163454 | ELECTROLESS PLATING A NICKLE LAYER AND A GOLD LAYER IN A SEMICONDUCTOR DEVICE - A method and resulting device for maintaining non-porous nickel layer at a nickel/passivation interface of a semiconductor device in a nickel/gold electroless plating process. The method can include determining a thickness of a gold layer of the semiconductor device; determining an electroless plating rate and plating time of the gold layer to reach the determined thickness; determining a thickness of nickel under the gold layer to maintain the non-porous nickel layer at the nickel/passivation interface at a termination of an electroless gold plating process; and following the determinations, sequentially electroless plating of each of the nickel layer and gold layer on the device layer to the determined thicknesses. | 07-07-2011 |
20120015483 | Semiconductor Device Package and Method of Assembly Thereof - A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip structure; and a molding material partially encapsulating the assembly, wherein an upper surface of the heat sink is exposed through the molding material. | 01-19-2012 |
Patent application number | Description | Published |
20130087900 | Thermally Enhanced Low Parasitic Power Semiconductor Package - A semiconductor device includes a source region, a gate region and a drain region. A first leadframe subassembly is coupled to the drain region. on a second side of the die are attached to a second leadframe subassembly. A second leadframe subassembly has a first portion electrically coupled with the source region and a second portion electrically coupled with the gate region. The first leadframe subassembly is attached to a third leadframe subassembly. A die is interposed between the first leadframe subassembly and the second leadframe subassembly. The height of the third leadframe subassembly provides a standoff for a distance between the first leadframe subassembly and the second leadframe subassembly. | 04-11-2013 |
20140063744 | Vertically Stacked Power FETS and Synchronous Buck Converter Having Low On-Resistance - A power FET ( | 03-06-2014 |
20140240062 | Dielectric Waveguide with Deformable Interface Surface - A dielectric wave guide (DWG) has a dielectric core member that has a first dielectric constant value. A cladding surrounding the dielectric core member has a second dielectric constant value that is lower than the first dielectric constant. A mating end of the DWG is configured for mating with a second DWG having a matching non-planar shaped mating end. A deformable material is disposed on the surface of the mating end of the DWG, such that when mated to a second DWG, the deformable material fills a gap region between the mating ends of the DWG and the second DWG | 08-28-2014 |
20140240187 | Dielectric Waveguide with Non-planar Interface Surface - A dielectric wave guide (DWG) has a dielectric core member having that has a first dielectric constant value. A cladding surrounding the dielectric core member has a second dielectric constant value that is lower than the first dielectric constant. A mating end of the DWG is configured in a non-planer shape for mating with a second DWG having a matching non-planar shaped mating end. | 08-28-2014 |
20140285277 | Dielectric Waveguide Manufactured Using Printed Circuit Board Technology - A dielectric waveguide may be manufactured by forming a set of parallel channels in a planar sheet that has a lower dielectric constant value. The set of channels is then filled with a material having a higher dielectric constant value. The planar sheet is sliced into a plurality of strips that each contain one or more of the channels. | 09-25-2014 |
20140285281 | Coupler to Launch Electromagnetic Signal from Microstrip to Dielectric Waveguide - A metallic waveguide is mounted on a multilayer substrate. The metallic waveguide has an open end formed by a top, bottom and sides configured to receive a core member of a dielectric waveguide, and an opposite tapered end formed by declining the top of the metallic waveguide past the bottom of the metallic waveguide and down to contact the multilayer substrate. A pinnacle of the tapered end is coupled to the ground plane element, and the bottom side of the metallic waveguide is in contact with the multiplayer substrate and coupled to the microstrip line. | 09-25-2014 |
20140285289 | Horn Antenna for Launching Electromagnetic Signal from Microstrip to Dielectric Waveguide - A horn antenna is formed within a multilayer substrate and has a generally trapezoidal shaped top plate and bottom plate formed in different layers of the multilayer substrate. A set of densely spaced vias form two sidewalls of the horn antenna by coupling adjacent edges of the top plate and the bottom plate. The horn antenna has a narrow input end and a wider flare end. A microstrip line is coupled to the top plate and a ground plane element is coupled to the bottom plate at the input end of the horn antenna. | 09-25-2014 |
20140285290 | Dielectric Waveguide Combined with Electrical Cable - A communication cable includes one or more conductive elements surrounded by a dielectric sheath. The sheath member has a first dielectric constant value. A dielectric core member is placed longitudinally adjacent to and in contact with an outer surface of the sheath member. The core member has a second dielectric constant value that is higher than the first dielectric constant value. A cladding surrounds the sheath member and the dielectric core member. The cladding has a third dielectric constant value that is lower than the second dielectric constant value. A dielectric wave guide is formed by the dielectric core member surrounded by the sheath and the cladding. | 09-25-2014 |
20140285291 | Dielectric Waveguide with Multiple Channels - A multichannel dielectric wave guide includes a set of dielectric core members that have a length and a cross section shape that is approximately rectangular, The core members have a first dielectric constant value. A cladding surrounds the set of dielectric core members and has a second dielectric constant value that is lower than the first dielectric constant. | 09-25-2014 |
20140285292 | Dielectric Waveguide with Corner Shielding - A dielectric wave guide (DWG) has a longitudinal dielectric core member. The core member has a first dielectric constant value. A cladding surrounds the dielectric core member and has a second dielectric constant value that is lower than the first dielectric constant. A portion of the DWG is configured as a corner having a radius. A conductive layer formed on an outer radius of the corner. | 09-25-2014 |
20140285293 | Dielectric Waveguide with RJ45 Connector - A communication cable includes a dielectric wave guide (DWG) that has a dielectric core member that has a first dielectric constant value and a cladding surrounding the dielectric core member that has a second dielectric constant value that is lower than the first dielectric constant. An RJ45 compatible connector is attached to a mating end of the DWG. The RJ45 connector is configured to retain a complimentary coupling mechanism on a mating end of a second DWG. | 09-25-2014 |
20140285294 | Retractable Dielectric Waveguide - A rotatable coupler for dielectric wave guides is described. A first dielectric wave guide (DWG) has an interface surface at a one end of the DWG. A second DWG has a matching interface surface at an end of the second DWG. A rotatable coupling mechanism is coupled to the two DWG ends and is configured to hold the interface surface of the first DWG in axial alignment with the interface surface of the second DWG while allowing the interface surface of the first DWG to rotate axially with respect to the interface surface of the second DWG. | 09-25-2014 |
20140287701 | Integrated Circuit with Dipole Antenna Interface for Dielectric Waveguide - An electronic device has a multilayer substrate that has an interface surface configured for interfacing to a dielectric waveguide. A conductive layer on the substrate is etched to form a dipole antenna disposed adjacent the interface surface to provide coupling to the dielectric waveguide. A reflector structure is formed in the substrate adjacent the dipole antenna opposite from the interface surface. | 09-25-2014 |
20140287702 | Dielectric Waveguide with Director Elements - A system includes an electronic device coupled to a mating end of a dielectric wave guide (DWG). The electronic device has a multilayer substrate that has an interface surface configured for interfacing to the mating end of the DWG. A conductive layer is etched to form a dipole antenna disposed adjacent the interface surface. A reflector structure is formed in the substrate adjacent the dipole antenna opposite from the interface surface. A set of director elements is embedded in the mating end of the DWG. Specific spacing is maintained between the dipole antenna and the set of director elements. | 09-25-2014 |
20140287703 | Integrated Circuit with Antenna for Dielectric Waveguide - A system includes an integrated circuit that has a substrate with a top surface and a bottom surface. Semiconductor circuitry is including a radio frequency (RF) amplifier configured to produce an RF signal or an RF receiver configured to receive an RF signal is formed on the top surface of the substrate. A through-substrate via is coupled to an output of the RF amplifier. A metalized antenna formed on the bottom surface of the substrate is coupled to the through-substrate via. The metalized antenna is configured to launch an electromagnet wave representative of the RF signal into a dielectric waveguide (DWG) when the DWG is coupled to the bottom side of the substrate. | 09-25-2014 |
20140306332 | Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips - A packaged multi-output converter ( | 10-16-2014 |
20140368301 | Dielectric Waveguide with Conductive Coating - A dielectric waveguide (DWG) has a dielectric core member that has a length L and an oblong cross section. The core member has a first dielectric constant value. A dielectric cladding surrounds the dielectric core member; the cladding has a second dielectric constant value that is lower than the first dielectric constant. A conductive shield layer surrounds a portion of the dielectric cladding. | 12-18-2014 |