Herbeck
Gilbert Herbeck, Livermore, CA US
Patent application number | Description | Published |
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20140203850 | POWER MANAGED SYNCHRONIZERS FOR ASYNCHRONOUS INPUT SIGNALS - Clock-gated synchronizer circuitry includes a number of clock-gated synchronizers, with each clock-gated synchronizer configured to synchronize an asynchronous input signal into a clock domain. The circuitry also includes a clock gater coupled to a clock input of the plurality of clock-gated synchronizers and coupled to receive an input clock and an enable signal. The clock gater is configured to provide the input clock to the plurality of synchronizers only upon receiving the enable signal. The circuitry also includes an enable generator coupled to receive the asynchronous input signals and configured to generate the enable signal for the clock gater responsive to the asynchronous input signals. | 07-24-2014 |
20140211906 | CLOCK SIGNAL RATE MANAGEMENT CIRCUIT - A prescalar counter may be configured to repeatedly increment once for each cycle of a clock signal at a first frequency and reset upon reaching a threshold counter value. The prescalar counter may also include toggling logic configured to generate a clock pulse of a global time base signal upon each reset of the prescalar counter. A frequency divider may be configured to divide the global time base signal into a plurality of separate clock signals with each of the separate clock signals having a different frequency. The frequency divider may also be configured to provide, to each of a plurality of timers, one of the separate clock signals. | 07-31-2014 |
Gilbert H. Herbeck, Livermore, CA US
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20140310443 | Shims for Processor Interface - An interface unit configured to perform transfers between a processor and one or more peripheral devices is disclosed. A system includes a processor, a number of devices (e.g., peripheral devices), and an interface unit coupled therebetween. The interface unit includes FIFOs for storing data transmitted to or received from the devices by the processor. The interface unit may access data from a device responsive to a request from the processor. The data may be loaded into a FIFO according to transfer parameters controlled by the device. After the data has been received by the FIFO, the interface unit may generate an interrupt to the processor. Data may then be transferred from the interface unit to the processor according to transfer parameters controlled by the processor. The interface unit may thus homogenize a processor interface to a number of different devices. | 10-16-2014 |
20140310540 | Interrupt Based Power State Management - A method and apparatus for power managed interrupt handling is disclosed. In one embodiment, a system includes one or more agents that may invoke an interrupt request. An interrupt controller is configured to receive and process the interrupt requests. When idle, the interrupt controller may be placed in a low power state. The system also includes an interrupt power control circuit coupled to receive interrupt request indications from each of the one or more agents that may invoke interrupts. The interrupt power control circuit is configured to assert a wakeup signal responsive to receiving an indication of an interrupt request from one of the agents. If the interrupt controller is in a low power state, it may exit the state and resume operation in an active state responsive to assertion of the wakeup signal. | 10-16-2014 |
20140310549 | FIFO Clock and Power Management - An apparatus and method for saving power when transmitting data across a clock boundary is disclosed. In one embodiment, an apparatus includes a FIFO coupled to receive data from circuitry in a first clock domain and output data to circuitry in a second clock domain. A first control circuit is responsible for writing data into the FIFO. A second control circuit is responsible for reading data from the FIFO. If the amount of data in the FIFO exceeds a first threshold, a power management circuit may place the first control circuit in a low power state. The second control circuit may monitor the amount of data in the FIFO. If the amount of data in the FIFO falls below a second threshold, it may assert an indication to the power management circuit. Thereafter, the power management circuit may cause the first control circuit to exit the low power state. | 10-16-2014 |
Ing. Lars Herbeck, Feldheim DE
Patent application number | Description | Published |
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20090008836 | METHOD FOR PRODUCING FIBER-REINFORCED PLASTIC COMPONENTS - For producing a joined-together fiber composite component in which mutually adjacent regions ( | 01-08-2009 |
Lars Herbeck, Veltheim DE
Patent application number | Description | Published |
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20100289188 | METHOD FOR PRODUCING A FIBRE-COMPOSITE COMPONENT - The invention relates to a method for producing a fibre composite component, comprising the steps: introduction of a first body ( | 11-18-2010 |
Lars Herbeck, Heidenheim DE
Patent application number | Description | Published |
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20090311506 | INDUCTION-ASSISTED PRODUCTION METHOD - In a production method for producing molded articles from fiber composites, superparamatic particles are selected which become coupled to an external alternating magnetic field. These superparamagnatic particles are added to a resin portion of a strip-shaped starting material further comprising reinforcing fibers. The strip-shaped starting material is then continuously advanced, and, while being advanced, heated by coupling-in an external alternating magnetic field to which the superparamagnatic particles in the resin portion become coupled. Next, the heated starting material is continuously molded into a molded article; and the resin portion in the molded particle is cured. | 12-17-2009 |
Lars Herbeck, Fedlheim DE
Patent application number | Description | Published |
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20080274322 | Fiber Composite Component and Method for the Production of a Fiber Composite Component - A fiber composite component comprising at least two, first and second partial elements ( | 11-06-2008 |