Patent application number | Description | Published |
20090033385 | Glitch Reduced Delay Lock Loop Circuits and Methods for Using Such - Various embodiments of the present invention provide delay lock loop circuits. Such delay lock loop circuits include two or more delay stages that each include a plurality of selectable delay elements. A reference signal drives an input of the first delay stage, and the first delay stage provides a first output. The first output drives an input of the second delay stage, and the second delay stage provides a second output. The circuits further include a first selector register that is associated with the first delay stage. A value maintained in the first selector register determines a number of the selectable delay elements utilized in the first delay stage. Modification of the value maintained in the first selector register is synchronized to the first output. The circuits further include a second selector register associated with the second delay stage. A value maintained in the second selector register determines a number of the selectable delay elements utilized in the second delay stage. Modification of the value maintained in the second selector register is synchronized to the second output. | 02-05-2009 |
20090033386 | Delay Lock Loop Circuits Including Glitch Reduction and Methods for Using Such - Various systems and methods for delaying one signal in relation to another are disclosed. As one example, a delay lock loop circuit is discussed that includes at least a first delay stage and a second delay stage, each including a plurality of selectable delay elements. The delay stages are configured such that a gated reference signal drives an input of the first delay stage, and a first output from the first delay stage drives an input of the second delay stage. The circuits further include a unified selector register that is associated with both the first delay stage and the second delay stage. A value maintained in the unified selector register determines a number of the selectable delay elements utilized in the first delay stage and a number of the selectable delay elements utilized in the second delay stage. In operation, modification of the value maintained in the unified selector register is synchronized to the reference signal. A reference signal gate is included that receives the reference signal and provides the gated reference signal. The gated reference signal is substantially the reference signal modified such that the gated reference signal is not asserted when modification of the unified selector register is enabled. | 02-05-2009 |
20090033387 | Master Slave Delay Locked Loops and Uses Thereof - Various systems and methods for delaying a signal relative to another signal are disclosed. As one example, a delay lock loop circuit is disclosed that includes at least two delay stages. Each of the aforementioned delay stages include a plurality of selectable delay elements. Such selectable delay elements may be, but are not limited to, a plurality of single input buffers, and a plurality of multiple input logic gates. Further, a first of the delay stages is selectably driven by one of a first signal and a reference signal, and the stage provides a first stage output. A second of the delay stages is selectably driven by one of a second signal and the first stage output, and the stage provides a second stage output. The circuit further includes a mode signal that has at least two states. One of the two states causes the first signal to drive the first delay stage and the second signal to drive the second delay stage, and the other state causes the reference signal to drive the first delay stage and the first stage output to drive the second delay stage. In some cases, the first state is referred to as a slave state and the second state is referred to as a master state. In addition, the circuit includes a feedback loop. | 02-05-2009 |
20090033388 | Systems and Methods for Reduced Area Delay Locked Loop - Various systems and methods for signal synchronization are disclosed. For example, some embodiments of the present invention provide methods for reduced area delay signal timing. Such methods include providing a delay lock loop circuit with a plurality of selectable delay elements. The methods further include operating the delay lock loop circuit in a first mode where a program number is established in relation to a reference frequency. The program number corresponds to a number of the plurality of selectable delay elements used to establish a first delay time at the reference frequency. The program number is multiplied by a multiplicand, and the product of the multiplication is used while operating the delay lock loop circuit in a second mode to select the number of delay elements utilized in delaying an input signal. In the second mode, an input signal is delayed by a second delay time that is approximately the first delay time multiplied by the multiplicand. | 02-05-2009 |
20090051390 | GLITCH REDUCED COMPENSATED CIRCUITS AND METHODS FOR USING SUCH - Various embodiments of the present invention provide systems and methods for glitch reduced circuits. As one example, a glitch reduced, variable width driver circuit is disclosed. Such circuits include a data output, and at least two transistors that each includes a gate, a first leg and a second leg. The gate of the first transistor is electrically coupled to a first combined control signal, and the gate of the second transistor is electrically coupled to a second combined control signal. The first leg of the first transistor and the first leg of the second transistor are electrically coupled to a power source, and the second leg of the first transistor and the second leg of the second transistor are electrically coupled to an output signal. The circuits further include a control circuit that combines a first control signal with the data output to create the first combined control signal, and combines a second control signal with the data output to create the second combined control signal. | 02-26-2009 |
20090177451 | APPARATUS AND METHOD FOR ACCELERATING SIMULATIONS AND DESIGNING INTEGRATED CIRCUITS AND OTHER SYSTEMS - A method of accelerating a Monte Carlo (MC) simulation for a system including a first component having a first input parameter and a second component having a second input parameter. The simulation model provided includes a first component model including a first model parameter corresponding to the first input parameter and a second component model having a second model parameter corresponding to the second input parameter. A first acceleration factor for the first component and a second acceleration factor for the second component are calculated based on at least the respective number of instances. A first scaled distribution is computed from the first distribution and a second scaled distribution is computed from the second distribution based on the respective acceleration factors. The MC simulation for the system is run, wherein values for the first model parameter value and second model parameter value are obtained based on the respective scaled distributions. | 07-09-2009 |