Patent application number | Description | Published |
20080198031 | METHOD OF ASSEMBLING SEMICONDUCTOR DEVICES WITH LEDS - Methods of forming integrated circuit packages having an LED molded into the package, and the integrated circuit package formed thereby. An integrated circuit including one or more semiconductor die, passive components and an LED may be assembled on a panel. The one or more semiconductor die, passive components and LED may all then be encapsulated in a molding compound, and the integrated circuits then singularized to form individual integrated circuit packages. The integrated circuits are cut from the panel so that a portion of the lens of the LED is severed during the singularization process, and an end of the lens remaining within the package lies flush with an edge of the package to emit light outside of the package. | 08-21-2008 |
20080237887 | SEMICONDUCTOR DIE STACK HAVING HEIGHTENED CONTACT FOR WIRE BOND - A semiconductor device is disclosed including die bond pads which are heightened to allow wire bonding of offset stacked die even in tight offset configurations. After a first die is affixed to a substrate, one or more layers of an electrical conductor may be provided on some or all of the die bond pads of the first substrate to raise the height of the bond pads. The conductive layers may for example be conductive balls deposited on the die bond pads of the first substrate using a known wire bond capillary. Thereafter, a second die may be added, and wire bonding of the first die may be accomplished using a known wire bond capillary mounting a wire bond ball on a raised surface of a first semiconductor die bond pad. | 10-02-2008 |
20080242076 | METHOD OF MAKING SEMICONDUCTOR DIE STACK HAVING HEIGHTENED CONTACT FOR WIRE BOND - A method of making a semiconductor device is disclosed including die bond pads which are heightened to allow wire bonding of offset stacked die even in tight offset configurations. After a first die is affixed to a substrate, one or more layers of an electrical conductor may be provided on some or all of the die bond pads of the first substrate to raise the height of the bond pads. The conductive layers may for example be conductive balls deposited on the die bond pads of the first substrate using a known wire bond capillary. Thereafter, a second die may be added, and wire bonding of the first die may be accomplished using a known wire bond capillary mounting a wire bond ball on a raised surface of a first semiconductor die bond pad. | 10-02-2008 |
20080303166 | TWO-SIDED SUBSTRATE LEAD CONNECTION FOR MINIMIZING KERF WIDTH ON A SEMICONDUCTOR SUBSTRATE PANEL - A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages. | 12-11-2008 |
20080305306 | SEMICONDUCTOR MOLDED PANEL HAVING REDUCED WARPAGE - A panel is disclosed on which a plurality of integrated circuit package outlines may be fabricated within a plurality of process tools. The panel includes recessed portions in the exposed surfaces of the molding compound and/or the substrate. The recesses relieve stress resulting from disparate coefficients of expansion between the substrate and molding compound applied to the substrate around the integrated circuits. In embodiments, the recesses may be formed as lines scored into the surface of the molding compound or substrate. Alternatively, the recesses may be formed in the solder mask on the substrate during a process for applying the solder mask, or the recesses may be formed in the molding compound during the encapsulation process. | 12-11-2008 |
20080305576 | METHOD OF REDUCING WARPAGE IN SEMICONDUCTOR MOLDED PANEL - A panel is disclosed on which a plurality of integrated circuit package outlines may be fabricated within a plurality of process tools. The panel includes recessed portions in the exposed surfaces of the molding compound and/or the substrate. The recesses relieve stress resulting from disparate coefficients of expansion between the substrate and molding compound applied to the substrate around the integrated circuits. In embodiments, the recesses may be formed as lines scored into the surface of the molding compound or substrate. Alternatively, the recesses may be formed in the solder mask on the substrate during a process for applying the solder mask, or the recesses may be formed in the molding compound during the encapsulation process. | 12-11-2008 |
20080305577 | METHOD OF MINIMIZING KERF WIDTH ON A SEMICONDUCTOR SUBSTRATE PANEL - A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages. | 12-11-2008 |
20090001365 | MEMORY CARD FABRICATED USING SIP/SMT HYBRID TECHNOLOGY - A portable memory card formed from a multi-die assembly, and methods of fabricating same, are disclosed. One such multi-die assembly includes an LGA SiP semiconductor package and a leadframe-based SMT package both affixed to a PCB. The multi-die assembly thus formed may be encased within a standard lid to form a completed portable memory card, such as a standard SD™ card. Test pads on the LGA SiP package, used for testing operation of the package after it is fabricated, may also be used for physically and electrically coupling the LGA SiP package to the PCB. | 01-01-2009 |
20090001534 | TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASED PACKAGE - A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe. | 01-01-2009 |
20090001552 | SEMICONDUCTOR PACKAGE HAVING THROUGH HOLES FOR MOLDING BACK SIDE OF PACKAGE - A portable memory card and methods of manufacturing same are disclosed. The portable memory includes a substrate having a plurality of holes formed therein. During the encapsulation process, mold compound flows over the top surface of the substrate, through the holes, and down into a recessed section formed in the bottom mold cap plate to form a projection of mold compound on the bottom surface of the substrate. | 01-01-2009 |
20090001610 | SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER - A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die. | 01-01-2009 |
20090004776 | METHOD OF FABRICATING A MEMORY CARD USING SIP/SMT HYBRID TECHNOLOGY - A portable memory card formed from a multi-die assembly, and methods of fabricating same, are disclosed. One such multi-die assembly includes an LGA SiP semiconductor package and a leadframe-based SMT package both affixed to a PCB. The multi-die assembly thus formed may be encased within a standard lid to form a completed portable memory card, such as a standard SD™ card. Test pads on the LGA SiP package, used for testing operation of the package after it is fabricated, may also be used for physically and electrically coupling the LGA SiP package to the PCB. | 01-01-2009 |
20090004781 | METHOD OF FABRICATING A SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER - A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die. | 01-01-2009 |
20090004782 | METHOD OF FABRICATING A TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASED PACKAGE - A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe. | 01-01-2009 |
20090004785 | METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE HAVING THROUGH HOLES FOR MOLDING BACK SIDE OF PACKAGE - A portable memory card and methods of manufacturing same are disclosed. The portable memory includes a substrate having a plurality of holes formed therein. During the encapsulation process, mold compound flows over the top surface of the substrate, through the holes, and down into a recessed section formed in the bottom mold cap plate to form a projection of mold compound on the bottom surface of the substrate. | 01-01-2009 |
20090065902 | METHOD OF FORMING A SEMICONDUCTOR DIE HAVING A SLOPED EDGE FOR RECEIVING AN ELECTRICAL CONNECTOR - A method of forming a low profile semiconductor package, and a semiconductor package formed thereby, is disclosed. The semiconductor die is formed with one or more sloped edges on which electrically conductive traces may be deposited to allow the semiconductor die to be coupled to another die and/or a substrate on which the die is mounted. Depositing the electrical traces directly on the surface and sloped edge of the die allows the die to be electrically coupled without bond wires, thereby allowing a reduction in the overall thickness of the package. | 03-12-2009 |
20090085231 | METHOD OF REDUCING MEMORY CARD EDGE ROUGHNESS BY PARTICLE BLASTING - A method of forming a semiconductor package with smooth edges, and a semiconductor package formed thereby is disclosed. In embodiments, after encapsulation, a panel of semiconductor packages may undergo a first cutting process which cuts the curvilinear edges of the packages. Next, the partially singulated panel of packages may undergo an abrasion process for smoothing the cut curvilinear edges. The abrasion process may occur by forcing abrasive particles over the jagged side edges of a semiconductor package as a result of a pressure differential above and below the semiconductor packages. Upon completion of the abrasive process, a second cutting process may be performed which cuts along straight edges and singulates the respective packages from the panel. | 04-02-2009 |
20090085232 | METHOD OF REDUCING MEMORY CARD EDGE ROUGHNESS BY EDGE COATING - A method of forming a semiconductor package with smooth edges, and a semiconductor package formed thereby is disclosed. In embodiments, after encapsulation, the semiconductor packages may be at least partially singulated from the panel by making one or more cuts through the panel to define one or more edges of the semiconductor package. The one or more edges may be smoothed by applying a laminate to the edges. The edges receiving the laminate may include any edge between a top and bottom surface of the package. | 04-02-2009 |
20090134502 | LEADFRAME BASED FLASH MEMORY CARDS - A leadframe design for forming leadframe-based semiconductor packages having curvilinear shapes is disclosed. The leadframes may each include one or more curvilinear slots corresponding to curvilinear edges in the finished and singulated semiconductor package. After encapsulation, the integrated circuit packages on the panel may be singulated by cutting the integrated circuits from the leadframe panel into a plurality of individual integrated circuit packages. The slots in the leadframe advantageously allow each leadframe to be singulated using a saw blade making only straight cuts. | 05-28-2009 |
20090165294 | LOW PROFILE WIRE BONDED USB DEVICE - A low profile USB flash memory device, and methods of forming same, are disclosed. The USB flash memory device includes an integrated circuit memory portion and a USB connector. The memory portion and the USB connector may be integrally formed on the same substrate. The USB flash memory device includes a substrate on which is mounted one or more flash memory die, a controller die, passive components and an LED for indicating when the memory is being accessed. In contrast to prior art USB memory devices which used TSOP packages mounted on a printed circuit board, the semiconductor die of the present invention are affixed to the substrate and wire bonded in a SIP configuration. Omitting the encapsulated TSOP packages allows a reduction in the overall thickness of the USB flash memory device. | 07-02-2009 |
20090166820 | TSOP LEADFRAME STRIP OF MULTIPLY ENCAPSULATED PACKAGES - A method of fabricating a semiconductor leadframe package from a strip including multiply encapsulated leadframe packages, and a leadframe package formed thereby are disclosed. An entire row or column of leadframes gets encapsulated together. Encapsulating an entire row or column reduces the keep-out area between adjacent leadframe packages, which allows the internal leads of each leadframe and the semiconductor die coupled thereto to be lengthened. | 07-02-2009 |
20090166828 | ETCHED SURFACE MOUNT ISLANDS IN A LEADFRAME PACKAGE - A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package includes a leadframe and one or more semiconductor die affixed to a die paddle of the leadframe. The leadframe is formed with a plurality of electrical terminals that get surface mounted to a host PCB. The leadframe further includes one or more extended leads, at least one of which includes an electrically conductive island which gets surface mounted to the host PCB with the electrical terminals. The islands effectively increase the number terminals within the package without adding footprint to the package. | 07-02-2009 |
20090166887 | SEMICONDUCTOR PACKAGE INCLUDING FLIP CHIP CONTROLLER AT BOTTOM OF DIE STACK - A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations. | 07-02-2009 |
20090256249 | STACKED, INTERCONNECTED SEMICONDUCTOR PACKAGE - An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages. | 10-15-2009 |
20090263969 | HIDDEN PLATING TRACES - A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided. | 10-22-2009 |
20090321950 | STACKED SEMICONDUCTOR PACKAGE WITH LOCALIZED CAVITIES FOR WIRE BONDING - A semiconductor die and a low profile semiconductor package formed therefrom are disclosed. The semiconductor package may include at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with localized cavities through a bottom surface of the semiconductor die, along a side edge of the semiconductor die. The one or more localized cavities in a side take up less than the entire side. Thus, the localized cavities allow low height stacking of semiconductor die while providing each die with a high degree of structural integrity to prevent cracking or breaking of the die edge during fabrication. | 12-31-2009 |
20090321951 | STACKED WIRE BONDED SEMICONDUCTOR PACKAGE WITH LOW PROFILE BOND LINE - A low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with a plurality of redistribution pads formed over and electrically coupled to a plurality of bond pads. After the semiconductor die are formed and diced from the wafer, the die may be mounted to the substrate using a low profile reverse wire bond according to the present invention. In particular, a wedge bond may be formed between the wire and the redistribution pad without having to use a second wire bond ball on the die bond pad as in conventional reverse ball bonding processes. | 12-31-2009 |
20090325321 | Reclaiming Packages - A method of forming a semiconductor card. A semiconductor package having a damaged controller die is reclaimed. The reclaim process includes severing the electrical connections between the controller die and the semiconductor package substrate without exposing the passive component. In one embodiment, the cutting tool comprises a saw blade. An electrically insulating material is deposited over the exposed bond wires to complete the reclaim process. The reclaimed package and a new controller die are affixed to a second substrate to electrically couple the memory die of the reclaimed package with the new controller die—forming a new package. The new package is encapsulated to form a new memory card. | 12-31-2009 |
20090325342 | METHOD OF FABRICATING STACKED SEMICONDUCTOR PACKAGE WITH LOCALIZED CAVITIES FOR WIRE BONDING - A method of fabricating a semiconductor die and a low profile semiconductor package are disclosed. The semiconductor package may include at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with localized cavities through a bottom surface of the semiconductor die, along a side edge of the semiconductor die. The one or more localized cavities in a side take up less than the entire side. Thus, the localized cavities allow low height stacking of semiconductor die while providing each die with a high degree of structural integrity to prevent cracking or breaking of the die edge during fabrication. | 12-31-2009 |
20090325344 | METHOD OF FABRICATING STACKED WIRE BONDED SEMICONDUCTOR PACKAGE WITH LOW PROFILE BOND LINE - A method of fabricating a low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with a plurality of redistribution pads formed over and electrically coupled to a plurality of bond pads. After the semiconductor die are formed and diced from the wafer, the die may be mounted to the substrate using a low profile reverse wire bond according to the present invention. In particular, a wedge bond may be formed between the wire and the redistribution pad without having to use a second wire bond ball on the die bond pad as in conventional reverse ball bonding processes. | 12-31-2009 |
20100044861 | SEMICONDUCTOR DIE SUPPORT IN AN OFFSET DIE STACK - A semiconductor device is disclosed including a support structure for supporting an edge of a semiconductor die that is not supported on the substrate or semiconductor die below. In embodiments, the semiconductor device may in general include a substrate having a plurality of contact pads, a first semiconductor die mounted on the substrate, and a second semiconductor die mounted on the first semiconductor die in an offset configuration so that an edge of the second semiconductor die overhangs the first semiconductor die. A support structure may be affixed to one or more of the contact pads beneath the overhanging edge to support the overhanging edge during a wire bonding process which exerts a downward force on the overhanging edge. | 02-25-2010 |
20100052155 | METHODS OF PROMOTING ADHESION BETWEEN TRANSFER MOLDED IC PACKAGES AND INJECTION MOLDED PLASTICS FOR CREATING OVER-MOLDED MEMORY CARDS - A flash memory card and methods of manufacturing same are disclosed. The card includes a semiconductor package fabricated to receive a single-sided or double-sided lid. A surface of the semiconductor package may be formed with holes, trenches and/or pockmarks. After the holes, trenches and/or pockmarks are formed, a lid may be attached to the package surface in an injection molding process. During the injection molding process, the molten plastic flows into the holes, trenches and/or pockmarks to interconnect with the surface of the semiconductor package. Thus, when the molten plastic hardens, the holes, trenches and/or pockmarks ensure that the lid remains firmly attached to semiconductor package. | 03-04-2010 |
20100055835 | METHOD OF STACKING AND INTERCONNECTING SEMICONDUCTOR PACKAGES VIA ELECTRICAL CONNECTORS EXTENDING BETWEEN ADJOINING SEMICONDUCTOR PACKAGES - An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages. | 03-04-2010 |
20100055836 | METHOD OF STACKING AND INTERCONNECTING SEMICONDUCTOR PACKAGES VIA ELECTRICAL CONNECTORS EXTENDING BETWEEN ADJOINING SEMICONDUCTOR PACKAGES - An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages. | 03-04-2010 |
20100055847 | METHODS OF PROMOTING ADHESION BETWEEN TRANSFER MOLDED IC PACKAGES AND INJECTION MOLDED PLASTICS FOR CREATING OVER-MOLDED MEMORY CARDS - A flash memory card and methods of manufacturing same are disclosed. The card includes a semiconductor package fabricated to receive a single-sided or double-sided lid. A surface of the semiconductor package may be formed with holes, trenches and/or pockmarks. After the holes, trenches and/or pockmarks are formed, a lid may be attached to the package surface in an injection molding process. During the injection molding process, the molten plastic flows into the holes, trenches and/or pockmarks to interconnect with the surface of the semiconductor package. Thus, when the molten plastic hardens, the holes, trenches and/or pockmarks ensure that the lid remains firmly attached to semiconductor package. | 03-04-2010 |
20100102440 | HIGH DENSITY THREE DIMENSIONAL SEMICONDUCTOR DIE PACKAGE - A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates. By providing each flash memory semiconductor die on a substrate with a unique layout of address traces, each memory die may be selectively addressed by the controller die. | 04-29-2010 |
20100252315 | Printed Circuit Board With Coextensive Electrical Connectors And Contact Pad Areas - A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads. | 10-07-2010 |
20100289147 | SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER - A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die. | 11-18-2010 |
20110024881 | SEMICONDUCTOR DEVICE HAVING UNDER-FILLED DIE IN A DIE STACK - A semiconductor device including a semiconductor die in a die stack under-filled with a film. Once the semiconductor die are formed, they may be stacked and interconnected. The interconnection may leave a small space between semiconductor die in the die stack. This space is advantageously completely filled using a vapor deposition process where a coating is deposited as a vapor which flows over all surfaces of the die stack, including into the spaces between the die in the stack. The vapor then deposits on the surfaces between and around the die and forms a film which completely fills the spaces between the die in the die stack. The material used in the vapor deposition under-fill process may for example be a member of the parylene family of polymers, and in embodiments, may be parylene-N. | 02-03-2011 |
20110024891 | METHOD OF REDUCING MEMORY CARD EDGE ROUGHNESS BY EDGE COATING - A method of forming a semiconductor package with smooth edges, and a semiconductor package formed thereby is disclosed. In embodiments, after encapsulation, the semiconductor packages may be at least partially singulated from the panel by making one or more cuts through the panel to define one or more edges of the semiconductor package. The one or more edges may be smoothed by applying a laminate to the edges. The edges receiving the laminate may include any edge between a top and bottom surface of the package. | 02-03-2011 |
20110024897 | METHOD OF ASSEMBLING SEMICONDUCTOR DEVICES WITH LEDS - Methods of forming integrated circuit packages having an LED molded into the package, and the integrated circuit package formed thereby. An integrated circuit including one or more semiconductor die, passive components and an LED may be assembled on a panel. The one or more semiconductor die, passive components and LED may all then be encapsulated in a molding compound, and the integrated circuits then singularized to form individual integrated circuit packages. The integrated circuits are cut from the panel so that a portion of the lens of the LED is severed during the singularization process, and an end of the lens remaining within the package lies flush with an edge of the package to emit light outside of the package. | 02-03-2011 |
20110095440 | SEMICONDUCTOR PACKAGE INCLUDING FLIP CHIP CONTROLLER AT BOTTOM OF DIE STACK - A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations. | 04-28-2011 |
20110210446 | SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER - A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die. | 09-01-2011 |
20110309485 | ETCHED SURFACE MOUNT ISLANDS IN A LEADFRAME PACKAGE - A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package includes a leadframe and one or more semiconductor die affixed to a die paddle of the leadframe. The leadframe is formed with a plurality of electrical terminals that get surface mounted to a host PCB. The leadframe further includes one or more extended leads, at least one of which includes an electrically conductive island which gets surface mounted to the host PCB with the electrical terminals. The islands effectively increase the number terminals within the package without adding footprint to the package. | 12-22-2011 |
20120007226 | SYSTEM-IN-A-PACKAGE BASED FLASH MEMORY CARD - A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package. | 01-12-2012 |
20120009732 | SYSTEM-IN-A-PACKAGE BASED FLASH MEMORY CARD - A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package. | 01-12-2012 |
20120081860 | PRE-TREATMENT OF MEMORY CARDS FOR INK JET PRINTING - A memory device is disclosed including at least one surface pre-treated to roughen the surface for better adhesion of ink on the surface. The surface of the memory device may be pre-treated by scoring lines in the surface with a laser or by forming discrete deformations with a particle blaster. The surface may also be roughened by providing a roughened pattern on a mold plate during an encapsulation process. In further examples, the surface may be chemically pre-treated to roughen the surface and/or increase the adhesion energy of the surface. | 04-05-2012 |
20120146247 | PRE-TREATMENT OF MEMORY CARDS FOR BINDING GLUE AND OTHER CURABLE FLUIDS - A memory device is disclosed including at least one surface pre-treated to roughen the surface for better adhesion of a curable fluid such as glue or ink on the surface. The surface of the memory device may be pre-treated by scoring lines in the surface with a laser or by forming discrete deformations with a particle blaster. The surface may also be roughened by providing a roughened pattern on a mold plate during an encapsulation process. In further examples, the surface may be chemically pre-treated to roughen the surface and/or increase the adhesion energy of the surface. | 06-14-2012 |
20120164828 | HIDDEN PLATING TRACES - A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided. | 06-28-2012 |
20120273968 | Printed Circuit Board With Coextensive Electrical Connectors And Contact Pad Areas - A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads. | 11-01-2012 |
20120279651 | EPOXY COATING ON SUBSTRATE FOR DIE ATTACH - A system and method are disclosed for applying a die attach epoxy to substrates on a panel of substrates. The system includes a window clamp having one or more windows through which the epoxy may be applied onto the substrate panel. The size and shape of the one or more windows correspond to the size and shape of the area on the substrate to receive the die attach epoxy. Once the die attach epoxy is sprayed onto the substrate through the windows of the window clamp, the die may be affixed to the substrate and the epoxy cured in one or more curing steps. The system may further include a clean-up follower for cleaning epoxy off of the window clamp, and a window cleaning mechanism for cleaning epoxy off of the sidewalls of the windows of the window clamp. | 11-08-2012 |
20120280378 | COL-BASED SEMICONDUCTOR PACKAGE INCLUDING ELECTRICAL CONNECTIONS THROUGH A SINGLE LAYER LEADFRAME - A semiconductor package is disclosed including a leadframe, memory die and controller die, one or more of which are customized to facilitate electrical connection of the memory and controller die bond pads to the contact pads of the host device via the leadframe. By customizing one or more of the leadframe, memory die and controller die, an interposer layer normally required to connect the die in the semiconductor package with a host device may be omitted. | 11-08-2012 |
20130006564 | DISCRETE COMPONENT BACKWARD TRACEABILITY AND SEMICONDUCTOR DEVICE FORWARD TRACEABILITY - A system is disclosed for providing backward and forward traceability by a methodology which identifies discrete components (die, substrate and/or passives) that are included in a semiconductor device. The present technology further includes a system for generating a unique identifier and marking a semiconductor device with the unique identifier enabling the semiconductor device, and the discrete components within that device, to be tracked and traced through each process and test in the production of the semiconductor device. | 01-03-2013 |
20130084677 | METHOD OF FABRICATING A MEMORY CARD USING SIP/SMT HYBRID TECHNOLOGY - A portable memory card formed from a multi-die assembly, and methods of fabricating same, are disclosed. One such multi-die assembly includes an LGA SiP semiconductor package and a leadframe-based SMT package both affixed to a PCB. The multi-die assembly thus formed may be encased within a standard lid to form a completed portable memory card, such as a standard SDTM card. Test pads on the LGA SiP package, used for testing operation of the package after it is fabricated, may also be used for physically and electrically coupling the LGA SiP package to the PCB. | 04-04-2013 |
20130087895 | RADIATION-SHIELDED SEMICONDUCTOR DEVICE - A semiconductor device is disclosed including an electromagnetic radiation shield. The device may include a substrate having a shield ring defined in a conductance pattern on a surface of the substrate. One or more semiconductor die may be affixed and electrically coupled to the substrate. The one or more semiconductor die may then be encapsulated in molding compound. Thereafter, a metal may be plated around the molding compound and onto the shield ring to form an EMI/RFI shield for the device. | 04-11-2013 |
20130157413 | SEMICONDUCTOR PACKAGE INCLUDING FLIP CHIP CONTROLLER AT BOTTOM OF DIE STACK - A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations. | 06-20-2013 |
20130200507 | TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASED PACKAGE - A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe. | 08-08-2013 |
20130299959 | RIGID WAVE PATTERN DESIGN ON CHIP CARRIER SUBSTRATE AND PRINTED CIRCUIT BOARD FOR SEMICONDUCTOR AND ELECTRONIC SUB-SYSTEM PACKAGING - A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking. | 11-14-2013 |
20140015116 | EMI SHIELDING AND THERMAL DISSIPATION FOR SEMICONDUCTOR DEVICE - A memory device including a metallic layer shielding electromagnetic radiation and/or dissipating heat, and a method of making the memory device, are disclosed. The metallic layer is formed on a metallic layer transfer assembly. The metallic layer transfer assembly and the unencapsulated memory device are placed in a mold and encapsulated. During the encapsulation and curing of the molding compound, the metallic layer is transferred from the shield to the encapsulated memory device. | 01-16-2014 |
20150054177 | RIGID WAVE PATTERN DESIGN ON CHIP CARRIER SUBSTRATE AND PRINTED CIRCUIT BOARD FOR SEMICONDUCTOR AND ELECTRONIC SUB-SYSTEM PACKAGING - A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking. | 02-26-2015 |