Patent application number | Description | Published |
20110045523 | Optical Nanosensors Comprising Photoluminescent Nanostructures - Systems and methods related to optical nanosensors comprising photoluminescent nanostructures are generally described. Generally, the nanosensors comprise a photoluminescent nanostructure and a polymer that interacts with the photoluminescent nanostructure. In some cases, the interaction between the polymer and the nanostructure can be non-covalent (e.g., via van der Waals interactions). The nanosensors comprising a polymer and a photoluminescent nanostructure may be particularly useful in determining the presence and/or concentration of relatively small molecules, in some embodiments. In addition, in some instances the nanosensors may be capable of determining relatively low concentrations of analytes, in some cases determining as little as a single molecule. In some embodiments, the interaction between the analyte and the nanosensor (e.g., between the analyte and the photoluminescent nanostructure) can be reversible, which may allow, for example, for the reuse of a nanosensor after it has been exposed to an analyte. | 02-24-2011 |
20110257033 | POLYMER-NANOSTRUCTURE COMPOSITION FOR SELECTIVE MOLECULAR RECOGNITION - A composition can include a complex, where the complex includes a photoluminescent nanostructure and a polymer free from selective binding to an analyte, the polymer adsorbed on the photoluminescent nanostructure, and a selective binding site associated with the complex. | 10-20-2011 |
20110269243 | SYSTEMS AND METHODS RELATED TO OPTICAL NANOSENSORS COMPRISING PHOTOLUMINESCENT NANOSTRUCTURES - Systems and methods related to optical nanosensors comprising photoluminescent nanostructures are generally described. | 11-03-2011 |
20140080122 | Optical Nanosensors Comprising Photoluminescent Nanostructures - Systems and methods related to optical nanosensors comprising photoluminescent nanostructures are generally described. Generally, the nanosensors comprise a photoluminescent nanostructure and a polymer that interacts with the photoluminescent nanostructure. In some cases, the interaction between the polymer and the nanostructure can be non-covalent (e.g., via van der Waals interactions). The nanosensors comprising a polymer and a photoluminescent nanostructure may be particularly useful in determining the presence and/or concentration of relatively small molecules, in some embodiments. In addition, in some instances the nanosensors may be capable of determining relatively low concentrations of analytes, in some cases determining as little as a single molecule. In some embodiments, the interaction between the analyte and the nanosensor (e.g., between the analyte and the photoluminescent nanostructure) can be reversible, which may allow, for example, for the reuse of a nanosensor after it has been exposed to an analyte. | 03-20-2014 |
Patent application number | Description | Published |
20090216984 | OPTIMIZATIONS OF A PERFORM FRAME MANAGEMENT FUNCTION ISSUED BY PAGEABLE GUESTS - Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests. | 08-27-2009 |
20090217098 | MANAGING USE OF STORAGE BY MULTIPLE PAGEABLE GUESTS OF A COMPUTING ENVIRONMENT - Management of storage used by pageable guests of a computing environment is facilitated. An enhanced suppression-on-protection facility is provided that enables the determination of which level of protection (host or guest) caused a fault condition, in response to an attempted storage access. | 08-27-2009 |
20100088444 | CENTRAL PROCESSING UNIT MEASUREMENT FACILITY - A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss. | 04-08-2010 |
20100088771 | VIRTUALIZATION OF A CENTRAL PROCESSING UNIT MEASUREMENT FACILITY - A central processing unit measurement facility is virtualized in order to support concurrent use of the facility by multiple guests executing within a virtual environment. Each guest of the environment has independent control over disablement/enablement of the facility for that guest. | 04-08-2010 |
20110029758 | CENTRAL PROCESSING UNIT MEASUREMENT FACILITY - A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss. | 02-03-2011 |
20110078419 | SET PROGRAM PARAMETER INSTRUCTION - A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss. | 03-31-2011 |
20120047343 | USE OF TEST PROTECTION INSTRUCTION IN COMPUTING ENVIRONMENTS THAT SUPPORT PAGEABLE GUESTS - Management of storage used by pageable guests of a computing environment is facilitated. A query instruction is provided that details information regarding the storage location indicated in the query. It specifies whether the storage location, if protected, is protected by host-level protection or guest-level protection. | 02-23-2012 |
20120089816 | QUERY SAMPLING INFORMATION INSTRUCTION - A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss. | 04-12-2012 |
20120284477 | EXECUTION OF A PERFORM FRAME MANAGEMENT FUNCTION INSTRUCTION - Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests. | 11-08-2012 |
20130138907 | USE OF TEST PROTECTION INSTRUCTION IN COMPUTING ENVIRONMENTS THAT SUPPORT PAGEABLE GUESTS - Management of storage used by pageable guests of a computing environment is facilitated. A query instruction is provided that details information regarding the storage location indicated in the query. It specifies whether the storage location, if protected, is protected by host-level protection or guest-level protection. | 05-30-2013 |
20130305023 | EXECUTION OF A PERFORM FRAME MANAGEMENT FUNCTION INSTRUCTION - Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests. | 11-14-2013 |
20140149705 | USE OF TEST PROTECTION INSTRUCTION IN COMPUTING ENVIRONMENTS THAT SUPPORT PAGEABLE GUESTS - Management of storage used by pageable guests of a computing environment is facilitated. A query instruction is provided that details information regarding the storage location indicated in the query. It specifies whether the storage location, if protected, is protected by host-level protection or guest-level protection. | 05-29-2014 |
20150100748 | USE OF TEST PROTECTION INSTRUCTION IN COMPUTING ENVIRONMENTS THAT SUPPORT PAGEABLE GUESTS - Management of storage used by pageable guests of a computing environment is facilitated. A query instruction is provided that details information regarding the storage location indicated in the query. It specifies whether the storage location, if protected, is protected by host-level protection or guest-level protection. | 04-09-2015 |
20150277908 | START VIRTUAL EXECUTION INSTRUCTION FOR DISPATCHING MULTIPLE THREADS IN A COMPUTER - Embodiments relate to multithreading in a computer. An aspect is a computer including a configuration having a core which includes physical threads and is operable in single thread (ST) and multithreading (MT) modes. The computer also includes a host program configured to execute in the ST mode on the core to issue a start-virtual-execution (start-VE) instruction to dispatch a guest entity which includes a guest virtual machine (VM). The start-VE instruction is executed by the core and includes obtaining a state description, having a guest state, from a location specified by the start-VE instruction. The execution includes determining, based on the guest state, whether the guest entity includes a single guest thread or multiple guest threads, and starting the guest threads in the MT mode or ST mode based on the guest state and a determination of whether the guest entity includes a single guest thread or multiple guest threads. | 10-01-2015 |
20150277913 | MULTITHREADING CAPABILITY INFORMATION RETRIEVAL - Embodiments relate to multithreading capability information retrieval. An aspect is a computer system includes a configuration with one or more cores configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of each core. The computer system also includes a multithreading facility configured to control utilization of the configuration to perform a method that includes executing, by the core, a retrieve multithreading capability information instruction. The execution includes obtaining thread identification information that identifies multithreading capability of the configuration, and storing the obtained thread identification information. | 10-01-2015 |
20150277918 | DYNAMIC ENABLEMENT OF MULTITHREADING - Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The computer system also includes a multithreading facility configured to control the configuration to perform a method. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads. | 10-01-2015 |
20150277919 | THREAD CONTEXT PRESERVATION IN A MULTITHREADING COMPUTER SYSTEM - According to one aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads. The computer system also includes a multithreading facility configured to control utilization of the configuration to perform a method. Based on determining, by the core in the MT mode, that MT is to be disabled, the MT mode switches to the ST mode, where the primary thread of the MT mode is maintained as the primary thread of the ST mode. A thread context of the one or more secondary threads is made inaccessible to programs. Based on the switching, any one of clearing the program accessible register values or retaining the program accessible register values is performed. | 10-01-2015 |
20150277920 | THREAD CONTEXT RESTORATION IN A MULTITHREADING COMPUTER SYSTEM - Embodiments relate to thread context restoration. One aspect is a multithreading computer system including a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method including disabling one or more secondary threads based on switching from MT mode to ST mode. A thread context of secondary threads is made unavailable to programs. Based on a last-set program-specified maximum thread-id indicating MT, the thread context is obtained by a) executing a set MT instruction to resume the MT mode, and b) based on being in the resumed MT mode, accessing the thread context. | 10-01-2015 |
20150277921 | ADDRESS EXPANSION AND CONTRACTION IN A MULTITHREADING COMPUTER SYSTEM - Embodiments relate to address expansion and contraction in a multithreading computer system. According to one aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method that includes accessing the primary thread in the ST mode using a core address value and switching from the ST mode to the MT mode. The primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value, where the expanded address value includes the core address value concatenated with a thread address value. | 10-01-2015 |
20150277923 | IDLE TIME ACCUMULATION IN A MULTITHREADING COMPUTER SYSTEM - Embodiments relate to idle time accumulation in a multithreading computer system. According to one aspect, a computer system includes a configuration having a plurality of cores and an operating system (OS)-image configurable between a single thread (ST) mode and a multithreading (MT) mode in a logical partition. The MT mode supports multiple threads on shared resources per core simultaneously. The computer system also includes a multithreading facility configured to perform a method that includes executing a query instruction on an initiating core of the plurality of cores. The executing includes obtaining, by the OS-image, a maximum thread identification value indicating a current maximum thread identifier of the cores within the logical partition. The initiating core also obtains a multithreading idle time value for each of the cores indicating an aggregate amount of idle time of all threads enabled on each of the cores in the MT mode. | 10-01-2015 |
20150277948 | CONTROL AREA FOR MANAGING MULTIPLE THREADS IN A COMPUTER - Embodiments relate to a control area for managing multiple threads in a computer. An aspect is a computer system that includes a virtual machine (VM) configuration with one or more cores. Each core is enabled to operate in a single thread (ST) mode or a multithreading (MT) mode. The ST mode consists of a single thread and the MT mode consists of a plurality of threads on shared resources of a respective core. The computer system includes a core-oriented system control area (COSCA) having a common area representing all of the cores of the VM configuration and separate core description areas for each of the cores in the VM configuration. Each core description area indicates a location of one or more thread description areas each representing a thread within the respective core, and each thread description area indicates a location of a state description of the respective thread. | 10-01-2015 |
20150339120 | DYNAMIC ENABLEMENT OF MULTITHREADING - Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer-implemented method for dynamic enablement of multithreading in a configuration is provided. The configuration includes a core configurable between a single thread (ST) mode and a multithreading (MT) mode, where the ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads. | 11-26-2015 |
20150339121 | THREAD CONTEXT RESTORATION IN A MULTITHREADING COMPUTER SYSTEM - Embodiments relate to thread context restoration. One aspect is a multithreading computer system including a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method including disabling one or more secondary threads based on switching from MT mode to ST mode. A thread context of secondary threads is made unavailable to programs. Based on a last-set program-specified maximum thread-id indicating MT, the thread context is obtained by a) executing a set MT instruction to resume the MT mode, and b) based on being in the resumed MT mode, accessing the thread context. | 11-26-2015 |
20150347132 | THREAD CONTEXT PRESERVATION IN A MULTITHREADING COMPUTER SYSTEM - According to one aspect, a computer-implemented method for thread context preservation in a configuration including a core configurable between a single thread (ST) mode and a multithreading (MT) mode is provided. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. Based on determining, by the core in the MT mode, that MT is to be disabled, switching from the MT mode to the ST mode is performed, where the primary thread of the MT mode is maintained as the primary thread of the ST mode. A thread context including program accessible register values and program counter values of the one or more secondary threads is made inaccessible to programs. Based on the switching, any one of clearing the program accessible register values or retaining the program accessible register values is performed. | 12-03-2015 |
20150355908 | ADDRESS EXPANSION AND CONTRACTION IN A MULTITHREADING COMPUTER SYSTEM - Embodiments relate to address expansion and contraction in a multithreading computer system. According to one aspect, a computer implemented method for address adjustment in a configuration is provided. The configuration includes a core configurable between an ST mode and an MT mode, where the ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The primary thread is accessed in the ST mode using a core address value. Switching from the ST mode to the MT mode is performed. The primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value. The expanded address value includes the core address value concatenated with a thread address value. | 12-10-2015 |
20150355940 | IDLE TIME ACCUMULATION IN A MULTITHREADING COMPUTER SYSTEM - Embodiments relate to idle time accumulation in a multithreading computer system. According to one aspect, a computer-implemented method for idle time accumulation in a computer system is provided. The computer system includes a configuration having a plurality of cores and an operating system (OS)-image configurable between single thread (ST) mode and a multithreading (MT) mode in a logical partition. The MT mode supports multiple threads on shared resources per core simultaneously. The method includes executing a query instruction on an initiating core of the plurality of cores. The executing includes obtaining, by the OS-image, a maximum thread identification value indicating a current maximum thread identifier of the cores within the logical partition. The initiating core also obtains a multithreading idle time value for each of the cores indicating an aggregate amount of idle time of all threads enabled on each of the cores in the MT mode. | 12-10-2015 |