Patent application number | Description | Published |
20120170376 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device includes a plurality of memory cells, including an N well formed within a P type region and a P well formed within the N well, a peripheral circuit configured to perform a program, program verify, read, erase, or erase verify operation on memory cells selected from among the memory cells, a voltage supply circuit configured to generate a positive voltage and a negative voltage for the program, program verify, read, erase, or erase verify operation, and a control circuit configured to control the peripheral circuit and the voltage supply circuit so that the program, program verify, read, erase, or erase verify operation is performed and, when the program verify and read operations are performed, different voltage is supplied to the P well and the N well. | 07-05-2012 |
20150221389 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - Provided are a semiconductor memory device and an operating method thereof. The semiconductor memory device may include a memory cell array having a plurality of strings each including a drain select transistor, a plurality of drain side memory cells, a pipe transistor, a plurality of source side memory cells, and a source select transistor. The semiconductor memory device may also include a peripheral circuit suitable for providing a plurality of operation voltages including an erase verify voltage to the plurality of strings, and a control logic suitable for controlling the peripheral circuit to adjust a voltage level of the erase verify voltage applied to a selected memory cell, from among the plurality of drain side memory cells and the plurality of source side memory cells, according to a distance between the selected memory cell and the pipe transistor when an erase verify operation is performed. | 08-06-2015 |
20150228348 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - An operating method of a semiconductor device includes repeating an erase loop operable to lower threshold voltages of memory cells in a selected memory block by applying an erase voltage to the selected memory block and performing an erase verification to determine whether the threshold voltages of the memory cells in the selected memory block are less than or equal to a target level, wherein an erase voltage is increased by a voltage difference wherein the voltage difference is increased between successive applications of two or more of the erase loops, and repeating a program loop including applying a program voltage to a selected word line to increase threshold voltages of memory cells electrically coupled to the selected word line and performing a program verification to determine whether the threshold voltages are greater than or equal to a target level, wherein a program voltage is increased by a voltage difference wherein the voltage difference is increased between successive applications of two or more program voltages. | 08-13-2015 |
20150235702 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - The semiconductor device includes a CAM block including a plurality of vertical strings having a perpendicular configuration with respect to a semiconductor substrate, wherein each of the plurality of vertical strings is electrically coupled to a plurality of word lines and each of the plurality of word lines is electrically coupled to a plurality of CAM cells, a peripheral circuit configured to program CAM cells selected from the plurality of CAM cells, and a control circuit configured to issue at least one command to the peripheral circuit to simultaneously apply a program voltage to an n | 08-20-2015 |
20160055913 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - An operating method of a semiconductor device is provided. The operating method of the semiconductor memory device includes programming a second source select transistor electrically coupled to a common source line through a first source select transistor; reprogramming the second source select transistor when a threshold voltage of the second source select transistor is less than a target voltage, and ending a program for the second source select transistor when the threshold voltage of the second source select transistor is greater than or equal to the target voltage. The programming includes electrically decoupling the second source select transistor from the common source line by turning off the first source select transistor. | 02-25-2016 |
20160078950 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - An operating method of a semiconductor device includes repeating an erase loop operable to lower threshold voltages of memory cells in a selected memory block by applying an erase voltage to the selected memory block and performing an erase verification to determine whether the threshold voltages of the memory cells in the selected memory block are less than or equal to a target level, wherein an erase voltage is increased by a voltage difference wherein the voltage difference is increased between successive applications of two or more of the erase loops, and repeating a program loop including applying a program voltage to a selected word line to increase threshold voltages of memory cells electrically coupled to the selected word line and performing a program verification to determine whether the threshold voltages are greater than or equal to a target level, wherein a program voltage is increased by a voltage difference wherein the voltage difference is increased between successive applications of two or more program voltages. | 03-17-2016 |
20160141011 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - Provided is a semiconductor device and an operating method thereof. The operating method of the semiconductor device includes performing an erase operation on a memory block including bottom dummy cells, a plurality of memory cells, top dummy cells and selection transistors arranged in a vertical direction with respect to a pipe gate, increasing threshold voltages of the top and bottom dummy cells at substantially a same time by applying a first soft program voltage to a bottom dummy word line coupled to the bottom dummy cells and a second soft program voltage greater than the first soft program voltage to the top dummy word line coupled to the top dummy cells, verifying the top and bottom dummy cells, and repeatedly performing the erase operation and increasing the threshold voltages by gradually increasing the first and second soft program voltages until the verifying of the top and bottom dummy cells passes. | 05-19-2016 |
20160141043 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device may include a memory block including memory strings connected to respective bit lines coupled to a substrate and commonly connected to a common source line coupled to the substrate. The semiconductor device may include an operation circuit configured to perform an operation on memory cells included in the memory strings. The bit lines may be classified into a plurality of groups. The operation circuit may be configured to apply a voltage to bit lines of a selected group and set the common source line to a voltage level for the operation. | 05-19-2016 |