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| 20110028541 | LUBIPROSTONE CRYSTAL, THE USE AND THE METHOD FOR THE PREPARATION THEREOF - The present invention relates to a lubiprostone crystal, the method for the preparation thereof, and a pharmaceutical composition or kit comprising the same, as well as the use of said crystal in the preparation of a medicament for the treatment of gastrointestinal tract diseases, especially constipation. The X-ray powder diffraction pattern of said crystal comprises characteristic peaks measured at the following 2θ reflection angles: 14.6±0.2°, 17.0±0.2° and 19.6±0.2°. As compared to amorphous lubiprostone, the crystal of the present invention has the advantages of relative high purity, stable properties and easy-for-storage and use. | 02-03-2011 |
| 20120270946 | CRYSTALLINE FORM OF BIMATOPROST, PREPARATION METHOD AND USE THEREOF - The crystalline form A of Bimatoprost of formula I, its preparation method and use are provided. There are characteristic peaks where diffraction angles 2θ are 3.2+0.2°, 5.5+0.2°, 11.4+0.2°, 16.7+0.2°, 17.6+0.2°, 19.9+0.2°, 20.8±02° and 22.8+0.2° in the X-ray powder diffraction pattern of the crystalline form A. | 10-25-2012 |
| 20130225482 | CASPOFUNGIN ANALOG, AND PREPARATION METHOD AND USES THEREOF - Disclosed are a caspofungin analog, and a preparation method and applications thereof. The caspofungin analog has a structure as represented in Formula 3. | 08-29-2013 |
| 20130231457 | PREPARATION METHOD FOR CASPOFUNGIN - Disclosed is a preparation method for caspofungin, comprising the steps: (a) a compound as represented in Formula 2 and a strong leaving group 5 are mixed to obtain a compound as represented in Formula 3; (b) the compound as represented in Formula 3 and ethylenediamine are mixed to obtain a compound as represented in Formula 4; and, (c) the compound as represented in Formula 4 is mixed with a hydroxyl protection agent, and then a borane complex is mixed in to obtain a compound as represented in Formula 1. | 09-05-2013 |
| 20130296229 | CASPOFUNGIN ANALOG AND APPLICATIONS THEREOF - Disclosed are a caspofungin analog and applications thereof. Said caspofungin analog is a compound having a structure as indicated in Formula (4), or pharmaceutically acceptable slats thereof. R1 can be chosen from hydroxyl, benzyloxy, phenoxy, substituted phenoxy, or substituted benzyloxy. R | 11-07-2013 |
| 20140114049 | PREPARATION METHOD OF MICAFUNGIN SODIUM - The method of the preparation of micafungin sodium comprises the step of mixing the weak base and the aqueous solution containing micafungin acid (the structure is illustrated by formula I) or the mixed aqueous solution containing the compound of formula I and organic solvent in order to obtain the sodium salt of micafungin (the structure is illustrated by formula II). | 04-24-2014 |
| 20140128315 | CASPOFUNGIN OR SALTS THEREOF WITH HIGH PURITY, AS WELL AS PREPARATION METHOD AND USE THEREOF - Disclosed are a high purity of caspofungin or salts thereof, and a preparation method thereof, and use thereof. Disclosed are a caspofungin or salts thereof with low solvent residue and hyposaline, and a preparation process comprising: dissolving a crude product of caspofungin or slats thereof into a system of water and acetic acid, them mixing with a first organic solvent ethyl alcohol, subsequently mixing with a second organic solvent ethyl acetate, then being subject to filtration and drying together with water, to obtain caspofungin or salts thereof with high stability, low solvent residue and hyposaline. | 05-08-2014 |
| 20150065417 | HIGH PURITY CYCLOPEPTIDE COMPOUND AS WELL AS PREPARATION METHOD AND USE THEREOF - Disclosed is a high purity cyclopeptide compound, the chemical structure of which is represented by formula (I). R represents H or a cation capable of forming a pharmaceutically acceptable salt, the purity being greater than or equal to 99.0%. Further disclosed are preparation method and use of the high purity cyclopeptide compound. | 03-05-2015 |
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| 20100139710 | METHODS AND APPARATUS FOR CLEANING SEMICONDUCTOR WAFERS - An apparatus for cleaning a surface of wafer or substrate includes a plate being positioned with a gap to surface of the wafer or substrate, and the plate being rotated around an axis vertical to surface of wafer or substrate. The rotating plate surface facing surface of the wafer or substrate has grooves, regular patterns, and irregular patterns to enhance the cleaning efficiency. Another embodiment further includes an ultra sonic or mega sonic transducer vibrating the rotating plate during cleaning process. | 06-10-2010 |
| 20100240226 | METHOD AND APPARATUS FOR THERMAL TREATMENT OF SEMICONDUCTOR WORKPIECES - The present invention provides an apparatus and method for rapid and uniform thermal treatment of semiconductor workpieces in two closely arranged thermal treatment chambers with a retractable door between them. The retractable door moves in between two thermal treatment chambers during heating or cooling process, and additional heating and cooling sources are provided for double-side thermal treatment of the semiconductor workpiece. | 09-23-2010 |
| 20110073469 | ELECTROCHEMICAL DEPOSITION SYSTEM - A electrochemical deposition system which has a 3-D stacked architecture comprises a factory interface for receiving semiconductor wafers, a mainframe comprising a mainframe transfer robot and a plurality of wafer holder assemblies which disposed on the top thereof, a plurality of electroplating cells disposed within the mainframe, a plurality of cleaning cells disposed within the mainframe and located below the electroplating cells, a plurality of thermal treatment chambers disposed in between the mainframe and the factory interface, and a fluid distribution system fluidly connected to the electroplating cells and the cleaning cells, wherein the mainframe transfer robot transfers the semiconductor wafer from the factory interface and within the electroplating cells, the cleaning cells, and the thermal treatment chambers. As a result, the system of the present invention is expandable to accommodate newly-added processing units without overmuch increased footprint. | 03-31-2011 |
| 20110079247 | SOLUTION PREPARATION APPARATUS AND METHOD FOR TREATING INDIVIDUAL SEMICONDUCTOR WORKPIECE - The invention discloses a low-cost apparatus for chemical solution preparation with controlled process parameters such as chemical age, temperature, yield of active ingredients at the point of use. In addition, this apparatus provides chamber-to-chamber consistency on these parameters across multiple processing chambers on a single wafer wet-clean system. The invention also discloses a method to use chemical solution mixture resident time to achieve optimal combined effect of temperature, reactivity and yield of active ingredients of chemical solution mixture for best wafer treatment results. | 04-07-2011 |
| 20110114120 | METHODS AND APPARATUS FOR CLEANING SEMICONDUCTOR WAFERS - An apparatus for cleaning and conditioning the surface of a semiconductor substrate such as wafer includes a rotatable chuck, a chamber, a rotatable tray for collecting cleaning solution with one or more drain outlets, multiple receptors for collecting multiple cleaning solutions, a first motor to drive chuck, and a second motor to drive the tray. The drain outlet in the tray can be positioned directly above its designated receptor located under the drain outlet. The cleaning solution collected by the tray can be guided into designated receptor. One characteristic of the apparatus is having a robust and precisely controlled cleaning solution recycle with minimum cross contamination. | 05-19-2011 |
| 20110259752 | METHOD FOR SUBSTANTIALLY UNIFORM COPPER DEPOSITION ONTO SEMICONDUCTOR WAFER - The methods practiced in an electrochemical deposition apparatus with two or more electrodes, described in earlier inventions, are disclosed. The methods produce uniform copper films with WFNU less than 2.5% on semiconductor wafers bearing a resistive copper seed layer with a thickness ranging from 50 to 9O0 A in a copper sulfate based electrolyte whose conductivity is between 0.02 to 0.8 S/cm. | 10-27-2011 |
| 20140034094 | Methods and Apparatus for Cleaning Semiconductor Wafers - An apparatus for cleaning and conditioning the surface of a semiconductor substrate such as wafer includes a rotatable chuck, a chamber, a rotatable tray for collecting cleaning solution with one or more drain outlets, multiple receptors for collecting multiple cleaning solutions, a first motor to drive chuck, and a second motor to drive the tray. The drain outlet in the tray can be positioned directly above its designated receptor located under the drain outlet. The cleaning solution collected by the tray can be guided into designated receptor. One characteristic of the apparatus is having a robust and precisely controlled cleaning solution recycle with minimum cross contamination. | 02-06-2014 |
| 20140216940 | METHODS AND APPARATUS FOR UNIFORMLY METALLIZATION ON SUBSTRATES - An apparatus for substrate metallization from electrolyte is provided. The apparatus comprises: an immersion cell containing metal salt electrolyte; at least one electrode connecting to at least one power supply; an electrically conductive substrate holder holding at least one substrate to expose a conductive side of the substrate to face the at least one electrode; an oscillating actuator for oscillating the substrate holder with an amplitude and a frequency; at least one ultrasonic device with an operating frequency and an intensity, disposed in the metallization apparatus; at least one ultrasonic power generator connecting to the ultrasonic device; at least one inlet for metal slat electrolyte feeding; and at least one outlet for metal salt electrolyte draining. | 08-07-2014 |
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| 20080310815 | Method and Apparatus For Playing Video - The present invention relates to the field of video playing. The method of playing video according to the invention comprises: receiving an event; looking up the PlayItems that simulate the event according to this event; and playing the play clips that correspond to said PlayItems. | 12-18-2008 |
| 20100067335 | METHOD AND APPARATUS FOR ERROR CORRECTION OF OPTICAL DISC DATA - A method and device for error correction of data in an optical disc is provided in the present invention. The method comprises the following steps: obtaining the description information about the error data read from an optical disc; sending request information for error correction, based on the description information, to a network server, where the network server stores the backup data corresponding to the data on the optical disc and the request information for error correction comprises the request for downloading the backup data corresponding to the error data; and replacing the error data with the downloaded backup data, so as to play the optical disc correspondingly. The method and device provided in the present invention can repair data error of various kinds and provide a playing effect of equal quality with the expected playing effect when data is not damaged. | 03-18-2010 |
| 20100104268 | METHOD AND APPARATUS FOR PLAYING AN OPTICAL DISC - The present invention provides a method and apparatus for playing an optical disc, and an optical disc recording apparatus. According to the method provided by the present invention, the description information of the program content and the description information of the enhancement content are first acquired, and then compared with each other; then it is judged whether the program corresponds to the enhancement content according to the result of the comparison; and finally, the program content is played independently of the enhancement content if the program content does not correspond to the enhancement content. With the present invention, the playback problem causing from the non-match of the program content and the enhancement content in an optical disc with the enhancement format resulting from the revision of the optical disc by a conventional optical disc recording apparatus that does not support the enhancement format can be avoided. | 04-29-2010 |
| 20100119209 | METHOD AND APPARATUS FOR ENABLING AN APPLICATION TO COOPERATE WITH RUNNING OF A PROGRAM - The present invention provides a method and apparatus for enabling an application to cooperate with the running of a program. According to the invention, the playing control information of a program and the linking information of an application corresponding to the program are edited into a program playing control file. Through executing said playing control file, guided by the linking information and based on the running control information of the application, the application can download, run or stop to run cooperating with the playing of the optical disc program. The Solution of combining an application and a program into a playing control file will effectively cause the downloading and running of the application to cooperate with the playing of the program so as to ensure normal realization of corresponding functions. | 05-13-2010 |
| 20120189280 | EXTENSIBLE DISC PLAYER - The present invention provides an extensible disc player that is upgradeable to play new content types. The player's capability can be extended by downloading an appropriate decoder from a web server via the Internet. In this way, the player can play back contents that it does not originally support. If the content type is unknown, the player will check whether the disc contains a URL for linking to a web site containing an appropriate decoder. If the disc contains the URL, the player will access the web site to download the appropriate decoder. In a similar manner, the capability of a recorder can also be expanded by downloading appropriate encoders from the Internet. | 07-26-2012 |
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| 20110316073 | SOI CMOS DEVICE HAVING VERTICAL GATE STRUCTURE - The present invention discloses an SOI CMOS device having a vertical gate structure, comprising: an SOI substrate, and an NMOS region and a PMOS region grown on the SOI substrate, wherein the NMOS region and the PMOS region share one vertical gate region, said vertical gate region lying in the same plane as the NMOS region and the PMOS region and between the NMOS region and the PMOS region; a gate oxide layer is arranged between the vertical gate region and the NMOS region for isolation; and a gate oxide layer is arranged between the vertical gate region and the PMOS region for isolation. The present invention occupies small area, contains less pattern layers, requires a simple process, has an open body region that can completely avoid the floating effect of the traditional SOI CMOS device, and is convenient to parasitic resistance and capacitance tests. | 12-29-2011 |
| 20120009740 | METHOD FOR FABRICATING SOI HIGH VOLTAGE POWER CHIP WITH TRENCHES - A method of manufacturing a SOI high voltage power chip with trenches is disclosed. The method comprises: forming a cave and trenches at a SOI substrate; filling oxide in the cave; oxidizing the trenches, forming oxide isolation regions for separating low voltage devices at the same time; filling oxide in the oxidized trenches; and then forming drain regions, source regions and gate regions for a high voltage power device and low voltage devices. The process involves depositing an oxide layer overlapping the cave of the SOI substrate. A SOI high voltage power chip thus made will withstand at least above 700V voltage. | 01-12-2012 |
| 20120021569 | MANUFACTURING METHOD OF SOI HIGH-VOLTAGE POWER DEVICE - The present invention relates to a manufacturing method of SOI devices, and in particular, to a manufacturing method of SOI high-voltage power devices. The method comprises steps of: forming a first oxide layer in a section on the surface of the SOI substrate; removing the first oxide layer to form a depressed area in the corresponding section of the upper surface of the SOI substrate; forming a second oxide layer, the upper surface of which is as high as the that of the SOI substrate, in the depressed area formed in step (B); performing photoetching and doping processes to form a P-type region, an N-type region and a gate region on the thus-formed structure where the second oxide layer is formed; forming a third oxide layer by deposition on the drift region of the structure after P-type and N-type regions are formed; wherein the total thickness of the third oxide layer and the second oxide layer approximates to the thickness of the buried oxide layer in the SOI substrate; and forming metal sub-regions, which are respectively in contact with the P-type region, the N-type region and the gate region, on the structure where the third oxide layer is formed, thereby forming a high-voltage power device. | 01-26-2012 |
| 20120058608 | METHOD OF FABRICATING SOI SUPER-JUNCTION LDMOS STRUCTURE CAPABLE OF COMPLETELY ELIMINATING SUBSTRATE-ASSISTED DEPLETION EFFECTS - The present invention relates to a method of fabricating an SOI SJ LDMOS structure that can completely eliminate the substrate-assisted depletion effects, comprising the following steps: step one: a conducting layer is prepared below the SOI BOX layer using the bonding technique; the conducting layer is prepared in the following way: depositing a barrier layer on a first bulk silicon wafer, and then depositing a charge conducting layer, thereby obtaining a first intermediate structure; forming a silicon dioxide layer on a second bulk silicon wafer via thermal oxidation, then depositing a barrier layer, and finally depositing a charge conducting layer, thereby obtaining a second intermediate structure; bonding the first intermediate structure and the second intermediate structure using the metal bonding technology to arrange the conducting layer below the SOI BOX layer; step two: a SJ LDMOS structure is fabricated on the SOI substrate having a conducting layer. The present invention is capable of releasing the charge accumulated at the lower interface of the BOX layer, eliminating the effect of the vertical charge on the charge balance between the p-type pillar and the n-type pillar, and therefore completely eliminating the substrate-assisted depletion effects and elevating the breakdown voltage of the device. | 03-08-2012 |
| 20120273861 | METHOD OF DEPOSITING GATE DIELECTRIC, METHOD OF PREPARING MIS CAPACITOR, AND MIS CAPACITOR - The present invention relates to a method of depositing a gate dielectric, a method of preparing a MIS capacitor and the MIS capacitor. In the method of depositing the gate dielectric, a semiconductor substrate surface is preprocessed with oxygen plasma and nitrogen-containing plasma to form a nitrogen-containing oxide layer thereon. Then, a high-k gate dielectric layer is grown on the nitrogen-containing oxide layer surface by a plasma-enhanced atomic layer deposition process, and the oxide layer converts during the gate dielectric layer growth process into a buffer layer of a dielectric constant higher than SiO | 11-01-2012 |
| 20120276718 | METHOD OF FABRICATING GRAPHENE-BASED FIELD EFFECT TRANSISTOR - The present invention provides a method of fabricating a graphene-based field effect transistor, which includes steps of: providing a semiconductor substrate on which a non-functionized graphene layer is formed; forming a metal oxide film as a nucleation layer through a reaction between a metal source and water which acts as oxidizer and is physically absorbed to a surface of the graphene layer; and generating a HfO | 11-01-2012 |
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| 20110003278 | H5 Subtype-Specific Binding Proteins Useful for H5 Avian Influenza Diagnosis and Surveillance - The invention provides monoclonal antibodies and related binding proteins that bind specifically to the envelope glycoprotein of H5 subtypes of avian influenza virus (“AIV”). The monoclonal antibodies and related binding proteins are useful for the detection of H5 subtypes of AIV, including the pathogenic H5N1 subtypes. Virus may be detected in formalin preserved, paraffin embeded specimens as well as frozen specimens and biological fluids. Accordingly, the invention provides means for the diagnosis and surveillance of dangerous viral infections. | 01-06-2011 |
| 20130004943 | H5 Subtype-Specific Binding Proteins Useful for H5 Avian Influenza Diagnosis and Surveillance - The invention provides monoclonal antibodies and related binding proteins that bind specifically to the envelope glycoprotein of H5 subtypes of avian influenza virus (“AIV”). The monoclonal antibodies and related binding proteins are useful for the detection of H5 subtypes of AIV, including the pathogenic H5N1 subtypes. Virus may be detected in formalin preserved, paraffin embedded specimens as well as frozen specimens and biological fluids. Accordingly, the invention provides means for the diagnosis and surveillance of dangerous viral infections. | 01-03-2013 |
| 20130004944 | H5 Subtype-Specific Binding Proteins Useful for H5 Avian Influenza Diagnosis and Surveillance - The invention provides monoclonal antibodies and related binding proteins that bind specifically to the envelope glycoprotein of H5 subtypes of avian influenza virus (“AIV”). The monoclonal antibodies and related binding proteins are useful for the detection of H5 subtypes of AIV, including the pathogenic H5N1 subtypes. Virus may be detected in formalin preserved, paraffin embeded specimens as well as frozen specimens and biological fluids. Accordingly, the invention provides means for the diagnosis and surveillance of dangerous viral infections. | 01-03-2013 |
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| 20100041663 | Organic Compounds as Smo Inhibitors - The present invention relates generally to novel compounds relating to the diagnosis and treatment of pathologies relating to the Hedgehog pathway, including but not limited to tumor formation, cancer, neoplasia, and non-malignant hyperproliferative disorders. The present invention includes novel compounds, novel compositions, methods of their use and methods of their manufacture, where such compounds are generally pharmacologically useful as agents in therapies whose mechanism of action involve methods of inhibiting tumorigenesis, tumor growth and tumor survival using agents that inhibit the Hedgehog and Smo signaling pathway. | 02-18-2010 |
| 20100069368 | Organic Compounds and Their Uses - The present disclosure relates to compounds relating to the diagnosis and treatment of pathologies relating to the Hedgehog pathway, including but not limited to tumor formation, cancer, neoplasia, and non-malignant hyperproliferative disorders; specifically relating to compounds of formula I: | 03-18-2010 |
| 20110065708 | HETEROCYCLIC OXIME COMPOUNDS - The invention relates to compounds of formula (I) and salts thereof: | 03-17-2011 |
| 20120142681 | HETEROCYCLIC HYDRAZONE COMPOUNDS - The invention relates to compounds of formula (I) and salts thereof: wherein the substituents are as defined in the specification; a compound of formula (I) for use in the treatment of the human or animal body, in particular with regard to c-Met tyrosine kinase mediated diseases or conditions; the use of a compound of formula (I) for manufacturing a medicament for the treatment of such diseases; pharmaceutical compositions comprising a compound of the formula (I), optionally in the presence of a combination partner, and processes for the preparation of a compound of formula (I). | 06-07-2012 |
| 20120207769 | Inhibitors of IAP - Novel compounds that inhibit the binding of the Smac protein to Inhibitor of Apoptosis Proteins (IAPs) of the formula (I). | 08-16-2012 |
| 20120289507 | ORGANIC COMPOUNDS AS SMO INHIBITORS - The present invention relates generally to novel compounds relating to the diagnosis and treatment of pathologies relating to the Hedgehog pathway, including but not limited to tumor formation, cancer, neoplasia, and non-malignant hyperproliferative disorders. The present invention includes novel compounds, novel compositions, methods of their use and methods of their manufacture, where such compounds are generally pharmacologically useful as agents in therapies whose mechanism of action involve methods of inhibiting tumorigenesis, tumor growth and tumor survival using agents that inhibit the Hedgehog and Smo signaling pathway. | 11-15-2012 |
| 20120302570 | HETEROCYCLIC OXIME COMPOUNDS - The invention relates to compounds of formula (I) and salts thereof: | 11-29-2012 |
| 20130005663 | SMAC PEPTIDOMETICS USEFUL AS IAP INHIBITORS - The present invention is directed to a compound of the formula: | 01-03-2013 |
| 20130245002 | Triazolopyridine Compounds - The invention relates to compounds of formula (I) and salts thereof: | 09-19-2013 |
| 20130261299 | PYRIDAZINYL DERIVATIVES AS SMO INHIBITORS - The present invention relates to compounds of formula I: | 10-03-2013 |
| 20130324526 | [1,2,4] TRIAZOLO [4,3-B] PYRIDAZINE COMPOUNDS AS INHIBITORS OF THE C-MET TYROSINE KINASE - The invention relates to compounds of formula (I) and salts thereof: wherein the substituents are as defined in the specification; a compound of formula (I) for use in the treatment of the human or animal body, in particular with regard to c-Met tyrosine kinase mediated diseases or conditions; the use of a compound of formula (I) for manufacturing a medicament for the treatment of such diseases; pharmaceutical compositions comprising a compound of the formula (I), optionally in the presence of a combination partner, and processes for the preparation of a compound of formula (I). | 12-05-2013 |
| 20140004101 | SMAC PEPTIDOMETICS USEFUL AS IAP INHIBITORS | 01-02-2014 |
| 20140089684 | METHOD AND APPARATUS FOR PROTECTING FILE - Embodiments of the present invention provide a method and a system for protecting a file, which belong to the field of information security. The method includes: replacing a secure file header of a file to be protected with its original file header to convert the file to be protected to a secure file; and preventing, by the secure file header of the secure file acquired by the conversion, another peripheral from performing an access operation on content of the secure file. By using this method, in a terminal device such as an Android mobile phone or a computer, without affecting normal use by a subscriber, the protection of files such as multimedia files can be realized and content of a protected secure file in a mobile phone is not allowed to be opened on another device to achieve a purpose of avoiding private information leakage and protecting personal privacy. | 03-27-2014 |
| 20140115516 | METHOD FOR CONTROLLING SYSTEM BAR OF USER EQUIPMENT, AND USER EQUIPMENT - Embodiments of the present invention provide a method for controlling a system bar of a user equipment, and a user equipment. The method includes: detecting a display status of the system bar; and when the system bar is presented on the screen of the user equipment, and the presented system bar includes a hidden button, receiving a first input used to select the hidden button and input by an input unit to hide the system bar; or when the system bar is not presented on the screen of the user equipment, receiving a second input which is input by the input unit to present the system bar. In the foregoing technical solutions, by flexibly invoking or hiding a system bar integrated with various information and/or convenient buttons, the screen can be used to display content to the greatest extent, so as to improve the utilization rate of the screen. | 04-24-2014 |
| 20150055343 | LUMINAIRE ELEMENT - The invention describes a luminaire element ( | 02-26-2015 |
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| 20120081390 | Displaying Widget Elements Based On Display Device Resolution - Displaying a web page on a display device is accomplished by receiving resolution information corresponding to a resolution of the display device, receiving a resolution threshold for displaying a widget element on the web page, and determining whether the resolution of the display device is less than the resolution threshold for displaying the widget element. If the resolution of the display device is not less than the resolution threshold for displaying the widget element, the widget element is displayed on the web page, wherein the web page is displayed on the display device. If the resolution of the display device is smaller than the resolution threshold for displaying the widget element, the widget element is not displayed on the web page. | 04-05-2012 |
| 20120166933 | VERIFYING PAGE LAYOUT AUTOMATICALLY - Verifying a page layout automatically, including reading page layout rules and parsing the page layout rules. A list of one or more of the page layout rules is generated based on the parsing. Page layout information is collected and verification is performed to verify that the page layout information conforms to the one or more page layout rules in the list. | 06-28-2012 |
| 20130263095 | CONTROLLING ASYNCHRONOUS CALL RETURN - Aspects include controlling asynchronous call return in a program. At least one asynchronous call is detected in the program. Execution of the program is stopped at a breakpoint in response to detecting that the breakpoint is set in the program. At least one callback corresponding to the at least one asynchronous call is obtained. The at least one callback is inserted into one or more specified positions of the program respectively according to a user selection. Execution of the program continues from the breakpoint in response to the insertion of the at least one callback into the program. | 10-03-2013 |
| 20130290933 | TRANSLATION VERIFICATION TESTING - Embodiments of translation verification testing are provided. An aspect includes reading a symbol table and a syntax tree to which source code corresponds. Widget objects and widget object methods are obtained in the symbol table. The widget objects and widget object methods are organized into a widget structure tree according to a code calling order in the syntax tree. An index file corresponding to the source code is generated by using the symbol table, the widget structure tree and resource files, where the index file records relationships between the widget objects. | 10-31-2013 |
| 20130326074 | MOBILE NETWORK APPLICATION TEST - Embodiments relate to a method, system, and computer program product for testing a mobile network application. An aspect includes a method that receives a test request for a mobile network application and activating a test session window on a browser of a mobile device according to the test request. The method also includes obtaining a request in hypertext markup language (HTTP) that corresponds to the test request such that the HTTP request contains session information for the test session window and sending the HTTP request to the mobile network application. An HTTP response containing session information is then received from the mobile network application. | 12-05-2013 |
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| 20110078490 | SVC CLUSTER CONFIGURATION NODE FAILOVER SYSTEM AND METHOD - Methods, systems, and computer programs are provided for failover responses to configuration node failures in SVC clusters. An SVC cluster manages a plurality of storage devices and includes a plurality of SVCs interconnected via a network, each SVC acting as a separate node. A new configuration node is activated in response to configuration node failures. The new configuration node retrieves client subscription information about events occurring in storage devices managed by the SVC cluster from the storage devices. In response to events occurring in the storage device managed by the SVC cluster, the new configuration node obtains storage device event information from a storage device event monitoring unit. The new configuration node sends storage device events to clients who have subscribed to this information according to subscription information obtained. The storage device is not installed in the original configuration node. This method allows complete transparency of the configuration node failover process to clients. | 03-31-2011 |
| 20120297243 | SVC CLUSTER CONFIGURATION NODE FAILOVER SYSTEM AND METHOD - Methods, systems, and computer programs are provided for failover responses to configuration node failures in SVC clusters. An SVC cluster manages a plurality of storage devices and includes a plurality of SVCs interconnected via a network, each SVC acting as a separate node. A storage device event log is saved, with an original configuration node. An entry is made in the storage device event log each time the original configuration node receives storage device events and setting the entry to a negative value indicating a storage device event has not been handled. The entry is set to a positive value indicating the storage device event has been handled after the original configuration node notifies respective subscribed clients about those of the storage device events the original configuration node receives. A new configuration node is activated in response to configuration node failures. | 11-22-2012 |
| 20130290774 | SVC CLUSTER CONFIGURATION NODE FAILOVER - Methods, systems, and computer programs are provided for failover responses to configuration node failures in SVC clusters. An SVC cluster manages a plurality of storage devices and includes a plurality of SVCs interconnected via a network, each SVC acting as a separate node. A storage device event log is saved, with an original configuration node. An entry is made in the storage device event log each time the original configuration node receives storage device events and setting the entry to a negative value indicating a storage device event has not been handled. The entry is set to a positive value indicating the storage device event has been handled after the original configuration node notifies respective subscribed clients about those of the storage device events the original configuration node receives. A new configuration node is activated in response to configuration node failures. | 10-31-2013 |
| 20130297966 | SVC CLUSTER CONFIGURATION NODE FAILOVER - Methods, systems, and computer programs are provided for failover responses to configuration node failures in SVC clusters. An SVC cluster manages a plurality of storage devices and includes a plurality of SVCs interconnected via a network, each SVC acting as a separate node. A storage device event log is saved, with an original configuration node. An entry is made in the storage device event log each time the original configuration node receives storage device events and setting the entry to a negative value indicating a storage device event has not been handled. The entry is set to a positive value indicating the storage device event has been handled after the original configuration node notifies respective subscribed clients about those of the storage device events the original configuration node receives. A new configuration node is activated in response to configuration node failures. | 11-07-2013 |
| 20140359344 | SVC CLUSTER CONFIGURATION NODE FAILOVER - An SVC cluster manages a plurality of storage devices and includes a plurality of SVCs interconnected via a network, each SVC acting as a separate node. A new configuration node is activated in response to configuration node failures. The new configuration node retrieves client subscription information about events occurring in storage devices managed by the SVC cluster from the storage devices. In response to events occurring in the storage device managed by the SVC cluster, the new configuration node obtains storage device event information from a storage device event monitoring unit. The new configuration node sends storage device events to clients who have subscribed to this information according to subscription information obtained. The storage device is not installed in the original configuration node. | 12-04-2014 |
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| 20090130873 | ELECTRICAL CONNECTOR - An electrical connector includes an insulating body and a plurality of signal terminals and ground terminals contained therein. Each terminal includes a contact portion, a foot portion and a connection portion therebetween. The contact portions are arranged in two lines on the insulating body, and the foot portions are arranged in two lines. The locations of the free ends of the foot portions included in one line correspond with the location arrangement of their contact portions. Compared with the free ends of the foot portions of each signal terminal pair in the line, the distance between the free ends of the foot portions of two corresponding adjacent terminals in the other line is increased. | 05-21-2009 |
| 20100285694 | CONNECTOR - An electrical connector comprises a support body, first and second metal cases assembled with the support frame, and first and second terminal groups. The support frame comprises a first tongue part, a second tongue part, and a partition part which partitions the first and second tongue parts. The first terminal group is arranged in the first tongue part, and the second terminal group is arranged in the second tongue part. The support frame is sheltered with a metal sheltering casing comprising a front sheltering casing and a back sheltering casing which are assembled together. First and second holding plates extend from the first and second metal casings, the front sheltering casing is provided with notches, the support frame is provided with recesses, so that the first and second holding plates are held in the notches and recesses. | 11-11-2010 |
| 20120289077 | ELECTRICAL CONNECTOR - An electrical connector comprises an insulating seat, a plurality of conductive terminals inserted on the insulating seat, and a cage covering on the insulating seat. The insulating seat comprises a body, a tongue plate projecting forward from the body for the arrangement of the conductive terminals, and a bottom plate extending along from the body under the tongue plate. The cage includes a bottom wall located between the tongue plate and the bottom plate of the insulating seat. The electrical connector further comprises a securing part for securing the insulating seat. The securing part comprises a main body abutting above the bottom plate of the insulating seat and two soldering parts bend downwards and extending from two ends of the main body respectively. | 11-15-2012 |
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| 20110202342 | MULTI-MODAL WEB INTERACTION OVER WIRELESS NETWORK - A system, apparatus, and method is disclosed for receiving user input at a client device, interpreting the user input to identify a selection of at least one of a plurality of web interaction modes, producing a corresponding client request based in part on the user input and the web interaction mode; and sending the client request to a server via a network. | 08-18-2011 |
| 20130027981 | HOLD-UP TIME EXTENSION CIRCUIT FOR A POWER CONVERTER - A power system has a power converter adapted for converting a first input voltage at an input thereof to a first output voltage at an output thereof, and a hold-up time extension circuit comprising a step-up stage and a step-down stage coupled to each other via a first energy-storage capacitor, where an input of the step-up stage is coupled to the input of the power converter, an output of the step-up stage is coupled to an input of the step-down stage, and an output of the step-down stage is coupled to the input of the power converter. The step-up stage is adapted for converting the first input voltage of the power converter to a second output voltage, and the step-down stage is adapted for converting the second output voltage of the step-up stage to the input voltage of the power converter. | 01-31-2013 |
| 20130041742 | CONTROL METHOD AND CORRESPONDING SYSTEM FOR OBTAINING COUPONS THROUGH COUPON TERMINAL - A control method for obtaining a coupon by a coupon terminal is disclosed. The method includes: step a. receiving request information for obtaining a coupon; step b. providing a coupon according to the request information; step c. deducting points corresponding to provided coupon from an account corresponding to the request information; step d. adaptively recording the provided coupon in a database; and step e. performing a statistics analysis on the provided coupon stored in the database. A control apparatus for obtaining a coupon by a coupon terminal is also disclosed. According to the present technical solution, by using the existing internet technology and RFID technology, a user may conveniently obtain required coupons by the coupon terminal, and download and print the coupons. | 02-14-2013 |
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| 20120171854 | METHOD FOR FORMING METAL GATE - A method for forming a metal gate includes providing a substrate, subsequently forming a dummy gate on the substrate, forming spacers on sidewalls of the dummy gate, forming a stop layer on the substrate, the dummy gate and spacers of the dummy gate, and forming a sacrificial dielectric layer on the dummy gate and the stop layer. The method further includes removing a part of the sacrificial dielectric layer and the stop layer until the dummy gate is exposed and, removing a residual sacrificial dielectric layer, depositing an interlayer dielectric layer on the dummy gate and the stop layer, polishing the interlayer dielectric layer until the dummy gate is exposed, removing the dummy gate to form a trench, and forming a metal gate in the trench. The interlayer dielectric layer is flat and substantially flush with the dummy gate, so that no recesses are formed thereon. | 07-05-2012 |
| 20120235243 | METHOD OF FORMING A GATE PATTERN AND A SEMICONDUCTOR DEVICE - This disclosure is directed to a method of forming a gate pattern and a semiconductor device. The method comprises: providing a plurality of stacked structures which are parallel to each other and extend continuously in a first direction, and which are composed of a gate material bar and an etching barrier bar thereon; leaving second resist regions between gaps to be formed adjacent to each other across gate bars by a second photolithography process; selectively removing the etching barrier bars by a second etching process; forming a third resist layer having a plurality of openings parallel to each other and extending continuously in a second direction substantially perpendicular to the first direction by a third photolithography process; and forming the gate pattern by a third etching process. The method is capable of having a larger photolithography process window and better controlling the shape and size of a gate pattern. | 09-20-2012 |
| 20120276727 | METHOD OF FORMING GATE PATTERN AND SEMICONDUCTOR DEVICE - This disclosure relates to a method of forming a gate pattern and a semiconductor device. The gate pattern comprises a plurality of parallel gate bars, and each gate bar is broken up by gaps. The method comprises: making an etching characteristic of a gate material layer at least at positions where the gaps are to be formed different from that at remaining positions; forming a plurality of parallel openings in a second resist layer; performing a first etching process on the gate material layer with the second resist layer as a mask, wherein portions of the gate material layer at least at the positions where the gaps are to be formed are selectively left; and performing a second etching process on the gate material layer so as to selectively remove the portions. This method can more accurately control the shape and size of the gate pattern. | 11-01-2012 |
| 20140138800 | SMALL PITCH PATTERNS AND FABRICATION METHOD - A method is provided for fabricating small pitch patterns. The method includes providing a semiconductor substrate, and forming a target material layer having a first region and a second region on the semiconductor substrate. The method also includes forming a plurality of discrete first sacrificial layers on the first region of the target material layer and a plurality of discrete second sacrificial layers on the second region of the target material layer, and forming first sidewall spacers on both sides of the discrete first sacrificial layers and the discrete second sacrificial layers. Further, the method includes removing the first sacrificial layers and the second sacrificial layers, and forming second sidewall spacers. Further, the method also includes forming discrete repeating patterns in the first region of the target material layer and a continuous pattern in the second region of the target material layer. | 05-22-2014 |
| 20150061047 | CAPACITIVE PRESSURE SENSORS AND FABRICATION METHODS THEREOF - A capacitive pressure sensor is provided. The capacitive pressure sensor includes a substrate; and a first electrode formed in one surface of the substrate and vertical to the surface of the substrate. The capacitive pressure sensor also includes a second electrode with a portion facing the first sub-electrode, a portion facing the second sub-electrode and a portion formed in the other surface of the substrate. Further, the capacitive pressure sensor includes a first chamber between the first electrode and the second electrode and a second chamber formed in the second electrode. Further, the pressure sensor also includes a first sealing layer formed on the second electrode; and a second sealing layer formed on the other surface of the substrate. | 03-05-2015 |
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| 20100205373 | SMART SD CARD AND METHOD OF ACCESSING THE SAME - A smart SD card and a method of accessing the same are disclosed, which resolve a problem of incompatibilities between drivers of various smart SD cards. The smart SD card includes a SD interface ( | 08-12-2010 |
| 20120158594 | TRANSFER METHOD OF ELECTRONIC CASH - A card to card transfer method used in the financial system is provided in the present invention, and comprises an initializing step, a transferring step and a transaction confirming step, wherein the initializing step includes the steps of calculating and obtaining the public key certificate and checking the amount of the transaction and so on, and the transferring step includes the steps of performing the transaction and so on. The present invention can achieve the function of transferring the electronic cash between two cards and can prevent the risk of repeatedly transferring the money into the card for transfer-in by using the card for transfer-out and so on. | 06-21-2012 |
| 20120246476 | MULTI-APPLICATION SMART CARD, AND SYSTEM AND METHOD FOR MULTI-APPLICATION MANAGEMENT OF SMART CARD - A multi-application smart card and a multi-application management system and method for the smart card are provided. The multi-application smart card comprises a management device for the application security domain, and the management device is use to manage and maintain the application security domains in the multi-application smart card, and the application security domains comprise a plurality of issuer application security domains which share the control right of the multi-application smart card. Optionally, the application security domains also comprise at least one cardholder application security domain which is subordinate to the issuer application security domain that creates the cardholder application security domain, and wherein the at least one cardholder application security domain is used to manage and maintain the applications created by the cardholder. | 09-27-2012 |
| 20120311001 | SMARTCARD FILE SYSTEM AND FILE SELECTION METHOD THEREOF - The invention provides a Smartcard file system and its method for selecting file. Said file system, including MF as well as a variety of DFs and Efs in the MF, wherein application root directory (ADF) is added in the MF; the tile attributes of said ADF, DF and EF of the tile system include the Application Identifier (AID); when visiting with HTTP protocol, the AID is understood as a long file name. External entities accessing said file system with the HTTP protocol, namely locating the application and file managed with CWS via URL; in URL, AID of directory or file identities its long file name, so that Smartcard file system also can support long file system and the way of selecting file of URL, which makes Smartcard to support the WEB services easier and more accepted by the user. | 12-06-2012 |
| 20130290718 | MOBILE STORAGE DEVICE AND THE DATA PROCESSING SYSTEM AND METHOD BASED THEREON - The present invention relates to network security technology, and particularly relates to a mobile storage device for data processing in security, and a data processing system comprising the mobile storage device, and a data processing method using the data processing system. According to the present invention, the mobile storage device for data processing in security comprising: at least one memory for storing a secret key; an interface circuit; and a processing unit for communicating with a remote device via the interface circuit and performing security processing and application processing, the security processing including data encryption and decryption with the secret key. Compared with the prior art, the mobile storage device according to the embodiments of the present invention stores not only confidential information such as secret key and digital certificate but also applications for executing transaction processes, whereby providing security protection for the applications at the same level as the confidential information. In addition, where the mobile storage device has a capability of simulating a network interface, a client terminal, such as a personal computer, previously used for executing the applications now can function as a bridge connector between the mobile storage device and a remote server, and the packeting and unpacketing of the transaction data can be performed inside the mobile storage device. This greatly improves the security performance of the transaction processes. | 10-31-2013 |
| 20130325994 | ETHERNET COMMUNICATION SYSTEM AND METHOD BASED ON MMC/SD INTERFACE - The present invention is directed to an Ethernet communication method and system which are based on the MMC/SD interface. In the invention, the communication system includes at least one master device and at least one slave device, the at least one master device and the at least one slave device are connected via MMC/SD interface and communicate with each other on the Ethernet. The Ethernet communication method and system disclosed herein enables the device with the MMC/SD interface to act as a node in the network, and thus greatly expanding the application domain of such devices. | 12-05-2013 |
| 20140164252 | USER TERMINAL AND PAYMENT SYSTEM - The invention provides a user terminal and a payment system. The user terminal comprises an input device, a multi-channel selection switch, an application module, a processor, a password processing module, and a security IC chip containing information on user's ID and/or banking card therein, wherein the multi-channel selection switch is coupled with the input device, the password processing module and the processor, the password processing module is coupled with the processor, and the security IC chip is coupled with the password processing module; the application module controls the multi-channel selection switch via the processor so as to place the user terminal in a password input mode or in a normal input mode. The invention ensures the safety in entering the user's password in hardware configuration so that even when software system of the user terminal is not safe in itself, the safety of input password can be ensured. | 06-12-2014 |
| 20140172605 | SAFETY CLOSED-LOOP PAYMENT SYSTEM AND METHOD - The invention relates to a safety closed-loop payment system and method. The safety closed-loop payment system of the invention comprises a user terminal ( | 06-19-2014 |
| 20140359362 | INFORMATION INTERACTION TEST DEVICE AND METHOD BASED ON AUTOMATIC GENERATION OF ASSOCIATED TEST CASES - The present invention proposes an information interaction testing device and method based on the associated testing case automatic generation. The associated testing case generation module in said device may automatically generate the associated testing case files corresponding to all associated information interactions which can be triggered by said reference information interaction based on the reference information interaction and the predefined rules determined by the application type provided by the system under test. The information interaction testing device and method based on the associated testing case automatic generation disclosed in the present invention have the higher testing speed and the higher testing usability as well as are low-cost. | 12-04-2014 |
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| 20100311991 | PROCESS FOR THE PREPARATION OF DOCETAXEL, ITS INTERMEDIATES, AND METHODS FOR PREPARATION THEREOF - The present invention disclosed an process for preparing docetaxel 1, including the following steps: a) hydroxyl acylation reaction of compound 2 and 3 to obtain compound 4; b) deprotection group R | 12-09-2010 |
| 20110306763 | PROCESS FOR THE PREPARATION OF IMATINIB AND SALTS THEREOF - Disclosed herein is a process for preparation of imatinib free base which comprises condensing 4-Methyl-N-(4-pyridin-3-yl-pyrimidin-2-yl)-benzene-1,3-diamine with 4-(4-Methyl-piperazin-1-ylmethyl)-benzoic acid ester in the presence of base including organic bases and inorganic bases in an organic solvent to form imatinib. | 12-15-2011 |
| 20130041149 | New Method for Synthesizing Imatinib - In the present invention, a synthesis method of Imatinib is disclosed, which comprises the following steps: the Imatinib, namely 4-(4-methyl-piperazin-1-ylmethyl)-N-[4-methyl-3-[4-(3-pyridinyl)-pyrimidin-2-ylamino]-benzamide shown in formula (III), is formed by reacting 4-methyl-N-3-(4-pyridin-3-yl-pyrimidin-2-yl)-1,3-benzenediamine shown in formula (I) with 4-(4-methyl-piperazin-1-methyl)-benzoic ester shown in formula (II), under the action of a base and in a non-protonic organic solvent, | 02-14-2013 |
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| 20100016590 | NILOTINIB INTERMEDIATES AND PREPARATION THEREOF - Intermediates of Nilotinib were prepared, including, for example, 3-(trifluoromethyl-5-(4-methyl-1H-imidazole-1-yl)-benzeneamine; 3-(4-(pyridin-3-yl)pyrimidin-2-ylamino) -4-methylbenzoyl halogen dihydrochloride; and N-(3-Bromo-5-trifluoromethylphenyl)-4-methyl-3-[[4-(3-pyridinyl)-2-pyrimidinyl]amino]benzamide. Nilotinib.3HCl and its crystalline forms are also described. | 01-21-2010 |
| 20110306792 | PROCESS FOR PREPARING TOLTERODINE AND THE L-TARTRATE THEREOF - The present invention relates to a process for preparing tolterodine and the L-tartrate thereof. The preparation consists of the following steps: A) ammonolysis reaction between diisopropylamine and compound 2 (3,4-dihydro-6-methyl-4-phenyl-2H-benzopyran-2-one) activated by an activator to afford the amide 3; B) reduction of the amide by a reductant to give compound 1, i.e., racemic tolterodine free base; C) Resolution of the tolterodine free base to afford tolterodine L-tartrate. The present route is very short and suitable for industrial production. | 12-15-2011 |
| 20130046100 | S-5-SUBSTITUENT-N-2'-(THIOPHENE-2-YL)ETHYL-TETRALIN-2-AMINE OR CHIRAL ACID SALTS THEREOF AND USE FOR PREPARING ROTIGOTINE - The chiral compound S-5-substituted-N-2′-(thienyl-2-yl-)ethyl-tetralin-2-amine or its chiral acid salts and preparation method thereof are disclosed, and the method for preparing Rotigotine by using the chiral compound is also disclosed. Racemic 5-substituted-N-2′-(thien-2-yl-)ethyl-tetralin-2-amine (compound 1) is resolved by using a conventional chiral acid to obtain an optically pure chiral acid salt of S-5-substituted-N-2′-(thien-2-yl-)ethyl-tetralin-2-amine, which is then dissociated to obtain S-5-substituted-N-2′-(thien-2-yl-)ethyl-tetralin-2-amine (compound 2). The compound 2 or chiral acid salt thereof is alkylated and deprotected to produce rotigotine (compound 5). | 02-21-2013 |
| 20130331561 | Method of Preparation of Antiviral Compounds and Useful Intermediates Thereof - The invention is directed to processes for synthesizing bicyclic nucleoside antiviral compounds and for synthesizing the intermediates used in the process. The invention is also directed to novel intermediate compounds useful in the process. The anti-viral compounds are useful in the treatment of herpes zoster (i.e., varicella zoster virus, VZV, shingles) and for the prevention of post herpetic neuralgia (PHN) resulting from this viral infection. | 12-12-2013 |
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| 20110306363 | METHOD, APPARATUS AND SYSTEM FOR OPTIMIZING AND UPDATING TRACKING AREA - The present invention relates to the field of mobile communication technologies, and discloses a method, an apparatus, and a system for optimizing a tracking area, and a method, an apparatus, and a system for updating a tracking area. The method for optimizing a tracking area includes the following steps: an Operation, Administration and Maintenance entity obtains an optimization threshold, and performs a tracking area optimization according to the optimization threshold. With the present invention, the Operation, Administration and Maintenance entity can optimize the tracking area automatically. | 12-15-2011 |
| 20150056981 | METHOD, APPARATUS, AND SYSTEM FOR DETERMINING A LINK COVERAGE PROBLEM - A method, apparatus, and system for determining link coverage problem are disclosed. Downlink measurement data and uplink measurement data are correlated to perform analysis, so that determining of a link coverage problem no longer depends only on the downlink measurement data, but depends on a combination of the downlink measurement data and the uplink measurement data. In this way, the determining of the link coverage problem is more accurate, which facilitates subsequent use of a correct solution. | 02-26-2015 |
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| 20120264287 | METHOD FOR FORMING AN INTERCONNECT STRUCTURE - A method for forming an interconnect structure includes providing a semiconductor substrate having a barrier layer, a low dielectric constant (Low K) inter-dielectric layer and a cap dielectric layer sequentially formed thereon; etching the cap dielectric layer and the Low K inter-dielectric layer sequentially until the barrier layer is exposed and a groove is formed; removing the cap dielectric layer until the Low K inter-dielectric layer is exposed; and doping a carbon element into the Low K inter-dielectric layer. The advantages of the method includes a decrease of the dielectric constant of the Low K inter-dielectric layer, thus, reduces the resistive-capacitive (RC) delay of interconnect layers of a semiconductor device and improve its operating speed and performance. | 10-18-2012 |
| 20140042559 | HIGH-K LAYERS, TRANSISTORS, AND FABRICATION METHOD - A method is provided for fabricating a High-K layer. The method includes providing a substrate, applying a first precursor gas on the substrate such that the substrate absorbs first precursor gas molecules in a chemical absorption process, and removing the unabsorbed first precursor gas using a first inert gas. The method also includes applying a second precursor gas on the substrate, and forming a first thin film on the substrate as a reaction product of the second precursor gas and the absorbed first precursor gas molecules. Further, the method includes removing unreacted second precursor gas and byproducts using a second inert gas, and forming a high-K layer on the substrate by forming a plurality of the first thin films layer-by-layer. | 02-13-2014 |
| 20140191301 | TRANSISTOR AND FABRICATION METHOD - Transistors and fabrication methods are provided. A first sidewall can be formed on each sidewall of a gate structure. A second sidewall can be formed on the first sidewall. The first sidewall can be made of a doped material. After forming a source and a drain, a metal silicide layer can be formed on the source and the drain. The second sidewall can be removed to expose a surface portion of the semiconductor substrate between the metal silicide layer and the first silicide layer. A stress layer can be formed on the exposed surface portion of the semiconductor substrate, on the metal silicide layer, on the first sidewall, and on the gate. | 07-10-2014 |
| 20150061028 | TRANSISTORS AND FABRICATION METHODS THEREOF - A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate having a first region; and forming a first gate structure on a surface of the semiconductor substrate in the first region. The method also includes forming trenches in the semiconductor substrate at both sides of the first gate structure; and forming a first stress layer with one surface lower than the surface of the semiconductor substrate in the trenches. Further, the method includes forming a second stress layer containing carbon atoms with a surface leveling with or higher than the surface of the semiconductor substrate on the first stress layer; and forming a source region and a drain region in the semiconductor substrate at both sides of the first gate structure. | 03-05-2015 |
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| 20120161092 | PHASE CHANGE MEMORY AND METHOD FOR FABRICATING THE SAME - The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, a plurality of peripheral shallow trench isolation (STI) units in the peripheral substrate, and at least one MOS transistor on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, a plurality of vertical LEDs on the N-type ion buried layer, a plurality of storage shallow trench isolation (STI) units between the vertical LEDs, and a plurality of phase change layers on the vertical LED and between the storage STI units. The storage STI units have thickness substantially equal to thickness of the vertical LEDs. The peripheral STI units have thickness substantially equal to thickness of the storage STI units. The N-type conductive region contains SiC. A top of P-type conductive region is flush with a top of the peripheral substrate. The N-type conductive region containing SiC reduces drain current through the vertical LED and raises current efficiency of the vertical LED. The peripheral circuit region can work normally without adverse influence on performance of the phase change memory. | 06-28-2012 |
| 20120161097 | PHASE CHANGE MEMORY AND METHOD FOR FABRICATING THE SAME - The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, peripheral shallow trench isolation (STI) units in the peripheral substrate, and MOS transistors on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, vertical LEDs on the on the N-type ion buried layer, storage shallow trench isolation (STI) units between the vertical LEDs, and phase change layers on the vertical LEDs and between the storage STI units. The storage STI units have thickness equal to thickness of the vertical LEDs. Each vertical LED comprises an N-type conductive region on the N-type ion buried layer, and a P-type conductive region on the N-type conductive region. The P-type conductive region contains SiGe. The peripheral STI units have thickness equal to thickness of the storage STI units. A top of P-type conductive region is flush with a top of the peripheral substrate. The P-type conductive region containing SiGe reduces drain current through the vertical LED and raises current efficiency of the vertical LED. The peripheral circuit region can work normally without adverse influence on performance of the phase change memory. | 06-28-2012 |
| 20130264537 | PHASE CHANGE MEMORY AND METHOD FOR FABRICATING THE SAME - The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, a plurality of peripheral shallow trench isolation (STI) units in the peripheral substrate, and at least one MOS transistor on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, a plurality of vertical LEDs on the N-type ion buried layer, a plurality of storage shallow trench isolation (STI) units between the vertical LEDs, and a plurality of phase change layers on the vertical LED and between the storage STI units. | 10-10-2013 |
| 20130320416 | SEMICONDUCTOR DEVICE - A semiconductor device and a method for forming the same are provided. The method includes: providing a substrate having a gate structure and first spacers on both sidewalls of the gate structure formed on a top surface of the substrate; forming first openings in the substrate by using the first spacers as a mask, wherein the first openings are located on both sides of the gate structure; forming second openings by etching the first openings with an etching gas, wherein each of the second openings is an expansion of a corresponding one of the first openings toward the gate structure and extends to underneath an adjacent first spacer; and forming epitaxial layers in the first openings and the second openings. | 12-05-2013 |
| 20140191301 | TRANSISTOR AND FABRICATION METHOD - Transistors and fabrication methods are provided. A first sidewall can be formed on each sidewall of a gate structure. A second sidewall can be formed on the first sidewall. The first sidewall can be made of a doped material. After forming a source and a drain, a metal silicide layer can be formed on the source and the drain. The second sidewall can be removed to expose a surface portion of the semiconductor substrate between the metal silicide layer and the first silicide layer. A stress layer can be formed on the exposed surface portion of the semiconductor substrate, on the metal silicide layer, on the first sidewall, and on the gate. | 07-10-2014 |
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| 20100064385 | CROP GRAIN FILLING GENE GIF1 AND THE APPLICATIONS THEREOF - A novel crop grain filling gene (GIF1) and the applications thereof are presented in the invention. The GIF1 gene can be applied to control grain filling, enhance crop yield or quality, or improve disease resistance or storage stability of crop grains. A method for improving crops is also presented in the invention. The GIF1 gene shows valuable potentials in controlling crop yield, quality, storage, and resistance to diseases. | 03-11-2010 |
| 20110093966 | PLANT HEIGHT REGULATORY GENE AND USES THEREOF - Provided are a crop height regulatory gene from | 04-21-2011 |
| 20130160164 | CROP GRAIN FILLING GENE (GIF1) AND THE APPLICATIONS THEREOF - Novel crop grain filling genes (GIF1) and the applications thereof are presented in the invention. The GIF1 genes can be applied to control grain filling, enhance crop yield or quality, or improve disease resistance or storage stability of crop grains. A method for improving crops is also presented in the invention. The GIF1 genes shows valuable potentials in controlling crop yield, quality, storage, and resistance to diseases. | 06-20-2013 |
| 20130247242 | PLANT HEIGHT REGULATORY GENE AND USES THEREOF - Provided are a crop height regulatory gene from | 09-19-2013 |
| 20140317782 | HIGH TEMPERATURE RESISTANT PLANT GENE AND USE THEREOF - Provided are a high temperature resistant plant gene and use thereof. The high temperature resistant gene can not only be used to modify she high temperature resistant property of a plant, but also has the functions of promoting plant growth, improving plant yield and increasing plant biomass and the like. The gene can also be utilized in the field of plant breeding to cultivate fine seed strain. | 10-23-2014 |
