Patent application number | Description | Published |
20090022771 | BIOMATERIAL - A process for the preparation of a composite biomaterial comprising an inorganic material and an organic material, the process comprising: (a) providing a first slurry composition comprising a liquid carrier, an inorganic material and an organic material; (b) providing a mould for the slurry; (c) depositing the slurry in the mould; (d) cooling the slurry deposited in the mould to a temperature at which the liquid carrier transforms into a plurality of solid crystals or particles; (e) removing at least some of the plurality of solid crystals or particles by sublimation and/or evaporation to leave a porous composite material comprising an inorganic material and an organic material; and (f) removing the material from the mould. | 01-22-2009 |
20100166830 | Bioactive Scaffold for Therapeutic and Adhesion Prevention Applications - A device for inhibiting adhesion of apposing human body tissue layers includes a scaffold having a designated mean pore size, relative density, and degradation half-life. The scaffold may be operably positioned between apposing tissue layers, such as proximate adhesiogenic layers at a wound site, so as to permit remesothelialization of the tissue without formation of fibrous adhesions. The scaffold device of the invention inhibits adhesion formation by promoting contractile cell migration away from the wound site for a predetermined period of time. The invention further relates to device and methods for promoting internal tissue regeneration, and for provision and/or dispensation of therapeutic and/or diagnostic agents in vivo. | 07-01-2010 |
20100248368 | BIOMATERIAL - A process for the preparation of a composite biomaterial comprising: providing a first substantially solid component comprising one or more of collagen, a glycosaminoglycan, albumin, hyaluronan, chitosan, and synthetic polypeptides comprising a portion of the polypeptide sequence of collagen, and optionally an inorganic material, said component having at least a surface portion that is porous; providing a fluid composition comprising one or more of collagen, a glycosaminoglycan, albumin, hyaluronan, chitosan, and synthetic polypeptides comprising a portion of the polypeptide sequence of collagen, and a liquid carrier, and optionally an inorganic material; contacting said fluid composition with said porous surface portion of said first component; cooling said fluid composition to a temperature at which the liquid carrier transforms into a plurality of solid crystals or particles; removing at least some of the plurality of solid crystals or particles by sublimation and/or evaporation. | 09-30-2010 |
20120294925 | BIOMATERIAL - A process for the preparation of a composite biomaterial comprising an inorganic material and an organic material, the process comprising: (a) providing a first slurry composition comprising a liquid carrier, an inorganic material and an organic material; (b) providing a mould for the slurry; (c) depositing the slurry in the mould; (d) cooling the slurry deposited in the mould to a temperature at which the liquid carrier transforms into a plurality of solid crystals or particles; (e) removing at least some of the plurality of solid crystals or particles by sublimation and/or evaporation to leave a porous composite material comprising an inorganic material and an organic material; and (f) removing the material from the mould. | 11-22-2012 |
Patent application number | Description | Published |
20140372952 | Simplified Data Input in Electronic Documents - Simplified data and/or syntax entry in electronic documents is provided. Custom user interface components and selectable controls may be provided that may float on a displayed document and allow for easier data or syntax input. Electronic inking gestures may be used for entry of data and/or programming syntax in an electronic scratch pad and/or directly on top of a displayed electronic document. Gestures (e.g., screen touches) may be used for selecting document components (e.g., spreadsheet ranges) followed by an interpretation by the associated application of the user's gestures. A variety of disambiguation displays, interactions and/or hints may be provided to help a user clarify ambiguous UI selections. | 12-18-2014 |
20150135054 | Comments on Named Objects - Associating comments with named objects is provided. A document may include a comment attached to a named object (e.g., a chart, a named range, a table, a pivot table, a piece of data in a pivot table, a shape, a picture, a graphic, clip art, an object within an object, etc.). The document may also comprise metadata associated with the comment that may include information such as the named object to which the comment is attached. If the named object is moved, the comment may remain attached to the object and accordingly, may be moved with the object. Attaching a comment to a named object via selecting the comment from a comments pane, dragging, and then dropping the comment onto the named object is also provided. | 05-14-2015 |
Patent application number | Description | Published |
20100208869 | MEASURING STRAIN OF EPITAXIAL FILMS USING MICRO X-RAY DIFFRACTION FOR IN-LINE METROLOGY - In a method for use of x-ray diffraction to measure the strain on the top silicon germanium layer of an SOI substrate, the location of the peak diffraction area of an upper silicon layer of the SOI substrate is determined by first determining the peak diffraction area of the upper silicon layer on a reference pad (where the SOI thickness is about 700-900 Angstroms) within a die formed on a semiconductor wafer. The x-ray beam then moves to that location on the pad of interest to be measured and begins the XRD scan on the pad of interest to ultimately determine the strain of the top silicon germanium layer of the pad of interest | 08-19-2010 |
20110316046 | Field Effect Transistor Device - A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material. | 12-29-2011 |
20120146050 | MEASUREMENT OF CMOS DEVICE CHANNEL STRAIN BY X-RAY DIFFRACTION - A direct measurement of lattice spacing by X-ray diffraction is performed on a periodic array of unit structures provided on a substrate including semiconductor devices. Each unit structure includes a single crystalline strained material region and at least one stress-generating material region. For example, the single crystalline strained material region may be a structure simulating a channel of a field effect transistor, and the at least one stress-generating material region may be a single crystalline semiconductor region in epitaxial alignment with the single crystalline strained material region. The direct measurement can be performed in-situ at various processing states to provide in-line monitoring of the strain in field effect transistors in actual semiconductor devices. | 06-14-2012 |
20120190216 | ANNEALING TECHNIQUES FOR HIGH PERFORMANCE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE FABRICATION - A semiconductor structure is provided. In some cases, an absorber having a low deposition temperature is applied to at least a portion of the structure. At least a portion of the structure is subjected to a long flash anneal process. | 07-26-2012 |
20130175547 | FIELD EFFECT TRANSISTOR DEVICE - A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material. | 07-11-2013 |
20140080275 | Multigate FinFETs with Epitaxially-Grown Merged Source/Drains - Method of forming multi-gate finFETs with epitaxially-grown merged source/drains. Embodiments of the invention may include forming a plurality of semiconductor fins joined by a plurality of inter-fin semiconductor regions, depositing a sacrificial gate over a center portion of each of the plurality of fins, forming a first merge layer over a first end of each of the plurality of fins to form a first merged fin region, forming a second merge layer over the second end of each of the plurality of fins to form a second merged fin region, etching a portion of the first merged fin region to form a first source/drain base region, etching a portion of the second merged fin region to form a second source/drain base region, forming a first source/drain region on the first source/drain base region, and forming a second source/drain region on the second source/drain base region. | 03-20-2014 |
20140159161 | MEASUREMENT OF CMOS DEVICE CHANNEL STRAIN BY X-RAY DIFFRACTION - A direct measurement of lattice spacing by X-ray diffraction is performed on a periodic array of unit structures provided on a substrate including semiconductor devices. Each unit structure includes a single crystalline strained material region and at least one stress-generating material region. For example, the single crystalline strained material region may be a structure simulating a channel of a field effect transistor, and the at least one stress-generating material region may be a single crystalline semiconductor region in epitaxial alignment with the single crystalline strained material region. The direct measurement can be performed in-situ at various processing states to provide in-line monitoring of the strain in field effect transistors in actual semiconductor devices. | 06-12-2014 |
20140308782 | SELF-LIMITING SELECTIVE EPITAXY PROCESS FOR PREVENTING MERGER OF SEMICONDUCTOR FINS - A self-limiting selective epitaxy process can be employed on a plurality of semiconductor fins such that the sizes of raised active semiconductor regions formed by the selective epitaxy process are limited to dimensions determined by the sizes of the semiconductor fins. Specifically, the self-limiting selective epitaxy process limits growth of the semiconductor material along directions that are perpendicular to crystallographic facets formed during the selective epitaxy process. Once the crystallographic facets become adjoined to one another or to a dielectric surface, growth of the semiconductor material terminates, thereby preventing merger among epitaxially deposited semiconductor materials. | 10-16-2014 |
20150014773 | Partial FIN On Oxide For Improved Electrical Isolation Of Raised Active Regions - A semiconductor fin suspended above a top surface of a semiconductor layer and supported by a gate structure is formed. An insulator layer is formed between the top surface of the semiconductor layer and the gate structure. A gate spacer is formed, and physically exposed portions of the semiconductor fin are removed by an anisotropic etch. Subsequently, physically exposed portions of the insulator layer can be etched with a taper. Alternately, a disposable spacer can be formed prior to an anisotropic etch of the insulator layer. The lateral distance between two openings in the dielectric layer across the gate structure is greater than the lateral distance between outer sidewalls of the gate spacers. Selective deposition of a semiconductor material can be performed to form raised active regions. | 01-15-2015 |
20150137193 | FINFET STRUCTURES WITH FINS RECESSED BENEATH THE GATE - A semiconductor structure may include a semiconductor fin, a gate over the semiconductor fin, a spacer on a sidewall of the gate, an angled recess region in an end of the semiconductor fin beneath the spacer, and a first semiconductor region filling the angled recess. The angled recess may be v-shaped or sigma shaped. The structure may further include a second semiconductor region in contact with the first semiconductor region and the substrate. The structure may be formed by forming a gate above a portion of the semiconductor fin on a substrate, forming a spacer on a sidewall of the gate; removing a portion of the semiconductor fin not covered by the spacer or the gate to expose a sidewall of the fin, etching the sidewall of the fin to form an angled recess region beneath the spacer, and filling the angled recess region with a first epitaxial semiconductor region. | 05-21-2015 |
20150236147 | GRAPHENE TRANSISTOR WITH A SUBLITHOGRAPHIC CHANNEL WIDTH - Silicon-carbon alloy structures can be formed as inverted U-shaped structures around semiconductor fins by a selective epitaxy process. A planarization dielectric layer is formed to fill gaps among the silicon-carbon alloy structures. After planarization, remaining vertical portions of the silicon-carbon alloy structures constitute silicon-carbon alloy fins, which can have sublithographic widths. The semiconductor fins may be replaced with replacement dielectric material fins. In one embodiment, employing a patterned mask layer, sidewalls of the silicon-carbon alloy fins can be removed around end portions of each silicon-carbon alloy fin. An anneal is performed to covert surface portions of the silicon-carbon alloy fins into graphene layers. In one embodiment, each graphene layer can include only a horizontal portion in a channel region, and include a horizontal portion and sidewall portions in source and drain regions. If a patterned mask layer is not employed, each graphene layer can include only a horizontal portion. | 08-20-2015 |
20150270332 | SINGLE-CRYSTAL SOURCE-DRAIN MERGED BY POLYCRYSTALLINE MATERIAL - A method of forming a semiconductor structure includes forming a first fin and a second fin on a substrate. A gate structure is formed over a first portion of the first fin and the second fin without covering a second portion of the first fin and the second fin. Single-crystal epitaxial layers are deposited surrounding the second portion of the first fin and the second fin such that the single-crystal epitaxial layer on the first fin does not contact the single-crystal epitaxial layer on the second fin. A polycrystalline layer is then deposited surrounding the single-crystal epitaxial layers, so that the polycrystalline layer contacts the single-crystal epitaxial layer on the first fin and the single-crystal epitaxial layer on the second fin. The single-crystal epitaxial layers and the polycrystalline layer form a merged source-drain region. | 09-24-2015 |
20150325406 | SEMICONDUCTOR INSPECTION SYSTEM INCLUDING REFERENCE IMAGE GENERATOR - A semiconductor substrate inspection system includes an e-beam inspection system configured to deliver electrons to a specimen semiconductor substrate. A sensor is configured to detect reflected electrons that reflect off the surface of the specimen semiconductor substrate. An analysis unit is configured to determine a number of electrons received by the semiconductor substrate, and to determine at least one target region including at least one defect of the semiconductor substrate. A reference image module is in electrical communication with the analysis unit. The reference image module is configured to generate a first digital image having a plurality of pixels, and to adjust a gray-scale level of the pixels included in the target region based on the number electrons included in each pixel to generate a second digital image that excludes the at least one defect. | 11-12-2015 |
20150340465 | METHOD FOR EMBEDDED DIAMOND-SHAPED STRESS ELEMENT - A method of manufacturing a semiconductor device with an embedded layer, by anisotropically etching a substrate adjacent to an already formed gate structure. A dummy layer is deposited in the previously etched region, and a second spacer is formed next to the first spacer. The dummy layer is removed, and a second anisotropic etch is performed. A semiconductor substrate is then epitaxially grown in the etched out region to form the embedded layer. | 11-26-2015 |
20150349093 | FINFET WITH DIELECTRIC ISOLATION AFTER GATE MODULE FOR IMPROVED SOURCE AND DRAIN REGION EPITAXIAL GROWTH - A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures. | 12-03-2015 |
20150364603 | FINFET AND NANOWIRE SEMICONDUCTOR DEVICES WITH SUSPENDED CHANNEL REGIONS AND GATE STRUCTURES SURROUNDING THE SUSPENDED CHANNEL REGIONS - A semiconductor device including at least one suspended channel structure of a silicon including material, and a gate structure present on the suspended channel structure. At least one gate dielectric layer is present surrounding the suspended channel structure, and at least one gate conductor is present on the at least one gate dielectric layer. Source and drain structures may be composed of a silicon and germanium including material. The source and drain structures are in contact with the source and drain region ends of the suspended channel structure through a silicon cladding layer. | 12-17-2015 |
20160035878 | FINFET WITH DIELECTRIC ISOLATION AFTER GATE MODULE FOR IMPROVED SOURCE AND DRAIN REGION EPITAXIAL GROWTH - A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures. | 02-04-2016 |
Patent application number | Description | Published |
20100090288 | METHOD OF FORMING SOURCE AND DRAIN OF A FIELD-EFFECT-TRANSISTOR AND STRUCTURE THEREOF - A semiconductor fabrication method involving the use of eSiGe is disclosed. The eSiGe approach is useful for applying the desired stresses to the channel region of a field effect transistor, but also can introduce complications into the semiconductor fabrication process. Embodiments of the present invention disclose a two-step fabrication process in which a first layer of eSiGe is applied using a low hydrogen flow rate, and a second eSiGe layer is applied using a higher hydrogen flow rate. This method provides a way to balance the tradeoff of morphology, and fill consistency when using eSiGe. Embodiments of the present invention promote a pinned morphology, which reduces device sensitivity to epitaxial thickness, while also providing a more consistent fill volume, amongst various device widths, thereby providing a more consistent eSiGe semiconductor fabrication process. | 04-15-2010 |
20100112762 | METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURES - Methods of fabricating a semiconductor structure with a non- epitaxial thin film disposed on a surface of a substrate of the semiconductor structure are disclosed. The methods provide selective non-epitaxial growth (SNEG) or deposition of amorphous and/or polycrystalline materials to form a thin film on the surface thereof. The surface may be a non-crystalline dielectric material or a crystalline material. The SNEG on non-crystalline dielectric further provides selective growth of amorphous/polycrystalline materials on nitride over oxide through careful selection of precursors-carrier-etchant ratio. The non-epitaxial thin film forms resultant and/or intermediate semiconductor structures that may be incorporated into any front-end-of-the-line (FEOL) fabrication process. Such resultant/intermediate structures may be used, for example, but are not limited to: source-drain fabrication; hardmask strengthening; spacer widening; high-aspect-ratio (HAR) vias filling; micro-electro-mechanical-systems (MEMS) fabrication; FEOL resistor fabrication; lining of shallow trench isolations (STI) and deep trenches; critical dimension (CD) tailoring and claddings. | 05-06-2010 |
20120112208 | STRESSED TRANSISTOR WITH IMPROVED METASTABILITY - An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material. | 05-10-2012 |
Patent application number | Description | Published |
20090173941 | METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURES AND STRUCTURES THEREOF - Methods of fabricating a semiconductor structure with a non-epitaxial thin film disposed on a surface of a substrate of the semiconductor structure; and semiconductor structures formed thereof are disclosed. The methods provide selective non-epitaxial growth (SNEG) or deposition of amorphous and/or polycrystalline materials to form a thin film on the surface thereof. The surface may be a non-crystalline dielectric material or a crystalline material. The SNEG on non-crystalline dielectric further provides selective growth of amorphous/polycrystalline materials on nitride over oxide through careful selection of precursors-carrier-etchant ratio. The non-epitaxial thin film forms resultant and/or intermediate semiconductor structures that may be incorporated into any front-end-of-the-line (FEOL) fabrication process. Such resultant/intermediate structures may be used, for example, but are not limited to: source-drain fabrication; hardmask strengthening; spacer widening; high-aspect-ratio (HAR) vias filling; micro-electro-mechanical-systems (MEMS) fabrication; FEOL resistor fabrication; lining of shallow trench isolations (STI) and deep trenches; critical dimension (CD) tailoring and claddings. | 07-09-2009 |
20090294801 | METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE - Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned. | 12-03-2009 |
20120228716 | METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE - A structure including an NFET having an embedded silicon germanium (SiGe) plug in a channel of the NFET; a PFET having a SiGe channel; and a trench isolation between the NFET and the PFET, wherein the NFET and the PFET are devoid of SiGe epitaxial growth edge effects. | 09-13-2012 |
20130134444 | STRESSED TRANSISTOR WITH IMPROVED METASTABILITY - An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material. | 05-30-2013 |
20160093740 | UNIFORM JUNCTION FORMATION IN FINFETS - The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel regions of high density technologies, such as tight pitch FinFET devices, using recessed source-drain (S-D) regions and annealing techniques. In an embodiment, a faceted buffer layer, deposited before the S-D region is formed, may be used to control the profile and dopant concentration of the junction under the channel. In another embodiment, the profile and dopant concentration of the junction may be controlled via a dopant concentration gradient in the S-D region. | 03-31-2016 |
Patent application number | Description | Published |
20130315780 | DIAGNOSTIC SYSTEMS AND INSTRUMENTS - Provided is a clinical diagnostic system that comprises a diagnostic instrument and a disposable cartridge. The diagnostic system can be used to measure assays in point of care clinical settings. | 11-28-2013 |
20130337432 | DIAGNOSTIC SYSTEMS AND CARTRIDGES - In particular, a disposable cartridge is disclosed that is suitable for use with a clinical or diagnostic point-of-care device and capable of performing diagnostic and analytical functions including filtering samples such as plasma from whole blood and running assays and collecting measurements of analytes or biomarkers. | 12-19-2013 |
20150132860 | CLINICAL DIAGNOSTIC SYSTEM INCLUDING INSTRUMENT AND CARTRIDGE - In embodiments disclosed herein, a diagnostic system is provided having a cartridge comprising at least one needle; at least one reservoir; at least one fluidic seal; and at least one fluidic channel of a fluidic pathway, wherein the cartridge is configured to store at least one reagent and at least one waste material on the cartridge. The diagnostic system is provided also having a diagnostic instrument comprising the fluidic pathway; an electrochemiluminescence (ECL) detection system; and a pump, wherein the fluidic pathway begins and ends in the cartridge and has a substantially single direction of flow in a pathway fluidically connecting the diagnostic instrument and the cartridge. | 05-14-2015 |
20150132861 | CLINICAL DIAGNOSTIC SYSTEMS - A diagnostic system is provided herein that includes an instrument comprising an electrochemiluminescence (ECL) detector, and a cartridge configured to fit within a portion of the instrument, wherein the cartridge includes at least one reagent including an ECL label and a blood collection holder. Also provided herein is a system that includes a diagnostic instrument, which includes a pump, an ECL detector, an incubator, a magnet, and an output device, and a cartridge configured to fit within a portion of the diagnostic instrument, a sample holder configured to fit within the cartridge, and a closed fluidic loop between the diagnostic instrument and the cartridge when the cartridge is fit within a portion of the diagnostic instrument, wherein the cartridge is configured to accept a sample from the sample holder and place the sample in fluidic communication with the diagnostic instrument via the closed fluidic loop. | 05-14-2015 |
Patent application number | Description | Published |
20100258291 | HEATED LINERS FOR TREATING SUBSURFACE HYDROCARBON CONTAINING FORMATIONS - A heating system for a subsurface formation includes a first tubular located in the subsurface formation and a second tubular. At least a portion of the first tubular is positioned in the second tubular. At least a portion of two or more electrical conductors are positioned between an outer surface of the first tubular and an inner surface of the second tubular. The electrical conductors are configured to provide heat to the subsurface formation when an electrical current is applied to the electrical conductors. | 10-14-2010 |
20110247817 | HELICAL WINDING OF INSULATED CONDUCTOR HEATERS FOR INSTALLATION - A method for installing two or more heaters in a subsurface formation includes providing a spool having a substantially helical configuration of two or more heaters that have been spooled on the spool. The helical configuration of heaters is unspooled from the spool and the helical configuration of heaters is installed into an opening in a subsurface formation. | 10-13-2011 |
20110247818 | VARIABLE THICKNESS INSULATED CONDUCTORS - A system used to heat a subsurface formation includes an elongated heater at least partially located in an opening in a hydrocarbon containing layer of the formation. The opening extends from the surface of the formation through an overburden section of the formation and into the hydrocarbon containing layer of the formation. The elongated heater includes an electrical conductor, an insulation layer at least partially surrounding the electrical conductor, and an electrically conductive sheath at least partially surrounding the insulation layer. The elongated heater tapers from a larger thickness at a first end of the heater to a smaller thickness at a second end of the heater. The first end is at or near the junction between the overburden section and the hydrocarbon containing layer and the second end is further into the hydrocarbon containing layer. | 10-13-2011 |
20110248018 | INSULATING BLOCKS AND METHODS FOR INSTALLATION IN INSULATED CONDUCTOR HEATERS - An insulated conductor heater may include an electrical conductor that produces heat when an electrical current is provided to the electrical conductor. An electrical insulator at least partially surrounds the electrical conductor. The electrical insulator comprises a resistivity that remains substantially constant, or increases, over time when the electrical conductor produces heat. An outer electrical conductor at least partially surrounds the electrical insulator. | 10-13-2011 |
20120110845 | SYSTEM AND METHOD FOR COUPLING LEAD-IN CONDUCTOR TO INSULATED CONDUCTOR - A method for coupling a lead-in cable to an insulated conductor includes exposing an end portion of a core of the insulated conductor by removing at least a portion of a jacket and an electrical insulator surrounding the end portion of the core. A recess is formed in the electrical insulator at the end of the electrical insulator surrounding the end portion of the core. An end portion of a conductor of the lead-in cable is exposed by removing at least a portion of a sheath and insulation surrounding the end portion of the conductor. The end portion of the core is coupled to the end portion of the conductor. The end portion of the core and the end portion of the conductor are placed in a body filled with electrically insulating material. | 05-10-2012 |
20130086800 | FORMING INSULATED CONDUCTORS USING A FINAL REDUCTION STEP AFTER HEAT TREATING - A method for forming an insulated conductor heater includes placing an insulation layer over at least part of an elongated, cylindrical inner electrical conductor. An elongated, cylindrical outer electrical conductor is placed over at least part of the insulation layer to form the insulated conductor heater. One or more cold working/heat treating steps are performed on the insulated conductor heater. The cold working/heat treating steps include: cold working the insulated conductor heater to reduce a cross-sectional area of the insulated conductor heater by at least about 30% and heat treating the insulated conductor heater at a temperature of at least about 870° C. The cross-sectional area of the insulated conductor heater is then reduced by an amount ranging between about 5% and about 20% to a final cross-sectional area. | 04-11-2013 |
20140034635 | INSULATING BLOCKS AND METHODS FOR INSTALLATION IN INSULATED CONDUCTOR HEATERS - An insulated conductor heater may include an electrical conductor that produces heat when an electrical current is provided to the electrical conductor. An electrical insulator at least partially surrounds the electrical conductor. The electrical insulator comprises a resistivity that remains substantially constant, or increases, over time when the electrical conductor produces heat. An outer electrical conductor at least partially surrounds the electrical insulator. | 02-06-2014 |
20140215809 | FORMING INSULATED CONDUCTORS USING A FINAL REDUCTION STEP AFTER HEAT TREATING - A method for forming an insulated conductor heater includes placing an insulation layer over at least part of an elongated, cylindrical inner electrical conductor, placing an elongated, cylindrical outer electrical conductor over at least part of the insulation layer to form the insulated conductor heater; and performing one or more cold working/heat treating steps on the insulated conductor heater, reducing the cross-sectional area of the insulated conductor heater by at most about 20% to a final cross-sectional area. The cold working/heat treating steps include cold working the insulated conductor heater to reduce a cross-sectional area of the insulated conductor heater; and heat treating the insulated conductor heater at a temperature of at least about 870° C. The insulation layer includes one or more blocks of insulation. | 08-07-2014 |
20150285033 | INSULATED CONDUCTORS FORMED USING A FINAL REDUCTION STEP AFTER HEAT TREATING - An insulated electrical conductor (MI cable) may include an inner electrical conductor, an electrical insulator at least partially surrounding the electrical conductor, and an outer electrical conductor at least partially surrounding the electrical insulator. The insulated electrical conductor may have a substantially continuous length of at least about 100 m. The insulated electrical conductor may have an initial breakdown voltage, over a substantially continuous length of at least about 100 m, of at least about 60 volts per mil of the electrical insulator thickness (about 2400 volts per mm of the electrical insulator thickness) at about 1300° F. (about 700° C.) and about 60 Hz. The insulated electrical conductor may be capable of being coiled around a radius of about 100 times a diameter of the insulated electrical conductor. The outer electrical conductor may have a yield strength based on a 0.2% offset of about 100 kpsi. | 10-08-2015 |
Patent application number | Description | Published |
20080300827 | SYSTEM AND METHOD TO DETERMINE ELECTRIC MOTOR EFFICIENCY NONINTRUSIVELY - A system and method for nonintrusively determining electric motor efficiency includes a processor programmed to, while the motor is in operation, determine a plurality of stator input currents, electrical input data, a rotor speed, a value of stator resistance, and an efficiency of the motor based on the determined rotor speed, the value of stator resistance, the plurality of stator input currents, and the electrical input data. The determination of the rotor speed is based on one of the input power and the plurality of stator input currents. The determination of the value of the stator resistance is based on at least one of a horsepower rating and a combination of the plurality of stator input currents and the electrical input data. The electrical input data includes at least one of an input power and a plurality of stator input voltages. | 12-04-2008 |
20080309366 | System and method for bearing fault detection using stator current noise cancellation - A system and method for detecting incipient mechanical motor faults by way of current noise cancellation is disclosed. The system includes a controller configured to detect indicia of incipient mechanical motor faults. The controller further includes a processor programmed to receive a baseline set of current data from an operating motor and define a noise component in the baseline set of current data. The processor is also programmed to repeatedly receive real-time operating current data from the operating motor and remove the noise component from the operating current data in real-time to isolate any fault components present in the operating current data. The processor is then programmed to generate a fault index for the operating current data based on any isolated fault components. | 12-18-2008 |
20130138651 | SYSTEM AND METHOD EMPLOYING A SELF-ORGANIZING MAP LOAD FEATURE DATABASE TO IDENTIFY ELECTRIC LOAD TYPES OF DIFFERENT ELECTRIC LOADS - A method identifies electric load types of a plurality of different electric loads. The method includes providing a self-organizing map load feature database of a plurality of different electric load types and a plurality of neurons, each of the load types corresponding to a number of the neurons; employing a weight vector for each of the neurons; sensing a voltage signal and a current signal for each of the loads; determining a load feature vector including at least four different load features from the sensed voltage signal and the sensed current signal for a corresponding one of the loads; and identifying by a processor one of the load types by relating the load feature vector to the neurons of the database by identifying the weight vector of one of the neurons corresponding to the one of the load types that is a minimal distance to the load feature vector. | 05-30-2013 |
20140067299 | SYSTEM AND METHOD FOR ELECTRIC LOAD IDENTIFICATION AND CLASSIFICATION EMPLOYING SUPPORT VECTOR MACHINE - A method identifies electric load types of a plurality of different electric loads. The method includes providing a support vector machine load feature database of a plurality of different electric load types; sensing a voltage signal and a current signal for each of the different electric loads; determining a load feature vector including at least six steady-state features with a processor from the sensed voltage signal and the sensed current signal; and identifying one of the different electric load types by relating the load feature vector including the at least six steady-state features to the support vector machine load feature database. | 03-06-2014 |
Patent application number | Description | Published |
20110276674 | RESOLVING INFORMATION IN A MULTITENANT DATABASE ENVIRONMENT - Disclosed herein are techniques for creating a representation of dependency relationships between computing resources within a computing environment. In some implementations, one or more sources for dependency analysis may be identified. Each source may be capable of being accessed to provide computing functionality via the computing environment. Each source may include one or more references to a respective one or more computing resources. Each computing resource may define a unit of the computing functionality available within the computing environment. A plurality of dependency relationships may be identified based on the one or more sources. A dependency relationship representation may be created based on the identified dependency relationships. | 11-10-2011 |
20110276693 | RESOLVING INFORMATION IN A MULTITENANT DATABASE ENVIRONMENT - Disclosed herein are techniques for provisioning computing services. In some implementations, a plurality of computing resources available within a computing environment are identified. The plurality of computing resources may be capable of being used to provide computing services via the computing environment. Each of the computing resources may comprise a respective unit of computing functionality available within the computing environment. A plurality of dependency relationships among the computing resources may be identified. Based on the identified dependency relationships, a first one or more of the computing resources may be selected for inclusion in a license definition. A license conforming to the license definition may provide an entity with access to the computing functionality associated with the first one or more computing resources. | 11-10-2011 |
20110276890 | RESOLVING INFORMATION IN A MULTITENANT DATABASE ENVIRONMENT - Disclosed herein are techniques for identifying computing resources specified by a representation of a computing service. In some implementations, a request to analyze a computing service provided via a computing environment may be received. The computing service may have an activated state in which the computing service is available for use and a deactivated state in which the computing service is not available for use. The computing environment may comprise a plurality of computing resources each defining a variable unit of computing functionality within the computing environment. Each computing resource may be associated with a respective parameter corresponding with a respective parameter value that specifies a level of the variable unit of computing functionality defined by the computing resource. The computing service may be represented by a metadata model comprising a plurality of nodes, at least some of which specify a respective one or more of the parameter values. | 11-10-2011 |
20110276892 | RESOLVING INFORMATION IN A MULTITENANT DATABASE ENVIRONMENT - Disclosed herein are techniques for providing a user interface component. In some implementations, a request for the user interface component may be received at a computing device. The user interface component may have a default visual presentation. A branding override may be selected from a plurality of available branding overrides. The branding override may define a modification to the default visual presentation of the user interface component. The branding override may be selected based on one or more contextual variables associated with the request for the user interface component. The user interface component may be modified in accordance with the selected branding override. The user interface component may be displayed on a display device. | 11-10-2011 |
20140047117 | RESOLVING INFORMATION IN A MULTITENANT DATABASE ENVIRONMENT - Disclosed herein are techniques for creating a representation of dependency relationships between computing resources within a computing environment. In some implementations, one or more sources for dependency analysis may be identified. Each source may be capable of being accessed to provide computing functionality via the computing environment. Each source may include one or more references to a respective one or more computing resources. Each computing resource may define a unit of the computing functionality available within the computing environment. A plurality of dependency relationships may be identified based on the one or more sources. A dependency relationship representation may be created based on the identified dependency relationships. | 02-13-2014 |