Patent application number | Description | Published |
20150186516 | APPARATUS AND METHOD OF GENERATING LOOKUPS AND MAKING DECISIONS FOR PACKET MODIFYING AND FORWARDING IN A SOFTWARE-DEFINED NETWORK ENGINE - Embodiments of the present invention relate to a Lookup and Decision Engine (LDE) for generating lookup keys for input tokens and modifying the input tokens based on contents of lookup results. The input tokens are parsed from network packet headers by a Parser, and the tokens are then modified by the LDE. The modified tokens guide how corresponding network packets will be modified or forwarded by other components in a software-defined networking (SDN) system. The design of the LDE is highly flexible and protocol independent. Conditions and rules for generating lookup keys and for modifying tokens are fully programmable such that the LDE can perform a wide variety of reconfigurable network features and protocols in the SDN system. | 07-02-2015 |
20160085475 | SESSION BASED PACKET MIRRORING IN A NETWORK ASIC - A forwarding pipeline of a forwarding engine includes a mirror bit mask vector with one bit per supported independent mirror session. Each bit in the mirror bit mask vector can be set at any point in the forwarding pipeline when the forwarding engine determines that conditions for a corresponding mirror session are met. At the end of the forwarding pipeline, if any of the bits in the mirror bit mask vector is set, then a packet, the mirror bit mask vector and a pointer to the start of a mirror destination linked list are forwarded to the multicast replication engine. The mirror destination linked list typically defines a rule for mirroring. The multicast replication engine mirrors the packet according to the mirror destination linked list and the mirror bit mask vector. | 03-24-2016 |
20160085644 | MULTICAST REPLICATION ENGINE OF A NETWORK ASIC AND METHODS THEREOF - A multicast replication engine includes a circuit implemented on a network chip to replicate packets, mirror packets and perform link switchovers. The multicast replication engine determines whether a switchover feature is enabled. If the switchover feature is not enabled, then the multicast replication engine mirrors the packet according to a mirror bit mask and to a mirror destination linked list. The mirror destination linked list corresponds to a mirroring rule. If the switchover feature is enabled, then the multicast replication engine replicates the packet according to a first live link of a failover linked list. The failover linked list corresponds to a switchover rule. The mirroring rule and the switchover rule are stored in the same table. Copies of the packet are forwarded according to a multicast rule that is represented by a hierarchical linked list with N tiers. | 03-24-2016 |
20160087808 | FAST HARDWARE SWITCHOVER IN A CONTROL PATH IN A NETWORK ASIC - A multicast destination table contains a list of links. The list of links includes the main link that is currently in use and alternate links to reach the same destination. The links in the list of links are ordered based on a metric. Each of the links is stored as an entry in the multicast destination table. A multicast replication engine traverses the list of links until an enabled link in the list of links is reached, and replicates a packet according to data associated with the enabled link in the list of links. | 03-24-2016 |
20160087809 | HIERARCHICAL HARDWARE LINKED LIST APPROACH FOR MULTICAST REPLICATION ENGINE IN A NETWORK ASIC - A multicast rule is represented in a hierarchical linked list with N tiers. Each tier or level in the hierarchical linked list corresponds to a network layer of a network stack that requires replication. Redundant groups in each tier are eliminated such that the groups in each tier are stored exactly once in a replication table. A multicast replication engine traverses the hierarchical linked list and replicates a packet according to each node in the hierarchical linked list. | 03-24-2016 |
20160117217 | APPARATUS AND A METHOD OF DETECTING ERRORS ON REGISTERS - An error detection circuit on a semiconductor chip detects whether soft errors have affected flip-flop implemented registers on the semiconductor chip. A signature of these flip-flop implemented registers on the semiconductor chip is periodically captured. The signature allows for the integrity of the flip-flop implemented registers to be constantly monitored. A soft error occurring on any of the flip-flop implemented registers can be immediately detected. In response to the detection, an interrupt is raised to notify software to take action. | 04-28-2016 |
20160117271 | SMART HOLDING REGISTERS TO ENABLE MULTIPLE REGISTER ACCESSES - A multiple access mechanism allows sources to simultaneously access different target registers at the same time without using a semaphore. The multiple access mechanism is implemented using N holding registers and source identifiers. The N holding registers are located in each slave engine. Each of the N holding registers is associated with a source and is configured to receive partial updates from the source before pushing the full update to a target register. After the source is finished updating the holding register and the holding register is ready to commit to the target register, a source identifier is added to a register bus. The source identifier identifies the holding register as the originator of the transaction on the register bus. The N holding registers are able to simultaneously handle N register transactions. The max value of N is 2 | 04-28-2016 |
20160117273 | MULTIPLE-INTERRUPT PROPAGATION SCHEME IN A NETWORK ASIC - Embodiments of the present invention are directed to a multiple-interrupt propagation scheme, which is an automated mechanism for the specification and creation of interrupts. Interrupts originating at leaf nodes of a network chip are categorized into different service levels according to their interrupt types and are propagated to a master of the network chip via a manager. For each interrupt, depending on its service level, the manager either instantaneously propagates the interrupt or delays propagation of the interrupt to the master. The master forwards the interrupts to different destinations. A destination can be a processing element that is located on the network chip or externally on a different chip. | 04-28-2016 |
20160117282 | TWO MODES OF A CONFIGURATION INTERFACE OF A NETWORK ASIC - Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module. | 04-28-2016 |