Patent application number | Description | Published |
20100112777 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes forming a bottom electrode having a top surface and a side surface on a semiconductor substrate, performing a tilted ion implantation process to supply ions to the top surface of the bottom electrode and to a portion of the side surface of the bottom electrode, and forming a dielectric layer on the bottom electrode. The formation of the dielectric layer is delayed at the ion-supplied top surface of the bottom electrode and the ion-supplied portion of the side surface of the bottom electrode. | 05-06-2010 |
20120100687 | METHODS FOR FABRICATING CAPACITOR AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICE INCLUDING THE CAPACITOR - Example embodiments relate to methods for fabricating a capacitor and methods for fabricating a semiconductor device including the capacitor. The methods for fabricating a capacitor may include forming a preliminary lower electrode with a first area on a substrate; implanting ions in the preliminary lower electrode to form a lower electrode with a second area that is larger or substantially larger than the first area; and forming a dielectric layer and an upper electrode on the lower electrode. | 04-26-2012 |
20120126300 | CAPACITORS, SEMICONDUCTOR DEVICES INCLUDING THE SAME AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES - A capacitor includes a first electrode, a first dielectric layer disposed on the first electrode, the first dielectric layer having a tetragonal crystal structure and including a first metal oxide layer doped with a first impurity, a second dielectric layer disposed on the first metal oxide layer, the second dielectric layer having a tetragonal crystal structure and including a second metal oxide layer doped with a second impurity, and a second electrode disposed on the second dielectric layer. The first dielectric layer has a lower crystallization temperature and a substantially higher dielectric constant than the second dielectric layer. | 05-24-2012 |
20140183434 | VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF FORMING THE SAME - Semiconductor devices, and methods of fabricating the same, include a metal-containing layer on a semiconductor layer, and a barrier-lowering portion between the metal-containing layer and the semiconductor layer. The barrier-lowering portion lowers a Schottky barrier height between the metal-containing layer and the semiconductor layer below a Schottky barrier height between a metal silicide layer and the semiconductor layer. | 07-03-2014 |
20140264517 | SEMICONDUCTOR DEVICES HAVING A SILICON-GERMANIUM CHANNEL LAYER AND METHODS OF FORMING THE SAME - Semiconductor devices having a silicon-germanium channel layer and methods of forming the semiconductor devices are provided. The methods may include forming a silicon-germanium channel layer on a substrate in a peripheral circuit region and sequentially forming a first insulating layer and a second insulating layer on the silicon-germanium channel layer. The methods may also include forming a conductive layer on the substrate, which includes a cell array region and the peripheral circuit region, and patterning the conductive layer to form a conductive line in the cell array region and a gate electrode in the peripheral circuit region. The first insulating layer may be formed at a first temperature and the second insulating layer may be formed at a second temperature higher than the first temperature. | 09-18-2014 |
20150235959 | WIRING STRUCTURE AND ELECTRONIC DEVICE EMPLOYING THE SAME - Example embodiments relate to a wiring structure, a method of forming the same, and an electronic device employing the same. The wiring structure includes a first conductive material layer and a nanocrystalline graphene layer on the first conductive material layer in direct contact with the metal layer. | 08-20-2015 |
20160035676 | Semiconductor Devices and Methods of Fabricating the Same - Semiconductor devices may include a substrate including an active region defined by a device isolation layer, source/drain regions in the active region, word lines extending in a first direction parallel to the active region and being arranged in a second direction crossing the first direction, a bit line pattern extending in the second direction and crossing over a portion of the active region positioned between the word lines, and a graphene pattern covering at least a portion of the bit line pattern. | 02-04-2016 |
20160104763 | SEMICONDUCTOR DEVICE INCLUDING CAPACITOR AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a lower electrode on a lower structure, a dielectric layer conformally covering a surface of the lower electrode, an upper electrode conformally covering a surface of the dielectric layer, and a barrier layer on the upper electrode. The barrier layer and the upper electrode define a space on a sidewall of the lower electrode. | 04-14-2016 |