Patent application number | Description | Published |
20080197372 | SEMICONDUCTOR STRUCTURES AND METHOD FOR FABRICATING THE SAME - A semiconductor structure is provided. The semiconductor structure includes a substrate, a gate disposed thereon, an insulation layer disposed on the substrate and overlying the gate, a patterned semiconductor layer disposed on the insulation layer, a source and a drain disposed on the patterned semiconductor layer, a protective layer overlying the insulation layer, the source and the boundary of the drain to expose a portion of the drain, and a pixel electrode disposed on the substrate, overlying the protective layer overlying the boundary of the drain, electrically connected to the exposed drain. | 08-21-2008 |
20080213951 | Method of fabricating pixel structure - A method of fabricating a pixel structure including the following procedures is provided. First, a substrate having an active device thereon is provided. A patterned passivation layer is formed on the substrate and the active device, and the patterned passivation layer exposes a portion of the active device. Then, a conductive layer is formed over the patterned passivation layer, and the conductive layer is electrically connected to the active device. A mask exposing a portion of the conductive layer is provided above the conductive layer. A laser is used to irradiate the conductive layer via the mask to remove the portion of the conductive layer exposed by the mask. As a result, the remained portion of the conductive layer constitutes a pixel electrode, and the pixel electrode is electrically connected to the active device. The method simplifies the fabrication process of a pixel structure, and thus reduces the fabrication cost. | 09-04-2008 |
20090053844 | METHOD FOR FABRICATING PIXEL STRUCTURE - A method for fabricating a pixel structure is provided. A substrate having a gate thereon is provided. Next, a gate dielectric layer is formed to cover the gate. A channel layer is formed on the gate dielectric layer above the gate. A source and a drain are formed on the channel layer at two sides of the gate, wherein the gate, the channel layer, the source and the drain constitute a thin film transistor (TFT). A passivation layer is formed on the gate dielectric layer and the TFT. A first shadow mask exposing parts of the passivation layer is provided thereabove. The drain is exposed by a laser applied via the first shadow mask to partially remove the passivation layer. A conductive layer is formed to cover the passivation layer and the drain. The conductive layer is then automatically patterned by the patterned passivation layer to form a pixel electrode. | 02-26-2009 |
20090053861 | METHOD FOR FABRICATING PIXEL STRUCTURE - A method for fabricating a pixel structure is provided. A substrate is provided, and a gate is formed on the substrate. A gate dielectric layer covering the gate is formed on the substrate. A semiconductor layer is formed on the gate dielectric layer. A first shadow mask exposing parts of the semiconductor layer is provided above the semiconductor layer. A laser is irradiated on the semiconductor layer through the first shadow mask to remove parts of semiconductor layer and form a channel layer. A source and a drain are respectively formed on the channel layer at both sides of the gate. A patterned passivation layer which covers the channel layer and exposes the drain is formed. A conductive layer is formed to cover the patterned passivation layer and the drain. The conductive layer is automatically patterned by the patterned passivation layer to form a pixel electrode. | 02-26-2009 |
20090068777 | METHOD FOR MANUFACTURING PIXEL STRUCTURE - A method for manufacturing a pixel structure is provided. First, a substrate with a gate formed thereon is provided. Next, a gate dielectric layer covering the gate is formed on the substrate. Then, a channel layer, a source and a drain are formed on the gate dielectric layer over the gate. The source and the drain are disposed on a portion of the channel layer. The gate, the channel layer, the source and the drain constitute a thin film transistor. Then, a passivation layer is formed on the gate dielectric layer and the thin film transistor. After that, a laser beam is utilized to irradiate the passivation layer via a first shadow mask so as to remove a portion of the passivation layer for exposing the drain. Then, a pixel electrode is formed on the gate dielectric layer and connected to the exposed drain. | 03-12-2009 |
20090087954 | METHOD FOR FABRICATING PIXEL STRUCTURE - A method for fabricating a pixel structure using a laser ablation process is provided. This fabrication method forms a gate, a channel layer, a source, a drain, a passivation layer, and a pixel electrode sequentially by using a laser ablation process. Particularly, the fabrication method is not similar to a photolithography and etching process, so as to reduce the complicated photolithography and etching processes, such as spin coating process, soft-bake, hard-bake, exposure, developing, etching, and stripping. Therefore, the fabrication method simplifies the process and thus reduces the fabrication cost. | 04-02-2009 |
20090148972 | METHOD FOR FABRICATING PIXEL STRUCTURE - A method for fabricating a pixel structure includes following steps. First, a substrate is provided. Next, a first conductive layer is formed on the substrate. Next, a first shadow mask is disposed over the first conductive layer. Next, a laser is applied through the first shadow mask to irradiate the first conductive layer to form a gate. Next, a gate dielectric layer is formed on the substrate to cover the gate. After that, a channel layer, a source and a drain are simultaneously formed on the gate dielectric layer over the gate, wherein the gate, the channel layer, the source and the drain together form a thin film transistor. A patterned passivation layer is formed on the thin film transistor and the patterned passivation layer exposes a part of the drain. Furthermore, a pixel electrode electrically connecting to the drain is formed. | 06-11-2009 |
20090148987 | METHOD FOR FABRICATING PIXEL STRUCTURE - A method for fabricating a pixel structure is disclosed. A substrate is provided. A first conductive layer is formed on the substrate, and a first shadow mask exposing a portion of the first conductive layer is disposed over the first conductive layer. Laser is used to irradiate the first conductive layer for removing the part of the first conductive layer and forming a gate. A gate dielectric layer is formed on the substrate to cover the gate. A channel layer is formed on the gate dielectric layer over the gate. A source and a drain are formed on the channel layer and respectively above both sides of the gate. A patterned passivation layer is formed to cover the channel layer and expose the drain. An electrode material layer is formed to cover the patterned passivation layer and the exposed drain. | 06-11-2009 |
20090173943 | ACTIVE MATRIX ARRAY STRUCTURE AND MANUFACTURING MEHTOD THEREOF - An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer. | 07-09-2009 |
20090256164 | Active Device Array Substrate and Method for Fabricating the Same - An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating layer, a patterned semiconductor layer and a patterned metal multilayer. Furthermore, the subject invention uses the means of selectively etching certain layers. Using the aforesaid means, the array substrate of the subject invention has some layers with under-cut structures, and thus, the number of the time-consuming and complicated mask etching process involved in the production of an array substrate can be reduced. The subject invention provides a relatively simple and time-saving method for producing an array substrate. | 10-15-2009 |
20090262269 | PIXEL STRUCTURE AND ACTIVE DEVICE ARRAY SUBSTRATE - A pixel structure is disposed on a substrate and electrically connected to a scan line and a data line. The pixel structure including an active device, a bottom capacitor electrode, an insulator, and a pixel electrode is provided. The active device is disposed on the substrate and has a gate, a source and a drain. Besides, the active device is electrically connected to the scan line and the data line. The bottom capacitor electrode and the gate are separately disposed on the substrate. The insulator covering the active device and the bottom capacitor electrode is made of a mono film. The pixel electrode is electrically connected to the active device, and at least a part of the pixel electrode extends to the insulator above the bottom capacitor electrode. | 10-22-2009 |
20100084660 | Semiconductor Structures - A semiconductor structure is provided. The semiconductor structure includes a substrate, a gate disposed thereon, an insulation layer disposed on the substrate and overlying the gate, a patterned semiconductor layer disposed on the insulation layer, a source and a drain disposed on the patterned semiconductor layer, a protective layer overlying the insulation layer, the source and the boundary of the drain to expose a portion of the drain, and a pixel electrode disposed on the substrate, overlying the protective layer overlying the boundary of the drain, electrically connected to the exposed drain. | 04-08-2010 |
20100213464 | ACTIVE MATRIX ARRAY STRUCTURE - An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer. | 08-26-2010 |
20100279450 | Active Device Array Substrate and Method for Fabricating the Same - An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating layer, a patterned semiconductor layer and a patterned metal multilayer. Furthermore, the subject invention uses the means of selectively etching certain layers. Using the aforesaid means, the array substrate of the subject invention has some layers with under-cut structures, and thus, the number of the time-consuming and complicated mask etching process involved in the production of an array substrate can be reduced. The subject invention provides a relatively simple and time-saving method for producing an array substrate. | 11-04-2010 |
20120222729 | PHOTOVOLTAIC DEVICE WITH DOUBLE-JUNCTION - The present invention, a photovoltaic device includes a substrate having a first doped-type, a first doped region having a second doped-type in the substrate, a second doped region in a portion of the first doped region and exposing the other portion of the first doped region, and a third doped region in the exposed portion of the first doped region. The polarity of the second doped-type is substantially reversed with that of the first doped-type. The second doped region has a polarity substantially identical to that of the first doped-type and a doped concentration substantially greater than that of the substrate. The third doped region has a polarity substantially identical to that of the second doped-type and a doped concentration substantially greater than that of the first doped region. The first doped-type is one of N-type and P-type, while the second doped-type is the other of P-type and N-type. | 09-06-2012 |
20140166091 | PHOTOVOLTAIC DEVICE WITH DOUBLE-JUNCTION - A photovoltaic device includes a substrate having a first doped-type, a first doped region having a second doped-type in the substrate, a second doped region in a portion of the first doped region and exposing the other portion of the first doped region, and a third doped region in the exposed portion of the first doped region. The polarity of the second doped-type is substantially reversed with that of the first doped-type. The second doped region has a polarity substantially identical to that of the first doped-type and a doped concentration substantially greater than that of the substrate. The third doped region has a polarity substantially identical to that of the second doped-type and a doped concentration substantially greater than that of the first doped region. The first doped-type is one of N-type and P-type, while the second doped-type is the other of P-type and N-type. | 06-19-2014 |