Patent application number | Description | Published |
20130293249 | Methods for Modeling Tunable Radio-Frequency Elements - A test system for characterizing an antenna tuning element is provided. The test system may include a test host, a radio-frequency tester, and a test fixture. The test system may calibrate the radio-frequency tester using known coaxial standards. The test system may then calibrate transmission line effects associated with the test fixture using a THRU-REFLECT-LINE calibration algorithm. The antenna tuning element may be mounted on a test socket that is part of the test fixture. While the antenna tuning element is mounted on the test socket, scattering parameter measurements may be obtained using the radio-frequency tester. An equivalent circuit model for the test socket can be obtained based on the measured scattering parameters and known characteristics of the antenna tuning element. Once the test socket has been characterized, an equivalent circuit model for the antenna tuning element can be obtained by extracting suitable modeling parameters from the measured scattering parameters. | 11-07-2013 |
20130321012 | Methods and Apparatus for Testing Small Form Factor Antenna Tuning Elements - A test system for testing a device under test (DUT) is provided. The test system may include a DUT receiving structure configured to receive the DUT during testing and a DUT retention structure that is configured to press the DUT against the DUT receiving structure so that DUT cannot inadvertently shift around during testing. The DUT retention structure may include a pressure sensor operable to detect an amount of pressure that is applied to the DUT. The DUT retention structure may be raised and lowered vertically using a manually-controlled or a computer-controlled positioner. The positioner may be adjusted using a coarse tuning knob and a fine tuning knob. The positioner may be calibrated such that the DUT retention structure applies a sufficient amount of pressure on the DUT during production testing. | 12-05-2013 |
20130328582 | Methods and Apparatus for Performing Wafer-Level Testing on Antenna Tuning Elements - A test system for testing an antenna tuning element is provided. The test system may include a tester, a test fixture, and a probing structure. The probing structure may include probe tips configured to mate with corresponding solder bumps formed on a device under test (DUT) containing an antenna tuning element. The DUT may be tested in a shunt or series configuration. The tester may be electrically coupled to the test probe via first and second connectors on the test fixture. An adjustable load circuit that is coupled to the second connector may be configured in a selected state so that a desired amount of electrical stress may be presented to the DUT during testing. The tester may be used to obtain measurement results on the DUT. Systematic effects associated with the test structures may be de-embedded from the measured results to obtain calibrated results. | 12-12-2013 |
20140087668 | Methods and Apparatus for Performing Coexistence Testing for Multi-Antenna Electronic Devices - Radio frequency test systems for characterizing antenna performance in various radio coexistence scenarios are provided. In one suitable arrangement, a test system may be used to perform passive radio coexistence characterization. During passive radio coexistence characterization, at least one signal generator may be used to feed aggressor signals directly to antennas within an electronic device under test (DUT). The aggressor signals may generate undesired interference signals in a victim frequency band, which can then be received and analyzed using a spectrum analyzer. During active radio coexistence characterization, at least one radio communications emulator may be used to communicate with a DUT via a first test antenna. While the DUT is communicating with the at least one radio communications emulator, test signals may also be conveyed between DUT | 03-27-2014 |
20140167794 | Methods for Validating Radio-Frequency Test Stations - A manufacturing system for assembling wireless electronic devices is provided. The manufacturing system may include test stations for testing the radio-frequency performance of components that are to be assembled within the electronic devices. A reference test station may be calibrated using calibration coupons having known radio-frequency characteristics. The calibration coupons may include transmission line structures. The reference test station may measure verification standards to establish baseline measurement data. The verification standards may include circuitry having electrical components with given impedance values. Many verification coupons may be measured to enable testing for a wide range of impedance values. Test stations in the manufacturing system may subsequently measure the verification standards to generate test measurement data. The test measurement data may be compared to the baseline measurement data to characterize the performance of the test stations to ensure consistent test measurements across the test stations. | 06-19-2014 |
20140266941 | Electronic Device With Hybrid Inverted-F Slot Antenna - An electronic device may be provided with a housing. The housing may have a periphery that is surrounded by peripheral conductive structures such as a segmented peripheral metal member. A segment of the peripheral metal member may be separated from a ground by a slot. An antenna feed may have a positive antenna terminal coupled to the peripheral metal member and a ground terminal coupled to the ground and may feed both an inverted-F antenna structure that is formed from the peripheral metal member and the ground and a slot antenna structure that is formed from the slot. Control circuitry may tune the antenna by controlling adjustable components that are coupled to the peripheral metal member. The adjustable components may include adjustable inductors and adjustable capacitors. | 09-18-2014 |
20140302797 | Methods and Apparatus for Testing Electronic Devices Under Specified Radio-frequency Voltage and Current Stress - Test systems for characterizing devices under test (DUTs) are provided. A test system for testing a DUT in a shunt configuration may include a signal generator and a matching network that is coupled between the signal generator and the DUT and that is optimized to apply desired voltage/current stress to the DUT with reduced source power. The matching network may be configured to provide matching and desired stress levels at two or more frequency bands. In another suitable embodiment, a test system for testing a DUT in a series configuration may include a signal generator, an input matching network coupled between the DUT and a first terminal of the DUT, and an output matching network coupled between the DUT and a second terminal of the DUT. The input and output matching network may be optimized to apply desired voltage/current stress to the DUT with reduced source power. | 10-09-2014 |
20140329558 | Electronic Device With Multiple Antenna Feeds and Adjustable Filter and Matching Circuitry - Electronic devices may include antenna structures. The antenna structures may form an antenna having first and second feeds at different locations. A first transceiver may be coupled to the first feed using a first circuit. A second transceiver may be coupled to the second feed using a second circuit. The first and second feeds may be isolated from each other using the first and second circuits. The second circuit may have a notch filter that isolates the second feed from the first feed at operating frequencies associated with the first transceiver. The first circuit may include an adjustable component such as an adjustable capacitor. The adjustable component may be placed in different states depending on the mode of operation of the second transceiver to ensure that the first feed is isolated from the second feed. | 11-06-2014 |
20140333495 | Electronic Device Antenna With Multiple Feeds for Covering Three Communications Bands - Electronic devices may be provided that include radio-frequency transceiver circuitry and antennas. An antenna may be formed from an antenna resonating element and an antenna ground. The antenna resonating element may have a shorter portion that resonates at higher communications band frequencies and a longer portion that resonates at lower communications band frequencies. An extended portion of the antenna ground may form an inverted-F antenna resonating element portion of the antenna resonating element. The antenna resonating element may be formed from a peripheral conductive electronic device housing structure that is separated from the antenna ground by an opening. A first antenna feed may be coupled between the peripheral conductive electronic device housing structures and the antenna ground across the opening. A second antenna feed may be coupled to the inverted-F antenna resonating element portion of the antenna resonating element. | 11-13-2014 |
20140333496 | Antenna With Tunable High Band Parasitic Element - Electronic devices may be provided that include radio-frequency transceiver circuitry and antennas. An antenna may be formed from an antenna resonating element and an antenna ground. The antenna resonating element may have a shorter portion that resonates at higher communications band frequencies and a longer portion that resonates at lower communications band frequencies. The resonating element may be formed from a peripheral conductive electronic device housing structure that is separated from the antenna ground by an opening. A parasitic monopole antenna resonating element or parasitic loop antenna resonating element may be located in the opening. Antenna tuning in the higher communications band may be implemented using an adjustable inductor in the parasitic element. Antenna tuning in the lower communications band may be implemented using an adjustable inductor that couples the antenna resonating element to the antenna ground. | 11-13-2014 |
20150341073 | Electronic Device Having Sensors and Antenna Monitor For Controlling Wireless Operation - An electronic device may be provided with wireless circuitry. Control circuitry may be used to adjust the wireless circuitry. The wireless circuitry may include an antenna that is tuned using tunable components. The control circuitry may gather information on the current operating mode of the. electronic device, sensor data from a proximity sensor, accelerometer, microphone, and other sensors, antenna impedance information for the antenna, and information on the use of connectors in the electronic device. Based on this gathered data, the control circuitry can adjust the tunable components to compensate for antenna detuning due to loading from nearby external objects, may adjust transmit power levels, and may make other wireless circuit adjustments. | 11-26-2015 |
20150372656 | Electronic Device With Adjustable Wireless Circuitry - An electronic device may be provided with wireless circuitry. Control circuitry may be used to adjust the wireless circuitry. The wireless circuitry may include antennas that are tuned, adjustable impedance matching circuitry, antenna port selection circuitry, and adjustable transceiver circuitry. Wireless circuit adjustments may be made by ascertaining a current usage scenario for the electronic device based on sensor data, information from cellular base station equipment or other external equipment, signal-to-noise ratio information or other signal information, antenna impedance measurements, and other information about the operation of the electronic device. | 12-24-2015 |
20160064801 | Electronic Device Antenna With Reduced Lossy Mode - An electronic device may be provided with an antenna. The antenna may have an antenna resonating element and an antenna ground. An adjustable inductor may be coupled between the antenna resonating element and the antenna ground. An antenna feed may have a positive feed terminal coupled to the antenna resonating element and a ground antenna feed coupled to the antenna ground. The adjustable inductor may have first and second inductors coupled to respective first and second ports of a switch. The switch may have a third port coupled to the antenna ground. A capacitor may have a first terminal coupled to ground and a second terminal coupled to the first inductor at the first port of the switch. An inductor may be coupled between the antenna resonating element and antenna ground at a location between the adjustable inductor and the antenna feed. | 03-03-2016 |
20160064812 | Electronic Device Antenna With Interference Mitigation Circuitry - An electronic device may be provided with an antenna. The antenna may have an antenna resonating element and an antenna ground. The antenna resonating element may be formed from peripheral conductive housing structures. An audio jack or other connector may be mounted in an opening in the peripheral conductive housing structures. The audio jack may overlap the antenna ground. Contacts in the audio jack may be coupled to an interference mitigation circuit. The interference mitigation circuit may include capacitors coupled to the ground and inductors coupled between the contacts and the capacitors. Radio-frequency signal blocking inductors may be coupled between the interference mitigation circuit and respective ports in an audio circuit. | 03-03-2016 |
20160097833 | Wireless Electronic Device With Calibrated Reflectometer - An electronic device may have control circuitry that uses a reflectometer to measure antenna impedance during operation. The reflectometer may have a directional coupler that is coupled between radio-frequency transceiver circuitry and an antenna. A calibration circuit may be coupled between the directional coupler and the antenna. The calibration circuit may have a first port coupled to the antenna, a second port coupled to the directional coupler, and a third port that is coupled to a calibration resistance. The reflectometer may have terminations of identical impedance that are coupled to ground. Switching circuitry in the reflectometer may be used to route signals from the directional coupler to a feedback receiver for measurement by the control circuitry or to ground through the terminations. Calibrated antenna reflection coefficient measurements may be used in dynamically adjusting the antenna. | 04-07-2016 |
Patent application number | Description | Published |
20120307792 | WI-FI VIRTUAL PORT UPLINK MEDIUM ACCESS CONTROL - Uplink medium access control on per-wireless device level. An access point sends a beacon frame to a wireless device. The beacon frame includes a BSSID that is unique to the wireless device. The beacon frame also includes embedded uplink configurations specifying uplink medium access for the wireless device. In one embodiment, a controller recognizes a device or user associated with the device, and sends corresponding uplink configurations for embedding in a subsequent beacon frame. | 12-06-2012 |
20130148609 | HYBRID VIRTUAL CELL AND VIRTUAL PORT WIRELESS NETWORK ARCHITECTURE - A controller directing access points to default to a virtual cell service mode which allows seamless mobility for stations in motion around a wireless network is disclosed. Responsive to identifying a first station, the controller logic may dictate tighter controls for the first station by selecting a virtual port service mode. Some embodiments can also select a native cell service mode for devices due to a connection history of the station or a MAC OUI that is incompatible with virtual cell service mode. An initial service mode can be changed due to a condition. Also, the controller provides multiple BSSIDs to each access point. | 06-13-2013 |
20130308600 | SEAMLESS MOBILITY IN WIRELESS NETWORKS - AP's associated with a communication network and any wireless devices desiring contact, operated according to a protocol in which each wireless device selects AP's with which to communicate. A system coordinator causes the AP's to operate so as to guide each wireless device to an AP selected by the system coordinator. This has the effect that, notwithstanding that the protocol involves having the wireless device make the selection of AP, functionally, the AP's make the selection for it. In a 1st technique, multiple AP's share an identifier, with the system coordinator directing one particular AP to respond to the wireless device, thus appearing to wireless devices as a “personal cell”. In a 2nd technique, AP's each maintain identifiers substantially unique to each wireless device, with the system coordinator directing only one particular AP to maintain any particular wireless device's identifier, thus appearing to wireless devices as a “personal AP”. | 11-21-2013 |
20140112322 | INCREASING ACCESS POINT THROUGHPUT BY EXCEEDING A-MPDU BUFFER SIZE LIMITATION IN A 802.11 COMPLIANT STATION - An 802.11-compliant device for high throughput is disclosed. A plurality of TCP packets received in a buffer for transmission are stored. The plurality of TCP packets can be aggregated as A-MSDU sub-frames to form a A-MSDU frame in accordance with an IEEE 802.11 standard. Additionally, a plurality of A-MSDU frames can be aggregated as A-MPDU sub-frames to form a A-MPDU frame. The A-MPDU frame is compliant with a number of allowable sub-frames and a maximum size in accordance with an 802.11 standard. The A-MPDU frame is sent for transmission as an IEEE 802.11 packet. | 04-24-2014 |
20140204802 | DISTRIBUTED CLIENT STEERING ALGORITHM TO A BEST-SERVING ACCESS POINT - Network devices are steered to preferred access points using a probability function. A probe request for connection is received from a network device. The probe request can be from a network device attempting to use a wireless network (e.g., a IEEE 802.11-type network or other suitable type of network). A probability function that defines a likelihood of granting the network device a connection is used to determine whether to accept or deny the response. The probe response is then sent to the network device. | 07-24-2014 |
20140233734 | RESTRICTING BROADCAST AND MULTICAST TRAFFIC IN A WIRELESS NETWORK TO A VLAN - Traffic broadcast to a VLAN is restricted. To do so, a plurality of stations are associated with a BSSID (basic service set identifier). A first VLAN is configured by sending a first group key to each station from the plurality of stations that is a member of the first VLAN, wherein each VLAN is associated with a unique group key. One or more frames addressed to the first VLAN are received. The one or more frames are encrypted with the first group key to prevent stations without the first group key from being able to decrypt the one or more frames. The one or more encrypted VLAN frames are broadcast to the plurality of stations associated with the BSSID. | 08-21-2014 |
20140301363 | ACCESS POINT FOR SURVEILLANCE OF ANOMALOUS DEVICES - An access point switches between an access point mode and a surveillance mode. In the access point mode, the access point provides network access for end stations using a BSSID (Basic Service Set Identifier) while in the access point mode. In surveillance mode, the access point scans one or more channels of the wireless network to identify one or more anomalous devices. | 10-09-2014 |
20150043530 | SEAMLESS MOBILITY IN WIRELESS NETWORKS - For seamless mobility, at least one communication parameter to associate with a BSSID is selected. A beacon is sent from a first access point to advertise its presence, wherein the beacon comprises the BSSID associated with the at least one communication parameter. Responsive to the mobile station choosing the BSSID being advertised in the beacon sent from the first access point, a uniquely assign the BSSID is selected for a mobile station. The first access point from the plurality of access points is associated with the mobile station persistently. Associating is made as selected by the system coordinator, the uniquely assigned BSSID being independent of an identify of mobile station and being eligible for subsequent assignment to a different mobile station as determined by the system coordinator. | 02-12-2015 |
20150124774 | AGGREGATED BEACONS FOR PER STATION CONTROL OF MULTIPLE STATIONS ACROSS MULTIPLE ACCESS POINTS IN A WIRELESS COMMUNICATION NETWORK - A technique for providing per station control of multiple stations in a wireless network across multiple access points. A look-up table that assigns a station connected to the access point and at least one communication parameter to each of a plurality of persistent, uniquely-assigned BSSIDs (Basic Service Set Identifiers) is stored. An access point responds to messages addressed one of the plurality of persistent, uniquely-assigned BSSIDs and ignores messages addressed to other BSSIDs. Persistence of the BSSID allows the controller to maintain individual control over each station after moving to a second access point of the plurality of access points. A frame comprising the plurality of BSSIDs corresponding to each connected station aggregated into the frame is generated. The frame is transmitted to the plurality of stations. Responsive to a station of the plurality of stations being handed-off to a different access point, a uniquely-assigned BSSID corresponding to the station is deleted from the look-up table. | 05-07-2015 |
20160057694 | STEERING CONNECTION REQUESTS FOR AN ACCESS POINT TO A BEST-SERVING ACCESS POINT - Network devices are steered to preferred access points using a probability function. A probe request for connection is received from a network device. The probe request can be from a network device attempting to use a wireless network (e.g., a IEEE 802.11-type network or other suitable type of network). A probability function that defines a likelihood of granting the network device a connection is used to determine whether to accept or deny the response. The probe response is then sent to the network device. | 02-25-2016 |
20160088523 | PER USER UPLINK MEDIUM ACCESS CONTROL ON A WI-FI COMMUNICATION NETWORK - Uplink medium access control on per-wireless device level for a specific user. An access point sends a beacon frame to a wireless device. The beacon frame includes a BSSID that is unique to the wireless device. The beacon frame also includes embedded uplink configurations specifying uplink medium access for the wireless device. In one embodiment, a controller recognizes a device or user associated with the device, and sends corresponding uplink configurations for embedding in a subsequent beacon frame. | 03-24-2016 |
Patent application number | Description | Published |
20120300332 | Systems and Methods for Data Addressing in a Storage Device - Various embodiments of the present invention provide systems and methods for format efficient data storage. As an example, a data storage device is described that includes: a storage medium, a read/write head assembly, and a read channel circuit. The read/write head assembly is disposed in relation to the storage medium and operable to sense information corresponding to an encoded codeword. The read channel circuit is operable to receive the encoded codeword. The read channel circuit includes a missing symbols insertion circuit, a codeword de-scramble circuit, an address insertion circuit, and a data decoder circuit. The missing symbols insertion circuit, the codeword de-scramble circuit, and the address insertion circuit together are operable to pad a derivative of the encoded codeword with a plurality of symbols, to de-scramble the derivative of the encoded codeword, and to insert address information corresponding to the derivative of the encoded codeword to yield a modified encoded codeword. The data decoder circuit is operable to apply a data decoding algorithm to the modified encoded codeword to yield a decoded output. | 11-29-2012 |
20120330584 | Systems and Methods for Power Monitoring in a Variable Data Processing System - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a data detector circuit, a data decoder circuit, and a power monitor circuit. The data detector circuit is operable to apply a data detection algorithm to a data input and a decoded output to yield a detected output. The data decoder circuit is operable to apply a data decoding algorithm to the detected output to yield the decoded output. The power monitor circuit is operable to receive a first power status signal from the data detector circuit and a second power status from the data decoder circuit, and to calculate a power usage of a combination of at least the data detector circuit and the data decoder circuit. In such a system, a number of global iterations through a combination of the data decoder circuit and the data detector circuit is variable and both of the first power status signal and the second power status signal varies at least in part as a function of the number of global iterations. | 12-27-2012 |
20120331363 | Systems and Methods for Reduced Format Non-Binary Decoding - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detecting circuit having: a first vector translation circuit, a second vector translation circuit, and a data detector core circuit. The data detecting circuit is operable to receive an input data set and at least one input vector in a first format. The at least one input vector corresponds to a portion of the input data set. The first vector translation circuit is operable to translate the at least one vector to a second format. The data detector core circuit is operable to apply a data detection algorithm to the input data set and the at least one vector in the second format to yield a detected output. The second vector translation circuit operable to translate a derivative of the detected output to the first format to yield an output vector. | 12-27-2012 |
20120331370 | Systems and Methods for Non-Binary Decoding - Various embodiments of the present invention provide systems and methods for data processing. A data processing circuit is disclosed that includes: a data detector circuit, a first symbol constrained arrangement circuit, and a second symbol constrained arrangement circuit. The data detector circuit is operable to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output that includes a number of non-binary symbols. The first symbol constrained arrangement circuit is operable to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output. The bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output. The second symbol constrained arrangement circuit is operable to receive a second input data set and to re-arrange the second data input in accordance with a second arrangement algorithm to yield the decoded data set. The bits for at least one non-binary symbol from the second input data set are maintained together in the decoded data set output. | 12-27-2012 |
20130007551 | Stochastic Stream Decoding of Binary LDPC Codes - Various embodiments of the present invention provide systems and methods for stochastic stream decoding of binary LDPC codes. For example, a data decoder circuit is discussed that includes a number of variable nodes and check nodes, with serial connections between the variable nodes and the check nodes. The variable nodes are each operable to perform a real-valued computation of a variable node to check node message for each neighboring check node. The check nodes are operable to perform a real-valued computation of a check node to variable node message for each neighboring variable node. The messages are passed iteratively between the variable nodes and the check nodes. | 01-03-2013 |
20130063835 | Systems and Methods for Generating Predictable Degradation Bias - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit and a bias calculation circuit. The data detector circuit is operable to apply a data detection algorithm to a first data set to yield a first series of soft decision data, and to apply the data detection algorithm to a second data set to yield a second series of soft decision data. The bias calculation circuit operable to calculate a series of bias values based at least in part on the first series of soft decision data and the second series of soft decision data. The series of bias values correspond to a conversion between the first series of soft decision data and the second series of soft decision data. | 03-14-2013 |
20130067247 | Systems and Methods for Governing Power Usage in an Iterative Decoding System - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit, a data decoder circuit, and a gating circuit. | 03-14-2013 |
20130067297 | Systems and Methods for Non-Binary Decoding Biasing Control - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit, a biasing circuit, and a data decoder circuit. The data detector circuit is operable to apply a data detection algorithm to a series of symbols to yield a detected output, and the detected output includes a series of soft decision data corresponding to non-binary symbols. The biasing circuit is operable apply a bias to each of the series of soft decision data to yield a series of biased soft decision data. The data decoder circuit is operable to apply a data decoding algorithm to the series of biased soft decision data corresponding to the non-binary symbols. | 03-14-2013 |
20130080844 | Systems and Methods for Efficient Data Shuffling in a Data Processing System - Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes: receiving a data input having at least a first local chunk and a second local chunk, the data input also being defined as having at least a first global chunk and a second global chunk; rearranging an order of the first local chunk and the second local chunk to yield a locally interleaved data set; storing the locally interleaved data set to a first memory, such that the first global chunk is stored to a first memory space, and the second global chunk is stored to a second memory space; accessing the locally interleaved data set from the first memory; and storing the locally interleaved data set to a second memory. The first global chunk is stored to a third memory space defined at least in part based on the first memory space, and the second global chunk is stored to a fourth memory space defined at least in part based on the second memory space. | 03-28-2013 |
20130111289 | SYSTEMS AND METHODS FOR DUAL PROCESS DATA DECODING | 05-02-2013 |
20130111290 | Systems and Methods for Ambiguity Based Decode Algorithm Modification | 05-02-2013 |
20130139022 | Variable Sector Size LDPC Decoder - Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for decoding variably sized blocks of data in an LDPC decoder. For example, in one embodiment an apparatus includes a low density parity check decoder operable to perform decoding of a plurality of circulant sub-matrices from an H matrix, and a controller connected to the low density parity check decoder, operable to omit any of the plurality of circulant sub-matrices from the decoding if they do not contain user data. | 05-30-2013 |
20130139023 | Variable Sector Size Interleaver - Various embodiments of the present invention are related to methods and apparatuses for interleaving data, and more particularly to methods and apparatuses for interleaving variably sized blocks of data. For example, in one embodiment an apparatus includes a data partitioner operable to partition the block of data into a real data portion and a missing bits portion. The real data portion is adapted to contain data bits from the variably sized block of data and the missing bits portion is adapted to be filled with a variable number of the data bits. The apparatus also includes at least one local interleaver operable to apply a permutation across each of a plurality of sub-portions of the real data portion and the missing bits portion, and a global interleaver operable to apply a global permutation across the real data portion. | 05-30-2013 |
20130148232 | Systems and Methods for Combined Binary and Non-Binary Data Processing - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a combination data decoder circuit. The combination data decoder circuit includes: a non-binary data decoder circuit and a binary data decoder circuit. | 06-13-2013 |
20130151923 | Systems and Methods for Scalable Data Processing Shut Down - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. | 06-13-2013 |
20130159634 | Systems and Methods for Handling Out of Order Reporting in a Storage Device - Various embodiments of the present invention provide systems and methods for handling out of order reporting in a storage device. | 06-20-2013 |
20130173932 | Systems and Methods for Decimation Based Over-Current Control - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. In some such systems and methods, the operation of one or more calibration circuits is modified when it is determined that too many data processing circuits are active. | 07-04-2013 |
20130205146 | Systems and Methods for Power Governance in a Data Processing Circuit - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. | 08-08-2013 |
20130219233 | Systems and Methods for Quality Based Priority Data Processing - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. | 08-22-2013 |
20130232155 | Systems and Methods for Out of Order Data Reporting - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for out of order reporting of results from data processing. | 09-05-2013 |
20130232360 | Data Processing System with Thermal Control - Various embodiments of the present invention provide systems and methods for a data processing system with thermal control. For example, a data processing system with thermal control is disclosed that includes a number of data processors and a scheduler, which is operable to determine the power consumption of the data processors and to switch the data processing system from a first mode to a second mode and from the second mode to a third mode. The data processing system consumes less power in the third mode than in the first mode. The second mode prepares the data processing system to enter the third mode. | 09-05-2013 |
20130232390 | Systems and Methods for Multi-Matrix Data Processing - The present inventions are related to systems and methods for data processing. As one example, a data processing system is discussed that includes a data decoder circuit and a matrix select control circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input using a selected parity check matrix to yield a decoder output. The matrix select control circuit operable to select one of a first parity check matrix and a second parity check matrix as the selected parity check matrix. | 09-05-2013 |
20130246877 | Systems and Methods for Compression Driven Variable Rate Decoding in a Data Processing System - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate encoding and/or decoding in a data processing system. | 09-19-2013 |
20130246888 | Systems and Methods for Out of Order Processing in a Data Retry - Various embodiments of the present invention provide systems and methods for data processing that includes selectively reporting results out of order or in order. | 09-19-2013 |
20130254619 | Systems and Methods for Mis-Correction Correction in a Data Processing System - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for mis-correction detection and correction in a data processing system. | 09-26-2013 |
20130263147 | Systems and Methods for Speculative Read Based Data Processing Priority - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. | 10-03-2013 |
20130283114 | Systems and Methods for Locating and Correcting Decoder Mis-Corrections - Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding circuit having a data decoder circuit, an element modification circuit, an element modification log, and a mis-correction detection circuit. | 10-24-2013 |
20130290806 | Systems and Methods for Data Decoder State Preservation During Extended Delay Processing - The present invention is related to systems and methods for maintaining additional processing information during extended delay processing. | 10-31-2013 |
20130322578 | Systems and Methods for Data Processing Including EET Feedback - The present invention is related to systems and methods for data processing system characterization. | 12-05-2013 |
20130326302 | Error Injection for LDPC Retry Validation - The present inventions are related to systems and methods for validating retry features in LDPC decoders and in systems incorporating LDPC decoders. For example, a data processing circuit is disclosed that includes a low density parity check decoder and is operable to correct errors in a data set. The data processing circuit includes at least one retry feature operable to assist in correcting the errors that are not corrected without the at least one retry feature. A retry validation circuit in the data processing circuit is operable to inject errors in the data set to trigger the at least one retry feature. | 12-05-2013 |
20130335850 | Initialization for Decoder-Based Filter Calibration - Various embodiments of the present inventions are related to initialization of decoder-based filter calibration, and in particular to initially using either a detector output or unconverged data from the decoder to train filter coefficients in a noise predictive calibration engine until data sectors converge in the decoder and can be used to train filter coefficients. | 12-19-2013 |
20130339827 | Adaptive Calibration of Noise Predictive Finite Impulse Response Filter - Various embodiments of the present inventions are related to adaptive calibration of NPFIR filters in a data detector. For example, an apparatus for calibrating a noise predictive filter is disclosed, including a data detector operable to generate detected values for data sectors and having an embedded noise predictive finite impulse response filter. The apparatus also includes a comparator operable to determine whether a quality metric for a current one of the data sectors meets a noise threshold. The apparatus also includes a filter calibration circuit operable to adapt a number of filter coefficients for the noise predictive finite impulse response filter based on the detected values for the data sectors, and to omit the detected values for the current one of the data sectors from adaptation for one of the filter coefficients if the quality metric for the current one of the data sectors does not meet the noise threshold. | 12-19-2013 |
20130343495 | APPARATUS AND METHOD FOR BREAKING TRAPPING SETS - An error correction data processing apparatus includes a noise predictive calibration circuit operable to calibrate a first set of filter coefficients based on a first data set and a second set of filter coefficients based on a second data set, and includes a first noise predictive detector operable to receive the first set of filter coefficients. The apparatus further includes a decoder operable to perform a first global iteration with the first noise predictive detector and determine a violation check count value, and a second noise predictive detector operable to receive the second set of filter coefficients if the violation check count value is less than a predetermined value or receive the first set of filter coefficients if the violation check count value is greater than the predetermined value. | 12-26-2013 |
20140025904 | Systems and Methods for Gate Aware Iterative Data Processing - The present invention is related to systems and methods for iterative data processing scheduling. | 01-23-2014 |
20140053038 | Method for Selecting a LDPC Candidate Code - A method for estimating error probability of LDPC codes includes ordering LDPC codes according to features in each code with known error characteristics. The method includes identifying features in each LDPC code having known error characteristics; adding each code to one or more categories based on the existence of such features; and ranking the LDPC codes according to the level of error risk. | 02-20-2014 |
20140059377 | DYNAMIC Y-BUFFER SIZE ADJUSTMENT FOR RETAINED SECTOR REPROCESSING - Aspects of the disclosure pertain to a system and method for providing dynamic y-buffer size adjustment for retained sector reprocessing (RSR). The system and method implement dynamic y-buffer size adjustment for RSR for promoting improved Sector Failure Rate (SFR) performance of the system. The system is a read channel system. | 02-27-2014 |
20140068372 | Systems and Methods for Local Iteration Randomization in a Data Decoder - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for local iteration randomization in a data decoder circuit. | 03-06-2014 |
20140068394 | SYSTEMS AND METHODS FOR SECTOR QUALITY DETERMINATION IN A DATA PROCESSING SYSTEM - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data set quality determination. | 03-06-2014 |
20140075264 | CORRECTING ERRORS IN MISCORRECTED CODEWORDS USING LIST DECODING - A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword. | 03-13-2014 |
20140095955 | Efficient Way to Construct LDPC Code by Comparing Error Events Using a Voting Based Method - A method for ordering trapping sets to find one or more dominant trapping sets includes analyzing a trapping set and a random set of codewords to generate a distance value for each trapping set, and ordering the trapping sets by the distance value. Distance values may be determined for each trapping set by tracking a vote count wherein a correct decode at a certain noise level produces a “right” vote and an incorrect decode at a certain noise level produces a “left” vote. A certain threshold number of “left” votes terminates processing at that noise level. | 04-03-2014 |
20140164866 | Low Density Parity Check Decoder With Miscorrection Handling - A data processing system is disclosed including a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a second portion of the composite matrix. The decoder circuit is also operable to correct the codeword on the hash when the syndrome indicates that the codeword based on the first portion of the composite matrix is correct but a second test indicates that the codeword is miscorrected. | 06-12-2014 |
20140200849 | DIVERSITY LOOP DETECTOR WITH COMPONENT DETECTOR SWITCHING - Aspects of the disclosure pertain to a system and method for providing component detector switching for a diversity loop detector. Switching between component detectors is performed via one of: a periodic state likelihood reset process, a slope-based switching process, or a cross-over connection process. The joint decision circuit switches among component detectors to promote improved performance with present of constant or transition phase offset. | 07-17-2014 |
20140223259 | Memory Architecture for Layered Low-Density Parity-Check Decoder - A LE hard decision memory comprises a global mapping element to interleave L values from a first and second circulant and store the interleaved values in a first memory element. A low-density parity-check decoder then processes the circulants from the first memory element and stores output in a second memory element. The LE hard decision memory does not include any mux-demux elements. | 08-07-2014 |
20140362463 | Timing Error Detector with Diversity Loop Detector Decision Feedback - Aspects of the disclosure pertain to an apparatus for detecting timing errors including an analog to digital converter circuit, a diversity loop detector and a timing error calculation circuit. The analog to digital converter circuit is operable to convert an input signal into a series of digital samples. The diversity loop detector is operable to apply a data detection algorithm to a plurality of signals derived from the series of digital samples at different phase offsets, to select one of the phase offsets, and to yield a detected output with the selected phase offset. The timing error calculation circuit is operable to calculate a timing error of the analog to digital converter circuit based at least in part on the selected phase offset. | 12-11-2014 |
20150143196 | Systems and Methods for FAID Follower Decoding - Systems and method relating generally to data processing, and more particularly to systems and methods for decoding information. | 05-21-2015 |
20150154114 | SYSTEM AND METHOD TO INTERLEAVE MEMORY - A memory interleaving apparatus includes first and second interleavers. The first interleaver selectively interleaves information stored in a first memory in response to a sector select signal. The second interleaver selectively interleaves information stored in a second memory in response the sector select signal. The first interleaver is coupled with the second interleaver. A memory interleaving system includes an interleaver and a storage device. The interleaver is associated with a first sector size and a second sector size. The interleaver selectively interleaves information stored in a first memory and/or a second memory in response to a sector select signal. The storage device selectively provides the first masking seed and/or a second masking seed to the interleaver in response to the sector select signal. Corresponding methods are also disclosed. | 06-04-2015 |
20150228303 | Read Channel Sampling Utilizing Two Quantization Modules for Increased Sample Bit Width - A communication channel structure and a decoding method supported by such a communication channel structure are disclosed. Such a communication channel includes a digital filter configured for filtering an input signal and two quantizer configured for quantizing the filtered signal. A first quantizer is utilized to quantize the filtered signal to produce a first quantized sample having a first precision and a second quantizer is utilized to quantize the filtered signal to produce a second quantized sample having a second precision, wherein the second precision is different from the first precision. The communication channel also includes an iterative decoder configured for utilizing the first quantized sample for a first global iteration of a decoding process and utilizing the second quantized sample for at least one subsequent global iteration of the decoding process. | 08-13-2015 |
20160091951 | Systems and Methods for Power Reduced Data Decoder Scheduling - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for scheduling in a data decoder. | 03-31-2016 |