Patent application number | Description | Published |
20110129367 | MOTORIZED VACUUM PUMP - A motorized vacuum pump apparatus, may include an electric motor operating in response to an electric signal, a pumping unit connected with a motor shaft of the electric motor, and a sound absorbing unit enclosing the pumping unit and having an inlet for sucking external air, a damping chamber and an outlet, wherein the sound absorbing unit is directly combined with the electric motor, and wherein the external air is compressed and supplied by the pumping unit to the damping chamber and discharged through the outlet such that noise is reduced by damping compressed air in the damping chamber. | 06-02-2011 |
20120285165 | ENGINE SYSTEM BASED ON TURBO CHARGER AND FUEL RATIO IMPROVING METHOD THEREOF - An engine system may include an electric or mechanical supercharger and an LP-EGR, basically with a turbocharger, an EGR valve, a channel control valve, and a bypass valve, which control the flow rate of external air and exhaust gas, may be integrally operated, and a operation section may be divided into a turbo-lag and low torque section, a mid-load section, and mid/high-load section such that the open amount of EGR valve, channel control valve, and bypass valve may be optimally controlled, such that it may be possible to improve availability for a low-speed/high-load section with turbo-lag reduced, using supercharger and considerably increase the ratio of fuel efficiency improvement in the low-speed/high-load section, using LP-EGR operating with supercharger. | 11-15-2012 |
Patent application number | Description | Published |
20140317470 | MEMORY DEVICES THAT PERFORM MASKED WRITE OPERATIONS AND METHODS OF OPERATING THE SAME - A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells. | 10-23-2014 |
20140317471 | SEMICONDUCTOR MEMORY DEVICES INCLUDING SEPARATELY DISPOSED ERROR-CORRECTING CODE (ECC) CIRCUITS - A semiconductor memory device may comprise: at least one bank, each of the at least one bank including a plurality of memory cells; an error-correcting code (ECC) calculator configured to generate syndrome data for detecting an error bit from among parallel data bits read out from the plurality of memory cells of each of the at least one bank; an ECC corrector separated from the ECC calculator, the ECC corrector configured to correct the error bit from among the parallel data bits by using the syndrome data and configured to output error-corrected parallel data bits; and/or a data serializer configured to receive the error-corrected parallel data bits and configured to convert the error-corrected parallel data bits into serial data bits. | 10-23-2014 |
20140331006 | SEMICONDUCTOR MEMORY DEVICES - A semiconductor memory device includes a memory cell array, a data inversion/mask interface and a write circuit. The data inversion/mask interface receives a data block including a plurality of unit data, each of the plurality of unit data having a first data size, and the data inversion/mask interface selectively enables each data mask signal associated with each of the plurality of unit data based on a number of first data bits in a second data size of each unit data. The second data size is smaller than a first data size of the unit data. The write circuit receives the data block and performs a masked write operation that selectively writes each of the plurality of unit data in the memory cell array in response to the data mask signal. | 11-06-2014 |
20140331101 | SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHOD OF WRITING DATA IN THE SAME - In one embodiment, the semiconductor device includes a memory array and a control architecture configured to control reading data from and writing data to the memory array. The control architecture is configured to receive data and a codeword location in the memory array, select one or more data units in the received data based on a data mask, read a codeword currently stored at the codeword location in the memory array, error correct the read codeword to generate a corrected read codeword, form a new codeword from the selected data units of the received data and data units in the corrected read codeword that do not correspond to the selected data units, and write the new codeword to the memory array. | 11-06-2014 |
Patent application number | Description | Published |
20120094453 | Semiconductor Devices And Methods Of Fabricating The Same - Semiconductor devices and methods of fabricating semiconductor devices that may include forming an insulation structure including insulation patterns that are sequentially stacked and vertically separated from each other to provide gap regions between the insulation patterns, forming a first conductive layer filling the gap regions and covering two opposite sidewalls of the insulation structure, and forming a second conductive layer covering the first conductive layer. A thickness of the second conductive layer covering an upper sidewall of the insulation structure is greater than a thickness of the second conductive layer covering a lower sidewall of the insulation structure. | 04-19-2012 |
20130228843 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device includes a memory gate pattern on a substrate, and a non-memory gate pattern on the substrate, the non-memory gate pattern being spaced apart from the memory gate pattern, wherein the non-memory gate pattern includes an ohmic layer, and the memory gate pattern is provided without an ohmic layer. | 09-05-2013 |
20130273727 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - A semiconductor device includes a substrate, a first poly-silicon pattern on the substrate, a metal pattern on the first poly-silicon pattern, and an interface layer between the first poly-silicon pattern and the metal pattern. The interface layer may include at least one selected from the group of a metal-silicon oxynitride layer, a metal-silicon oxide layer, and a metal-silicon nitride layer. | 10-17-2013 |
20140001625 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME | 01-02-2014 |
20140015030 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern. | 01-16-2014 |
20140264498 | MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A memory device includes a gate structure, a contact plug, and a spacer. The gate structure includes first and second conductive layer patterns sequentially stacked on a substrate. The contact plug passes through the second conductive layer pattern, and a sidewall of the contact plug directly contacts at least a portion of the second conductive layer pattern. The spacer surrounds a portion of the sidewall of the contact plug and contacting the gate structure. | 09-18-2014 |
20140332874 | SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate, a first poly-silicon pattern on the substrate, a metal pattern on the first poly-silicon pattern, and an interface layer between the first poly-silicon pattern and the metal pattern. The interface layer may include at least one selected from the group of a metal-silicon oxynitride layer, a metal-silicon oxide layer, and a metal-silicon nitride layer. | 11-13-2014 |
20150084109 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern. | 03-26-2015 |
Patent application number | Description | Published |
20100201865 | IMAGING METHOD FOR USE WITH VARIABLE CODED APERTURE DEVICE AND IMAGING APPARATUS USING THE IMAGING METHOD - Provided are an imaging method for use with a variable coded aperture filter and an imaging apparatus using the imaging method. The variable coded aperture filter includes a plurality of regulated patterns which may be properly selected, and an image obtained via a certain pattern of the variable coded aperture filter may be processed by a deconvolution method related to the certain pattern. The patterns in the variable coded aperture filter have different aperture degrees from each other so as to adjust an exposure amount, and accordingly, a subject which is extremely bright or extremely dark may be photographed and depth information and focus information may be obtained from the photographed image. Therefore, images of high image quality may be obtained in a large range of brightness variation. | 08-12-2010 |
20110026815 | METHOD AND APPARATUS FOR IMAGE PROCESSING - A method and apparatus for image processing are provided. The method may include generating a first restoration image by removing distortion components from an original image; determining a mixing ratio between the original image and the first restoration image based on distortion information of a region of interest in the original image; and generating a second restoration image by mixing the original image and the first restoration image according to the mixing ratio. | 02-03-2011 |
20110157387 | METHOD AND APPARATUS FOR GENERATING IMAGE DATA - A method for generating image data includes adjusting an angle formed by each of a plurality of lenses attached to the imaging device relative to a reference plane based on a photography mode, obtaining at least one first image data using the plurality of adjusted lenses, and generating second image data corresponding to the photography mode using the at least one first image data. | 06-30-2011 |
20110169980 | APPARATUS AND METHOD FOR OBTAINING HIGH DYNAMIC RANGE IMAGE - Provided is an apparatus and method for obtaining a high dynamic range (HDR) image. The apparatus includes an image sensor generating a first image by applying different exposure times for units of different predetermined regions, an image separating unit separating the first image into images, each of which is composed of regions having an identical exposure time, an image restoring unit restoring the separated images in such a way that each of the separated images has a resolution that is the same as a resolution of the first image, and an image synthesizing unit synthesizing the restored images into a second image. | 07-14-2011 |
20120033043 | METHOD AND APPARATUS FOR PROCESSING AN IMAGE - A method and apparatus for processing an image are provided. The method includes obtaining an image, generating 3-dimensional (3D) disparity information that represents a degree of stereoscopic effects of the image, and outputting the 3D disparity information. | 02-09-2012 |
20120063697 | IMAGE PROCESSING METHOD AND IMAGE PROCESSING APPARATUS - An image processing method and an image processing apparatus, the method including: generating a blurry image by using a maximum telephoto image among N (where N is a natural number equal to or greater than 2) live view images; generating an alpha map by using two or more images of the N live view images; and generating a soft focus image by combining the maximum telephoto image and the blurry image by using the alpha map. | 03-15-2012 |
20130120601 | PHOTOGRAPHING APPARATUS AND IMAGE PROCESSING APPARATUS USING CODED LIGHT, AND METHOD THEREOF - A photographing apparatus includes a light source to continuously emit a light, a photographing unit to photograph an object, a control unit to control radiation of the light by turning the light source on and off according to a light control code during a shutter time of the photographing unit, and an image processing unit to restore an image of the object using a frequency component value of the data captured at the photographing unit during the shutter time. Accordingly, efficient de-blurring is provided. | 05-16-2013 |
20140204183 | PHOTOGRAPHING DEVICE AND PHOTOGRAPHING METHOD FOR TAKING PICTURE BY USING A PLURALITY OF MICROLENSES - A photographing apparatus and method are provided. The photographing device includes: a main lens configured to transmit light beams reflected from a subject; a microlens array which includes a plurality of microlenses configured to filter and transmit the reflected light beams as different colors; an image sensor configured to sense the light beams that are transmitted by the plurality of microlenses; a data processor configured to collect pixels of positions corresponding to one another from a plurality of original images sensed by the image sensor to generate a plurality of sub images; a storage device configured to store the plurality of sub images; and a controller configured to detect pixels matching one another in the plurality of sub images stored in the storage device and to acquire color information and depth information of an image of the subject. Therefore, color information and depth information are restored without reducing resolution. | 07-24-2014 |
20150015773 | IMAGE GENERATING APPARATUS AND METHOD AND NON-TRANSITORY RECORDABLE MEDIUM - An image generating apparatus and method are provided. The image generating apparatus includes: a main lens; a microlens array configured to transmit light that is incident on and received from the main lens; an image sensor configured to sense the light received from the microlens array according to a direction; and a digital iris configured to selectively assign, according to the direction of the light, a weight to a light sensing value of the light that is sensed by the image sensor. | 01-15-2015 |
20150029378 | IMAGE PHOTOGRAPHING APPARATUS AND PHOTOGRAPHING METHOD THEREOF - An image photographing apparatus and a photographing method thereof are provided. The image photographing method includes displaying a photographing mode selection user interface (UI), in response to a plurality of photographing modes being selected through the photographing mode selection UI, calculating a final setting value based on a photographing setting value of the plurality of selected photographing modes, and in response to a photographing command being input, photographing an image according to the calculated final setting value. | 01-29-2015 |
20150029379 | IMAGE PHOTOGRAPHING APPARATUS AND METHOD THEREOF - An image photographing apparatus and method are provided. The image photographing method includes inputting images having different view points for a subject; displaying a first image among the images; in response to an input of a user command, changing the first image to a second image having a view point which is different from that of the first image, and displaying the second image; and in response to an input of a photographing command, acquiring the second image. | 01-29-2015 |
Patent application number | Description | Published |
20100019831 | CHARGE PUMP USING LOW VOLTAGE CAPACITORS AND DDI COMPRISING THE CHARGE PUMP - A charge pump includes a first end including a first section having a first capacitor and a first node, and a second end including a second section having a second capacitor. The first section charges the first capacitor with a first voltage during a first logic section of a clock signal, and converts an external voltage to a first middle voltage using the first voltage and a second voltage in a second logic section of the clock signal. The first middle voltage is a node voltage of a first node. The second section is connected to the first node, charges the second capacitor with a third voltage during the first logic section of the clock signal, and converts the external voltage to an internal voltage by using the third voltage and the first middle voltage in the second logic section of the clock signal. | 01-28-2010 |
20100171372 | Charge Pump Circuit and Voltage Converter Using the Same - An apparatus for generating a voltage required for a semiconductor device by using a voltage supplied from an external power supply is provided. A charge pump circuit includes a first circuit comprising a first capacitor and a first group of switching elements and controlling the first group of switching elements according to first and second switching signals to transfer a voltage charged in the first capacitor to a target terminal during a first period and to charge the first capacitor with a reference voltage applied to a first input terminal of the first capacitor during a second period, and a second circuit comprising a second capacitor, a third capacitor connected between an output terminal and a ground terminal and a second group of switching elements, and controlling the second group of switching elements according to the first and second switching signals to connect a first terminal of the second capacitor to the ground terminal during the first period, connect the first terminal of the second capacitor to a power supply voltage input terminal during the second period, connect a second terminal of the second capacitor to the power supply voltage input terminal when a voltage of the second terminal of the second capacitor is lower than a voltage of the target terminal during the first period, and connect the second terminal of the second capacitor to the output terminal during the second period. | 07-08-2010 |
20110050110 | APPARATUS AND METHOD OF DRIVING LED, SYSTEM FOR DRIVING LED USING THE SAME, AND LIQUID CRYSTAL DISPLAY APPARATUS INCLUDING THE SYSTEM - The light emitting diode (LED) driving apparatus includes a channel driving unit configured to detect a pulse width of a pulse width modulation (PWM) signal, and configured to output n dimming signals, where n is a natural number greater than or equal to 2. The channel driving unit is configured to sequentially shift a phase of the PWM signal by as much as the detected pulse width to generate the n dimming signals, and configured to output the n dimming signals to n channels. | 03-03-2011 |
20110109243 | CIRCUIT AND METHOD OF DRIVING LIGHT EMITTING DIODES, AND LIGHT EMITTING DIODE SYSTEM HAVING THE SAME - A light-emitting-diode driving circuit includes a current driving circuit configured to control current signals flowing through light-emitting-diode strings in response to a first signal that includes information of a light-emitting-diode current, a dynamic headroom controller configured to generate a third control signal that changes according to a change of the current signals flowing through the light-emitting-diode strings based on voltage signals of first terminals of each of the light-emitting-diode strings and a second control signal that includes the information of the light-emitting-diode current, and a power supply circuit configured to generate a light-emitting-diode driving voltage that changes in response to the third control signal, and provide the light-emitting-diode driving voltage to second terminals of each of the light-emitting-diode strings. | 05-12-2011 |
20110121755 | METHOD OF CONTROLLING SUPPLY VOLTAGE, MULTI-CHANNEL LIGHT-EMITTING DIODE DRIVING CIRCUIT AND MULTI-CHANNEL SYSTEM USING THE SAME - Provided is a multi-channel LED driving circuit which includes: an LED array of N LED channels (N is an integer equal to or greater than one), each channel having a plurality of LEDs connected in series, a supply voltage being input to one end of each channel, and the other end of each channel being connected to N current drivers, respectively; a dynamic headroom control block comparing N channel voltages of common nodes of the N LED channels and the N current drivers with combination voltages of a first reference voltage and a hysteresis voltage, and generating a second reference voltage in response to at least one dimming signal that defines a time period during which a predetermined current flows to the N current drivers through the N LED channels; and a direct current to direct current (DC-DC) converter generating the supply voltage corresponding to the second reference voltage. | 05-26-2011 |
20110204817 | LIGHT SOURCE DRIVER, METHOD OF DRIVING THE SAME AND DEVICES INCLUDING THE SAME - A light source driver including an adjusting circuit configured to adjust a voltage applied to each of a plurality of light source channels in response to a plurality of comparison signals and a comparison circuit configured to compare a minimum voltage among output voltages of the respective light source channels with a plurality of reference voltages and output the plurality of comparison signals. | 08-25-2011 |
20120127214 | LIGHT EMITTING DIODE DRIVING CIRCUIT, AND DISPLAY DEVICE HAVING THE SAME - A light-emitting-diode (LED) driving circuit and a display device include a current driving circuit, a level detector, a comparing circuit, a digital control circuit, and a power supply circuit. The level detector detects a minimum detection voltage signal having a minimum voltage level among voltage signals of first terminals of respective LED strings. The comparing circuit generates a first comparison output signal and a second comparison output signal based on a headroom-control reference voltage and the minimum detection voltage signal. The digital control circuit adjusts a duty ratio of a gate control signal in a digital mode based on the first comparison output signal, the second comparison output signal and a control clock signal. Therefore, the LED driving circuit has a small area in a semiconductor integrated circuit. | 05-24-2012 |
Patent application number | Description | Published |
20110316165 | Semiconductor Device and Method of Fabricating the Same - A semiconductor device includes first, second, and third conductive lines, each with a respective line portion formed over a substrate and extending in a first direction and with a respective branch portion extending from an end of the respective line portion in a direction different from the first direction. The branch portion of a middle conductive line is disposed between and shorter than the respective branch portions of the outer conductive lines such that contact pads may be formed integral with such branch portions of the conductive lines. | 12-29-2011 |
20120122297 | METHOD OF FABRICATING A NONVOLATILE MEMORY DEVICE - A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps. | 05-17-2012 |
20120202335 | METHODS OF FABRICATING NONVOLATILE MEMORY DEVICES INCLUDING VOIDS BETWEEN ACTIVE REGIONS AND RELATED DEVICES - A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed. | 08-09-2012 |
20140231953 | NAND FLASH MEMORY DEVICE - A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps. | 08-21-2014 |
Patent application number | Description | Published |
20110318930 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A first gas for plasma etch and a second gas for plasma deposition are introduced onto a semiconductor substrate, the semiconductor substrate including a mask pattern. A flow rate of the first and second gases is periodically changed within a range of flow rates during a process cycle, such that a plasma etch process and a plasma deposition process are performed together to form an opening in the semiconductor substrate. | 12-29-2011 |
20120064709 | METHOD OF FORMING SEMICONDUCTOR DEVICE - Provided is a method of forming a semiconductor device. The method may include forming a first insulating layer on a semiconductor substrate. A first polycrystalline silicon layer may be formed on the first insulating layer. A second insulating layer may be formed on the first polycrystalline silicon layer. A second polycrystalline silicon layer may be formed on the second insulating layer. A mask pattern may be formed on the second polycrystalline silicon layer. The second polycrystalline silicon layer may be patterned using the mask pattern as an etch mask to form a second polycrystalline silicon pattern exposing a portion of the second insulating to layer. A sidewall of the second polycrystalline silicon pattern may include a first amorphous region. The first amorphous region may be crystallized by a first recrystallization process. The exposed portion of the second insulating layer may be removed to form a second insulating pattern exposing a portion of the first polycrystalline silicon layer. The exposed portion of the first polycrystalline silicon layer may be removed to form a first polycrystalline silicon pattern exposing a portion of the first insulating layer. The exposed portion of the first insulating layer may be removed to form a first insulating pattern exposing a portion of the semiconductor substrate. | 03-15-2012 |
20120164809 | SEMICONDUCTOR DEVICES INCLUDING STRAINED SEMICONDUCTOR REGIONS, METHODS OF FABRICATING THE SAME, AND ELECTRONIC SYSTEMS INCLUDING THE DEVICES - A method of fabricating a semiconductor device includes forming a gate pattern on a substrate, forming an amorphous silicon (a-Si) region adjacent to the gate pattern by implanting a dopant containing a Group IV or VIII element into portions of the semiconductor substrate, forming gate spacers on sidewalls of the gate pattern, forming a first cavity by etching the a-Si region and the substrate using a first etching process, forming a second cavity by etching the substrate, such that the second cavity expands a profile of the first cavity in lateral and vertical directions, and forming a strained semiconductor region in the second cavity. | 06-28-2012 |
20130005110 | Method of fabricating semiconductor device - Provided is a method of manufacturing a semiconductor device having a capacitor. The method includes forming a composite layer, including sequentially stacking on a substrate alternating layers of first through nth sacrificial layers and first through nth supporting layers. A plurality of openings that penetrate the composite layer are formed. A lower electrode is formed in the plurality of openings. At least portions of the first through nth sacrificial layers are removed to define a support structure for the lower electrode extending between adjacent ones of the plurality of openings and the lower electrode formed therein, the support structure including the first through nth supporting layers and a gap region between adjacent ones of the first through nth supporting layers where the first through nth sacrificial layers have been removed. A dielectric layer is formed on the lower electrode and an upper electrode is formed on the dielectric layer. | 01-03-2013 |
20140038383 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING PHOTO KEY - A method of fabricating a semiconductor device includes providing a substrate that is divided into a first region on which a pattern layer is formed and a second region on which a photo key is formed. A silicon layer is formed on the first region and second region of the substrate. The silicon layer is patterned to form a hole exposing a photo key portion of the second region on which the photo key is formed. A buried oxide layer is formed to fill the hole exposing the photo key portion. The silicon layer is patterned by using the photo key formed under the buried oxide layer to form a silicon pattern layer. | 02-06-2014 |
20140065785 | SEMICONDUCTOR DEVICES INCLUDING A SUPPORT FOR AN ELECTRODE AND METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING A SUPPORT FOR AN ELECTRODE - Semiconductor devices are provided. Each of the semiconductor devices may include a plurality of electrodes. Moreover, each of the semiconductor devices may include a supporting pattern connected to sidewalls of the plurality of electrodes. Related methods of forming semiconductor devices are also provided. For example, the methods may include forming the supporting pattern before forming the plurality of electrodes. | 03-06-2014 |
20150079791 | METHOD OF FABRICATING SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device is provided. The method may include forming an interlayered insulating layer on a structure with a cell region and a peripheral circuit region, forming a first mask layer on the interlayered insulating layer, forming trenches in the first mask layer exposing the interlayered insulating layer by patterning the first mask layer on the peripheral circuit region, and forming key mask patterns in the trenches. An etch selectivity of the first mask patterns with respect to the interlayered insulating layer may be greater than that of the key mask patterns with respect to the interlayered insulating layer. | 03-19-2015 |
Patent application number | Description | Published |
20080204392 | DISPLAY DEVICE AND DRIVING METHOD THEREFOR - A display device, includes: a plurality of thin film transistors which comprise a gate electrode, a source electrode and a drain electrode; a plurality of pixel electrodes which are respectively connected to the drain electrode of the thin film transistors; a plurality of gate lines which are respectively disposed to the opposite edge parts of the pixel electrodes in a lengthwise direction of the pixel electrodes, and connected to the gate electrode of the thin film transistors; and a plurality of data lines which are respectively disposed to a single edge part of the pixel electrodes in a widthwise direction of the pixel electrodes, and connected to the source electrode of the thin film transistors, a pair of pixel electrodes adjoining each other to interpose the single data line therebetween, and a pair of thin film transistors which are respectively connected to the pair of pixel electrodes being connected with the same single data line. | 08-28-2008 |
20100171728 | Gate Drive Circuit and Display Apparatus Having the Same - A gate drive circuit includes a plurality of stages connected one after another to each other. Each of the stages includes a charging section, a driving section, a discharging section, a holding section and a holding control section. The driving section pulls up a high level of a first clock signal to output a gate signal. The discharging section discharges a voltage potential of a first node to a first off-voltage. The holding section holds a voltage potential of the first node to the first off-voltage. The holding control section receives the first clock signal and a second clock signal. The holding control section holds a voltage potential of the holding section to a second off-voltage through a second node in accordance with the second clock signal to prevent floating of the holding section. | 07-08-2010 |
20130293449 | DISPLAY DEVICE AND DRIVING METHOD THEREFOR - A display device, includes: a plurality of thin film transistors which comprise a gate electrode, a source electrode and a drain electrode; a plurality of pixel electrodes which are respectively connected to the drain electrode of the thin film transistors; a plurality of gate lines which are respectively disposed to the opposite edge parts of the pixel electrodes in a lengthwise direction of the pixel electrodes, and connected to the gate electrode of the thin film transistors; and a plurality of data lines which are respectively disposed to a single edge part of the pixel electrodes in a widthwise direction of the pixel electrodes, and connected to the source electrode of the thin film transistors, a pair of pixel electrodes adjoining each other to interpose the single data line therebetween, and a pair of thin film transistors which are respectively connected to the pair of pixel electrodes being connected with the same single data line. | 11-07-2013 |
20140043222 | GATE DRIVE CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME - A gate drive circuit includes a plurality of stages connected one after another to each other. Each of the stages includes a charging section, a driving section, a discharging section, a holding section and a holding control section. The driving section pulls up a high level of a first clock signal to output a gate signal. The discharging section discharges a voltage potential of a first node to a first off-voltage. The holding section holds a voltage potential of the first node to the first off-voltage. The holding control section receives the first clock signal and a second clock signal. The holding control section holds a voltage potential of the holding section to a second off-voltage through a second node in accordance with the second clock signal to prevent floating of the holding section. | 02-13-2014 |
Patent application number | Description | Published |
20100302268 | DISPLAY APPARATUS AND METHOD OF DRIVING THE SAME - A display apparatus includes a display panel which receives a light, a backlight which provides the light to the display panel in response to a driving voltage, and a backlight driver which applies the driving voltage to the backlight. The backlight is turned on and off during a communication period to transmit data to an external receiver using visible light communication during the communication period. The backlight driver controls a voltage level of the driving voltage according to a number of turn-on periods of the driving voltage during the communication period. | 12-02-2010 |
20110044695 | Visible Light Communication System - A visible light communication system includes a light source emitting a first light having information, an optical filter receiving the first light and an externally provided second light and filtering the first and second light according to wavelength bands of the first and second light to output a filtered light, a photoelectric device receiving the filtered light to generate an output signal, and a data output part receiving the output signal to output data. Accordingly, the external light not having information may be substantially prevented from being provided to the photoelectric device, thereby preventing noise from occurring on the output signal. In addition, no additional operation is required to filter the output signal from the photoelectric device. | 02-24-2011 |
20110216049 | VISIBLE LIGHT COMMUNICATION APPARATUS AND METHOD - Provided is a visible light communication apparatus. The visible light communication apparatus includes: a display unit that displays an image according to an image signal; a light source unit that operates as a backlight for the display unit, generates an optical signal by driving a light source based on a data signal, and outputs the generated optical signal to the display unit; a sensor unit that detects a region corresponding to a shape of a terminal which touches or approaches the display unit; and an image signal conversion unit that converts the image signal such that an image displayed in the region detected by the sensor unit is converted to a bright image having a gray level higher than a predetermined reference gray level. | 09-08-2011 |
20120038868 | TRANSPARENT DISPLAY DEVICE AND DISPLAYING METHOD USING THE SAME - A transparent display device includes a liquid crystal display (LCD) module and a transparent reflector. The LCD module includes an LCD panel having a liquid crystal layer, a light source providing light to the LCD panel, and a polarizing plate disposed between the light source and the LCD panel to polarize light from the light source. The transparent reflector and the LCD module are spaced apart. The transparent reflector displays the image by reflecting the image provided from the LCD panel. The transparency of the transparent reflector may be controlled, and the transparent reflector may have a curved shape. | 02-16-2012 |
20140184666 | DISPLAY APPARATUS AND METHOD OF DRIVING THE SAME - A display apparatus includes a display panel which receives a light, a backlight which provides the light to the display panel in response to a driving voltage, and a backlight driver which applies the driving voltage to the backlight. The backlight is turned on and off during a communication period to transmit data to an external receiver using visible light communication during the communication period. The backlight driver controls a voltage level of the driving voltage according to a number of turn-on periods of the driving voltage during the communication period. | 07-03-2014 |
Patent application number | Description | Published |
20120083989 | COMBUSTION DETECTING METHOD OF ENGINE - A combustion phase detection method is able to reduce exhaust gas and to improve combustion stability, to compensate injection and ignition delay time between combustion chambers and between cycles, and to detect a combustion phase in real time such that a heat generation rate and a heat release can be effectively calculated at an early state of the combustion by using a combustion pressure and a motoring pressure difference of an engine not affected by an offset value of the cylinder pressure. The combustion phase detection method of an engine may include detecting a combustion phase according to fuel injection timing by using a specific point of DHdP that is calculated by the following heat release equation: | 04-05-2012 |
20120083992 | COMBUSTION DETECTING METHOD OF ENGINE - A combustion phase detection method of an engine has the advantages of being able to reduce exhaust gas and to improve combustion stability, to compensate injection and ignition delay time between combustion chambers and between cycles, and to detect a combustion phase in real time such that a heat generation rate and heat release can be effectively calculated in an early state of combustion with a simple calculation method to control combustion of an engine, by using a combustion pressure and a motoring pressure difference of an engine not affected by an offset value of the cylinder pressure. For this, a combustion phase detection method may include detecting a combustion phase by using a specific point of DRdV as follows: | 04-05-2012 |
20130116910 | SYSTEM AND METHOD FOR JUDGING ABNORMAL CONDITION OF A COMBUSTION PRESSURE SENSOR - A system and method for judging an abnormal condition of a combustion pressure sensor, may include determining whether a driving condition of a vehicle, a fuel injection condition, and an intake air condition may be satisfied, deriving a relational equation from an amount of air measured in real time and a combustion pressure measured by the combustion pressure sensor, and monitoring a slope and a y-intercept of the relational equation when the driving condition, the fuel injection condition, and the intake air condition may be satisfied, determining whether the slope and the y-intercept may be in a predetermined normal range, accumulating the number of times the slope and the y-intercept may be beyond the predetermined normal range, and outputting a warning when the accumulated number reaches a number which may be predetermined as an abnormal condition number of the sensor. | 05-09-2013 |
20130131954 | METHOD OF PREDICTING NOx GENERATION AMOUNT - A method of predicting NOx generation amount may include calculating NO generation rate by using a combustion pressure of an engine and driving variables of the engine, obtaining NO generation period by using the combustion pressure of the engine, calculating NO generation amount based on the NO generation rate and the NO generation period, and predicting the NOx generation amount by obtaining NO | 05-23-2013 |
20130131967 | SYSTEM AND METHOD FOR CONTROLLING NOx - A system and a method for controlling NOx may include predicting NOx generation amount by using a virtual sensor; comparing the NOx prediction amount with a predetermined NOx target amount; and controlling the NOx generation amount so as for the NOx prediction amount to follow the NOx target amount. | 05-23-2013 |
20140116385 | DEVICE AND METHOD FOR DETERMINING AND CONTROLLING COMBUSTION MISFIRE OF VEHICLE ENGINE - A method of determining and controlling misfire in an engine. The method and device sense combustion pressure in a combustion chamber of an engine while the engine is operated; calculate MFB (a ratio of the amount of combustion heat at a specific point of time to the total amount of combustion heat), MFB50 (a point of time at which the amount of combustion heat is 50% of the total amount of combustion heat), MFB50 COV (Coefficient of Variation), IMEP (Indicated Mean Effective Pressure) and IMEP COV, from the combustion chamber; set a desired MFB50; and determine that there is misfire when a crank angle is delayed at 5 degrees or more, the MFB50 COV is 20% or more, or the IMEP COV is 20% or more, by comparing the calculated MFB50 with the desired MFB50; and then advance an injection time such that the MFB follows the desired MFB. | 05-01-2014 |
Patent application number | Description | Published |
20110025845 | Apparatus and method for measuring location and distance of object by using camera - The present invention provides an apparatus for measuring a location and a distance of an object by using a camera including: a camera module for photographing an external image; a parameter setup unit for setting internal and external parameters of the camera module; an image processor unit for receiving a captured image of an image photographed from the camera module, extracting a target object within the captured image, and extracting specific point coordinates of the extracted target object; and a location and distance calculating unit for calculating three-dimensional object location information in a two-dimensional camera coordinate system through the internal and external parameters of the camera module and coordinates of the target object, and calculating distance information from the location information of the object. | 02-03-2011 |
20130335041 | POWER CONVERSION APPARATUS AND METHOD OF CONTROLLING THE SAME - A power conversion apparatus including a current source converter configured to convert Alternate Current (AC) power to Direct Current (DC) power; a power controller configured to set a d-axis current command and a q-axis current command, which correspond to the AC power to the current source converter, by reflecting a difference between a measurement DC link voltage measured at an output terminal of the current source converter and a DC link voltage set by a DC link voltage command; and a phase angle controller configured to adjust a phase angle of the current source converter and transmit the adjusted phase angle to the current source converter, in response to the d-axis current command and the q-axis current command. | 12-19-2013 |
20140035495 | METHODS AND APPARATUSES FOR OBTAINING MAXIMUM MAGNETIC FLUX OF PERMANENT MAGNET SYNCHRONOUS MOTORS - A method of obtaining a maximum magnetic flux of a permanent magnet synchronous motor may comprise: receiving a first command voltage from a current controller to control current applied to the permanent magnet synchronous motor; receiving an on/off duty ratio of a control pulse signal to control an output voltage of an inverter that drives the permanent magnet synchronous motor, the on/off duty ratio being determined based on the first command voltage; generating a second command voltage corresponding to the output voltage to be output from the inverter based on the on/off duty ratio of the control pulse signal; obtaining a maximum command voltage error by comparing the first and second command voltages; and/or obtaining the maximum command magnetic flux of the permanent magnet synchronous motor according to a position of a rotor of the permanent magnet synchronous motor based on the maximum command voltage error. | 02-06-2014 |
20140070755 | METHODS AND APPARATUSES FOR CONTROLLING OUTPUT VOLTAGES OF INVERTERS DRIVING ELECTRIC MOTORS - A method of controlling an output voltage of an inverter driving an electric motor may include calculating a current total harmonic distortion (THD) of a current output to the electric motor; comparing the current THD with a reference current THD; determining a pulse width modulation (PWM) method to be changed from a first modulation method that reduces harmonic components of the current output to the electric motor to a second modulation method when the current THD is less than the reference current THD, the PWM method modulating a pulse width of a control pulse signal for controlling the output voltage of the inverter; and/or generating the control pulse signal based on the determined PWM method. | 03-13-2014 |
20140375234 | METHODS AND APPARATUSES FOR COMPENSATING FOR FRICTION TORQUES OF PERMANENT MAGNET SYNCHRONOUS MOTORS - A method of compensating for a friction torque of a permanent magnet synchronous motor may include: receiving input of a motor current and a rotor speed of the permanent magnet synchronous motor; estimating a motor torque based on the input motor current; acquiring a first friction torque corresponding to the input rotor speed and the estimated motor torque by using a lookup table of friction torques; compensating for a second friction torque of the permanent magnet synchronous motor based on the first friction torque, wherein the compensating is in response to a first torque command input to control driving of the permanent magnet synchronous motor and outputs a second torque command that compensates for the second friction torque; and/or controlling the driving of the permanent magnet synchronous motor based on the second torque command. | 12-25-2014 |
20140375236 | METHODS AND APPARATUSES FOR CONTROLLING TORQUES OF PERMANENT MAGNET SYNCHRONOUS MOTORS - A method of controlling torque of a permanent magnet synchronous motor (PMSM) by using a speed-torque lookup table may include: receiving a current direct-current (DC) link voltage of an inverter configured to drive the PMSM and a speed of a rotor of the PMSM; calculating a change ratio of a DC link voltage based on the current DC link voltage and a DC link voltage at a time when the speed-torque lookup table is generated; calculating a normalized speed of the rotor according to a change in the DC link voltage by using the speed of the rotor and the change ratio of the DC link voltage; and/or transferring the normalized speed of the rotor as an input to the speed-torque lookup table. | 12-25-2014 |
Patent application number | Description | Published |
20110241184 | INTEGRATED CIRCUIT DEVICES HAVING SELECTIVELY STRENGTHENED COMPOSITE INTERLAYER INSULATION LAYERS AND METHODS OF FABRICATING THE SAME - An integrated circuit device includes a plurality of stacked circuit layers, at least one of the plurality of circuit layers including a composite interlayer insulation layer including laterally adjacent first and second insulating material regions having different mechanical strengths and dielectric properties and a plurality of circuit components disposed in the composite interlayer insulation layer. The first insulating material region may have a lower dielectric constant and a lower mechanical strength than the second insulating material region such that, for example, the first insulating material region may be positioned near signal lines or other circuit features to reduce capacitance while using the second insulating material region near a location that is susceptible to localized mechanical stress, such as a fuse location, an external connection bonding location or a scribe line location. | 10-06-2011 |
20110263117 | APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A method of manufacturing a semiconductor device and an apparatus for manufacturing a semiconductor device in which moisture is removed from a porous low-dielectric layer after a chemical mechanical polishing (CMP) process include formation of a porous low-dielectric layer on a substrate. A metal interconnection is formed on the substrate having the porous low-dielectric layer. The metal interconnection forms a planar surface with the porous low-dielectric layer to fill the openings. Ultraviolet (UV) light is irradiated to the porous low-dielectric layer to remove absorbed moisture from the porous low-dielectric layer. A capping layer is formed on the substrate having the porous low-dielectric layer and the metal interconnection. The capping layer is formed in-situ to prevent additional absorption of moisture. | 10-27-2011 |
20120083117 | Method Of Forming Hardened Porous Dielectric Layer And Method Of Fabricating Semiconductor Device Having Hardened Porous Dielectric Layer - Example embodiments relate to a method of forming a hardened porous dielectric layer. The method may include forming a dielectric layer containing porogens on a substrate, transforming the dielectric layer into a porous dielectric layer using a first UV curing process to remove the porogens from the dielectric layer, and transforming the porous dielectric layer into a crosslinked porous dielectric layer using a second UV curing process to generate crosslinks in the porous dielectric layer. | 04-05-2012 |
20120094437 | METHOD OF FORMING THROUGH SILICON VIA OF SEMICONDUCTOR DEVICE USING LOW-K DIELECTRIC MATERIAL - A method of forming through silicon vias (TSVs) includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate. | 04-19-2012 |
20120112361 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device is provided. The semiconductor device includes a substrate having a via hole comprised of a first region having a first width and a second region having a second width greater than the first width, wherein at least a portion of the substrate is exposed in the via hole, and an insulating region having an air gap spaced apart from and surrounding the first region of the via hole. | 05-10-2012 |
20120153500 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A semiconductor device comprises a top surface having a first contact, a bottom surface having a second contact, a via hole penetrating a substrate, an insulation layer structure on a sidewall of the via hole, the insulation layer structure having an air gap therein, a through electrode having an upper surface and a lower surface on the insulation layer structure, the through electrode filling the via hole and the lower surface being the second contact, and a metal wiring electrically connected to the upper surface of the through electrode and electrically connected to the first contact. | 06-21-2012 |
20120178253 | Method of Manufacturing a Semiconductor Device Having a Porous, Low-K Dielectric Layer - The inventive concept provides porous, low-k dielectric materials and methods of manufacturing and using the same. In some embodiments, porous, low-k dielectric materials are manufactured by forming a porogen-containing dielectric layer on a substrate and then removing at least a portion of said porogen from the layer. | 07-12-2012 |
20130228936 | METHOD OF FORMING THROUGH SILICON VIA OF SEMICONDUCTOR DEVICE USING LOW-K DIELECTRIC MATERIAL - A method of forming through silicon vias (TSVs) uses a low-k dielectric material as a via insulating layer to thereby improve step coverage and minimize resistive capacitive (RC) delay. To this end, the method includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate. | 09-05-2013 |
20140061926 | SEMICONDUCTOR DEVICES INCLUDING SUPPORTING PATTERNS IN GAP REGIONS BETWEEN CONDUCTIVE PATTERNS AND METHODS OF FABRICATING THE SAME - An integrated circuit device includes spaced apart conductive patterns on a substrate surface, and a supporting pattern on the substrate surface between adjacent ones of the conductive patterns and separated therefrom by respective gap regions. The adjacent ones of the conductive patterns extend away from the substrate surface beyond a surface of the supporting pattern therebetween. A capping layer is provided on respective surfaces of the conductive patterns and the surface of the supporting pattern. Related fabrication methods are also discussed. | 03-06-2014 |
20140312456 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device can include wiring lines on a substrate and an interlayer insulating structure, between ones of the wiring lines. The wiring lines can include a pore-containing layer that includes a plurality of pores extending away from a surface of the substrate, wherein ones of the pores have respective volumes that increase with a distance from the substrate until reaching an air gap layer above the pore-containing layer and beneath uppermost surfaces of the wiring lines. | 10-23-2014 |
20140370704 | METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING LOW-K DIELECTRIC LAYER - Methods of forming a dielectric layer are provided. The methods may include introducing oxygen radicals and organic silicon precursors into a chamber to form a preliminary dielectric layer on a substrate. Each of the organic silicon precursors may include a carbon bridge and a porogen such that the preliminary dielectric layer may include carbon bridges and porogens. The methods may also include removing at least some of the porogens from the preliminary dielectric layer to form a porous dielectric layer including the carbon bridges. | 12-18-2014 |
Patent application number | Description | Published |
20090067143 | ELECTRONIC DEVICE HAVING STACK-TYPE SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - An electronic device includes a lower electronic part including a lower substrate, a lower chip structure disposed on the lower substrate, and a lower molding layer covering the lower chip structure and having a recessed region in an upper surface of the lower molding layer, and an upper electronic part including an upper substrate disposed on the lower electronic part, and an upper chip structure projecting from the upper substrate, wherein the recessed region of the lower molding layer receives the upper chip structure. | 03-12-2009 |
20100038765 | Semiconductor package and method for manufacturing the same - Provided is a semiconductor package and a method for fabricating the semiconductor package. The semiconductor package may include a first package having a first semiconductor chip mounted on a first substrate and a second package having a second semiconductor chip mounted on a second substrate, the second substrate being bent to cover a side of the first package to contact the first substrate such that the first and second packages are connected electrically. | 02-18-2010 |
20120021600 | METHOD OF FABRICATING FILM CIRCUIT SUBSTRATE AND METHOD OF FABRICATING CHIP PACKAGE INCLUDING THE SAME - A method of fabricating a film circuit substrate and a method of fabricating a chip package. The method of fabricating a film circuit substrate can include providing a base film including a chip packaging area to package a chip and a separation area to separate the two chip packaging areas from each other, the separation area including a cut area and an uncut area; forming a reserve interconnection pattern having a first height on the base film; and forming an interconnection pattern having a second height that is lower than the first height on the out area by selectively etching the reserve interconnection pattern of the cut area. | 01-26-2012 |
20120199964 | ELECTRONIC DEVICE HAVING STACK-TYPE SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - An electronic device includes a lower electronic part including a lower substrate, a lower chip structure disposed on the lower substrate, and a lower molding layer covering the lower chip structure and having a recessed region in an upper surface of the lower molding layer, and an upper electronic part including an upper substrate disposed on the lower electronic part, and an upper chip structure projecting from the upper substrate, wherein the recessed region of the lower molding layer receives the upper chip structure. | 08-09-2012 |
20130005088 | METHODS OF FORMING SEMICONDUCTOR MODULES AND SEMICONDUCTOR MODULES FORMED BY THE SAME - Provided are methods of forming semiconductor modules. The method includes forming a high polymer material layer having an adhesive property on a support substrate, adhering a semiconductor chip to the support substrate using the high polymer material layer, bonding the semiconductor chip adhered to the support substrate to a flexible panel, and removing the support substrate. | 01-03-2013 |
20130148312 | TAPE WIRING SUBSTRATE AND CHIP-ON-FILM PACKAGE INCLUDING THE SAME - A tape wiring substrate includes a base film having at least one recess in a first surface of the base film and a chip-mounting region on which a semiconductor chip is included on a second surface of the base film. A wiring pattern is formed on the second surface of the base film and is extended to an edge of the chip-mounting region. A protection film covers the wiring pattern. | 06-13-2013 |
20130175528 | CHIP ON FILM PACKAGE INCLUDING TEST PADS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME - Provided are a chip on film (COF) package and semiconductor having the same. The COF package can include a flexible film having first and second surfaces opposite to and facing each other and including a conductive via penetrating from the first surface to the second surface, first and second conductive patterns respectively is on the first surface and the second surface and electrically connected to each other through the conductive via, an integrated circuit (IC) chip is on the first surface and electrically connected to the first conductive pattern, a test pad overlaps the conductive via and is electrically connected to at least one of the first conductive pattern and the second conductive pattern, and an external connection pattern is on the second surface spaced apart from the conductive via and electrically connected to the second conductive pattern. | 07-11-2013 |
20130186680 | Tape Film Packages and Methods of Fabricating the Same - A tape film package is provided including an insulating pattern; a via contact in a via hole in the insulating pattern; first interconnection patterns extending from the via contact to a cutting surface of the insulating pattern; and second interconnection patterns connected to the via contact below the insulating pattern. The second interconnection patterns are parallel to the first interconnection patterns and spaced apart from the cutting surface of the insulating pattern. | 07-25-2013 |
20130240917 | SEMICONDUCTOR PACKAGE HAVING A CONDUCTIVE LAYER FOR ELECTROSTATIC DISCHARGE AND DISPLAY DEVICE INCLUDING THE SAME - A semiconductor package is provided. The semiconductor package may include a base film having a first surface and a second surface opposite the first surface, an interconnection pattern on the first surface of the base film, and a ground layer on the second surface of the base film. The semiconductor package may further include a semiconductor chip on the first surface of the base film within the first region and a via contact plug in the second region that penetrates the base film and is configured to electrically connect the interconnection pattern with the ground layer when electrostatic discharge occurs through the via contact plug. | 09-19-2013 |
20130293816 | CHIP-ON-FILM PACKAGE AND DEVICE ASSEMBLY INCLUDING THE SAME - Chip-on-film packages and device assemblies including the same may be provided. The device assembly includes a film package including a semiconductor chip, a panel substrate connected to one end of the film package, a display panel disposed on the panel substrate, and a controlling part connected to another end of the film package. The film package includes a film substrate, a first wire disposed on a top surface of the film substrate, and a second wire disposed on a bottom surface of the film substrate. | 11-07-2013 |
20130344627 | METHOD OF FABRICATING WAFER LEVEL PACKAGE - A method of fabricating a wafer level package includes preparing a wafer including a plurality of first semiconductor chips, mounting a plurality of second semiconductor chips on the wafer, disposing the wafer on a lower mold and disposing an upper mold so as to surround edges of a top surface of the wafer, dispensing a molding member on the wafer, and pressurizing the molding member by using a plunger so as to fabricate a wafer level package in which a top surface of each of the plurality of second semiconductor chips is exposed. | 12-26-2013 |
20140239478 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first semiconductor chip at least partially overlapping a second semiconductor chip. The first semiconductor chip is coupled to a substrate and has a first width, and the second semiconductor chip has a second width. The device also includes a heat sink coupled to the second semiconductor chip and having a third width different from at least one of the first width or the second width. A package molding section at least partially overlaps a first area of the heat sink and does not overlap a second area of the heat sink which includes a top surface of the heat sink. | 08-28-2014 |
20140252605 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor package and a method of fabricating the same. The method of fabricating the semiconductor package includes arranging each of a plurality of second semiconductor chips and each of a plurality of first semiconductor chips to be electrically connected to each other on a first wafer which includes the plurality of first semiconductor chips, with a first width of each of the first semiconductor chips is greater than a second width of each of the second semiconductor chips, forming a first molding layer surrounding the second semiconductor chips on the first wafer, forming a chip package including the first and second semiconductor chips by sawing the first wafer in units of the first semiconductor chips, arranging the chip package on a package substrate to electrically connect the second semiconductor chips to the package substrate, and forming a second molding layer surrounding the chip package on the package substrate. | 09-11-2014 |
20140273350 | METHOD OF FABRICATING SEMICONDUCTOR MULTI-CHIP STACK PACKAGES - Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures. | 09-18-2014 |
20140299980 | SEMICONDUCTOR PACKAGES INCLUDING A HEAT SPREADER AND METHODS OF FORMING THE SAME - Semiconductor packages including a heat spreader and methods of forming the same are provided. The semiconductor packages may include a first semiconductor chip, a second semiconductor chip, and a heat spreader stacked sequentially. The semiconductor packages may also include a thermal interface material (TIM) layer surrounding the second semiconductor chip and directly contacting a sidewall of the second semiconductor chip. An upper surface of the TIM layer may directly contact a lower surface of the heat spreader, and a sidewall of the TIM layer may be substantially coplanar with a sidewall of the heat spreader. In some embodiments, a sidewall of the first semiconductor chip may be substantially coplanar with the sidewall of the TIM layer. | 10-09-2014 |
20140301055 | PRINTED CIRCUIT BOARD INCLUDING THROUGH REGION AND SEMICONDUCTOR PACKAGE FORMED BY USING THE SAME - Provided is a printed circuit board (PCB). The PCB includes a board body that includes a first surface and a second surface opposite the first surface, a semiconductor chip mounting region that is disposed on the first surface of the board body, and includes a plurality of semiconductor chip mounting parts on which a semiconductor chip may be mounted, a through region that is disposed at a peripheral portion of the semiconductor chip mounting region, and includes a plurality of through holes passing through the board body, and an external terminal forming region that is disposed on the second surface of the board body, wherein a plurality of external terminal forming parts are disposed at the external terminal forming region in correspondence with the respective semiconductor chip mounting parts. | 10-09-2014 |
Patent application number | Description | Published |
20090127609 | Method of fabricating recess channel transistor having locally thick dielectrics and related devices - Provided are a method of fabricating a recess channel transistor and a related semiconductor device. The method may include forming a first gate trench on a substrate, forming a dielectric spacer on a sidewall of the first gate trench, forming a second gate trench on the substrate under the first gate trench, and forming a gate electrode to fill the trenches. The dielectric spacer may remain between the gate electrode and the substrate. | 05-21-2009 |
20120091532 | Semiconductor Devices Including Buried-Channel-Arrray Transistors - Provided is a semiconductor device in which a short margin between a storage contact plug and a bit line contact plug may be increased. The device includes a substrate including isolation regions and active regions defined by the isolation regions, gates disposed in the substrate and configured to intersect the active regions and define source regions and drain regions in the active regions, an interlayer insulating layer disposed on the substrate, bit line contact plugs configured to penetrate the interlayer insulating layer and contact the drain regions, and first bit line structures and second bit line structures disposed on the interlayer insulating layer. The first bit line structures include first bit line conductive patterns and first bit line spacers covering sidewalls of the first bit line conductive patterns. The second bit line structures include second bit line conductive patterns configured to contact the bit line contact plugs to be substantially parallel to the first bit line conductive patterns and first bit line spacers covering sidewalls of the second bit line conductive patterns and sidewalls of the bit line contact plugs. | 04-19-2012 |
20140264727 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate with an active pattern, the active pattern having a first extension portion extending in a first direction substantially parallel to a top surface of the substrate, a second extension portion extending from a first end of the first extension portion in a third direction oriented obliquely to the first direction, a third extension portion extending from a second end of the first extension portion in a direction opposed to the third direction, a first projection portion protruding from the second extension portion in a direction opposed to the first direction, the first projection portion being spaced apart from the first extension portion, and a second projection portion protruding from the third extension portion in the first direction, the second projection portion being spaced apart from the first extension portion. | 09-18-2014 |
Patent application number | Description | Published |
20110042205 | CAPACITIVE DEIONIZATION DEVICE - A capacitive deionization device includes; at least one flow path configured for influent water flow, at least one pair of electrodes, at least one charge barrier disposed between the at least one flow path and a corresponding electrode of the at least one pair of electrodes, and at least one electrolyte solution disposed between the at least one electrode of the at least one pair of electrodes and a corresponding charge barrier of the at least one charge barrier, wherein the at least one electrolyte solution is different in at least one of ionic concentration and ionic species from the influent water. | 02-24-2011 |
20120181228 | Polyacrylonitrile Copolymer, Method For Manufacturing Membrane Including The Same, Membrane Including The Same, And Water Treatment Module Using The Membrane - Example embodiments relate to a polyacrylonitrile-based copolymer, a method for manufacturing a membrane including the same, a membrane including the same, and a water treatment module using the same. A membrane according to an example embodiment may include a polyacrylonitrile-based copolymer including a repeating unit represented by Chemical Formula 1, a repeating unit represented by Chemical Formula 2, and/or a repeating unit represented by Chemical Formula 3. The definitions of the above Chemical Formulae 1, 2, and/or 3 may be the same as in the detailed description. Accordingly, the membrane may allow the attainment of a relatively high water permeation amount and a water treatment module having a relatively high energy efficiency. | 07-19-2012 |
20120211423 | DRAW SOLUTE FOR FORWARD OSMOSIS, DRAW SOLUTION INCLUDING THE SAME, FORWARD OSMOSIS WATER TREATMENT DEVICE USING THE SAME, AND FORWARD OSMOSIS METHOD FOR WATER TREATMENT USING THE SAME - A draw solute for forward osmosis may include a copolymer including a first structural unit where a temperature-sensitive side chain is graft polymerized, and a second structural unit including a hydrophilic functional group. The temperature-sensitive side chain may include a structural unit for a side chain including a temperature-sensitive moiety. | 08-23-2012 |
20120261321 | SEPARATION MEMBRANE, METHOD FOR MANUFACTURING THE SAME, AND FORWARD OSMOSIS DEVICE INCLUDING THE SAME - Example embodiments relate to a separation membrane including at least one polymer including a structural unit represented by the following Chemical Formula 1, | 10-18-2012 |
20120267304 | Membrane, Method For Manufacturing The Same, And Composite Membrane Including The Same - Example embodiments relate to a membrane, a method of manufacturing the same, and a composite membrane including the same. The membrane may include a polyacrylonitrile-based copolymer that includes a hydrophobic side chain and/or a hydrophobic repeating unit. The membrane may include a skin layer and a porous layer. A thickness ratio of the skin layer relative to the porous layer may be about 0.01 or less. The skin layer may have a thickness of about 1 μm or less. The membrane may have a relatively high water flux. When using the membrane, a water treatment module having higher energy efficiency may be achieved. | 10-25-2012 |
20120298574 | Organic/Inorganic Hybrid Compound For Fouling Resistance, Membrane Including The Same For Fouling Resistance, And Method Of Preparing Membrane For Fouling Resistance - An organic/inorganic composite compound for fouling resistance may include a core and at least an arm. The core may be formed of a polyhedron of polyhedral oligomeric silsesquioxane. At least one arm may be connected to a Si atom of the polyhedral oligomeric silsesquioxane. The arm may include a vinyl-based first structural unit including at least one ethylene oxide group at the side chain, and a hydrophobic vinyl-based second structural unit. | 11-29-2012 |
20130020243 | SEPARATION MEMBRANE, METHOD FOR MANUFACTURING THE SAME, AND WATER TREATMENT DEVICE INCLUDING THE SAME - A separation membrane may include a support layer and a polymer matrix layer. The support layer may include a polymer including a structural unit represented by Chemical Formula 1, and the polymer matrix layer is a semi-permeable membrane and has a higher rejection rate against a target material to be separated compared to the support layer. Chemical Formula 1 may be as described in the detailed description. | 01-24-2013 |
20130134081 | HYBRID POROUS STRUCTURE, METHOD OF PREPARING HYBRID POROUS STRUCTURE, SEPARATION MEMBRANE INCLUDING HYBRID POROUS STRUCTURE, AND WATER TREATMENT DEVICE INCLUDING MEMBRANE - A hybrid porous structure may include a base template and an ionic polymer coating layer within the base template. The structural framework of the base template itself is non-porous. The base template fills the gaps among a plurality of imaginary spherical bodies stacked in three-dimensions as an imaginary stack. The ionic polymer coating layer is laminated on an inner surface of the base template inside the imaginary spherical bodies. The imaginary spherical bodies may have a pore in the center which is not occupied by the ionic polymer coating layer. The hybrid porous structure may include a plurality of necks, which are openings formed in a contact part where adjacent imaginary spherical bodies contact each other. The necks may be interconnected to the pores located in the center part of the imaginary spherical bodies. | 05-30-2013 |
20130153489 | SEMI-PERMEABLE FILM AND SEPARATION MEMBRANE INCLUDING NANOPOROUS MATERIAL, AND METHOD OF MANUFACTURING THE SAME - Example embodiments herein relate to a semi-permeable film including a nanoporous material and a polymer matrix. The nanoporous material includes a nanoporous core and a coating layer that is disposed on a surface of the nanoporous core. The coating layer may include a particle selected from a metal hydroxide particle, a metal oxide particle, and a combination thereof. A separation membrane may include the semi-permeable film. Example embodiments also relate to a method of manufacturing the semi-permeable film and the separation membrane. | 06-20-2013 |
20130240444 | THERMOSENSITIVE COPOLYMERS, FORWARD OSMOSIS WATER TREATMENT DEVICES INCLUDING THE SAME, AND METHODS OF PRODUCING AND USING THE SAME - A thermosensitive copolymer may include a first repeating unit having a temperature-sensitive oligomer and a second repeating unit having an ionic moiety and a counter ion to the ionic moiety. The temperature-sensitive oligomer may be an oligomer including a repeating unit derived from a unsaturated monomer with a moiety represented by Chemical Formula 1 or Chemical Formula 2, or an oligomer including a repeating unit derived from a heterocyclic compound having C, N, O, and a C═N bond in its ring. | 09-19-2013 |
20130313182 | SEPARATION MEMBRANE AND WATER TREATMENT DEVICE INCLUDING THE SAME - A forward osmosis water treatment device may use a separation membrane including a polymer layer introduced with a functional group having an affinity for an osmosis draw solute present in an osmosis draw solution. | 11-28-2013 |
20130327701 | SEPARATION MEMBRANE AND WATER TREATMENT DEVICE INCLUDING A SEPARATION MEMBRANE - A separation membrane including a polymer having a structural unit represented by the following Chemical Formula 1, and a water treatment device including a separation membrane, are useful for desalination. | 12-12-2013 |
20140048477 | HYBRID POROUS STRUCTURED MATERIAL, MEMBRANE INCLUDING THE SAME, AND METHOD OF PREPARING HYBRID POROUS STRUCTURED MATERIAL - A hybrid porous structured material may include a matrix including a plurality of first pores interconnected in three dimensions, and a porous material including second pores and filling wholly or partially each of the plurality of the first pores. | 02-20-2014 |
20140158612 | COMPOSITE MEMBRANE, METHOD OF MANUFACTURING THE SAME, SEPARATION MEMBRANE INCLUDING THE COMPOSITE MEMBRANE, AND WATER TREATMENT DEVICE USING THE SEPARATION MEMBRANE - An organic/inorganic composite membrane may include hydrophilic inorganic particles dispersed in an organic polymer matrix having finger-like pores. The hydrophilic inorganic particles may be present at a higher concentration near one surface of the membrane having a higher density than the other surface of the membrane having a lower density. | 06-12-2014 |
20140217026 | DRAW SOLUTE FOR FORWARD OSMOSIS, FORWARD OSMOSIS WATER TREATMENT DEVICE, AND FORWARD OSMOSIS METHOD FOR WATER TREATMENT - A method of manufacturing polymer hydrogel for an osmosis solute may include cross-linking polymerizing a zwitterionic monomer (including an anionic group and a cationic group) and a temperature-sensitive monomer. Example embodiments also relate to a draw solute for forward osmosis including polymer hydrogel manufactured according to the method, and a forward osmosis water treatment device and method using the forward osmosis draw solute. | 08-07-2014 |
20140326657 | SEMI-PERMEABLE FILM, MEMBRANE INCLUDING THE SEMI-PERMEABLE FILM, AND METHOD OF MANUFACTURING THE SEMI-PERMEABLE FILM - The present disclosure pertains to a semi-permeable film including a polyhedron oligomer silsesquioxane derivative dispersed in a polymer matrix, a method of manufacturing the same, a separation membrane including the semi-permeable film, and a water treatment device including the separation membrane. | 11-06-2014 |
20140353240 | HYBRID POROUS STRUCTURED MATERIAL, METHOD OF PREPARING HYBRID POROUS STRUCTURED MATERIAL, MEMBRANE INCLUDING HYBRID POROUS STRUCTURED MATERIAL, AND WATER TREATMENT DEVICE INCLUDING MEMBRANE INCLUDING HYBRID POROUS STRUCTURED MATERIAL - A hybrid porous structured material may include a porous region and a non-porous region. The porous region may include an imaginary stacked structure, wherein a plurality of imaginary spherical bodies/cavities are stacked so as to contact each other in three-dimensional directions. The non-porous region fills the gaps between the imaginary spherical bodies. A spherical colloid particle is present in each of the plurality of imaginary spherical bodies in the porous region. A separation membrane may include the hybrid porous structured material. A water treatment device may include the membrane. | 12-04-2014 |
20150060361 | DRAW SOLUTES INCLUDING AMINO ACID IONIC OLIGOMERS - A draw solute including an oligomer having an amino acid repeating unit with an ionic moiety and a counter ion thereof, and a forward osmosis water treatment device and method using the same are provided. | 03-05-2015 |
Patent application number | Description | Published |
20090072798 | APPARATUS AND METHOD FOR APPLYING HIGH VOLTAGE WITH HIGH FREQUENCY - An apparatus and a method for applying high voltage with high frequency. The apparatus includes a power generator for generating electric power with predetermined frequency, a voltage transformer receiving the electric power generated by the power generator, amplifying voltage of the electric power received, and applying the amplified voltage to a load, and an impedance matcher connected between the power generator and the voltage transformer to match impedances of the power generator and the voltage transformer to thereby transmit the electric power to the voltage transformer. High voltage with high frequency is obtained by transmitting the electric power generated from the power generator to the load without reflecting loss while conducting an impedance matching, and amplifying the voltage applied to the load using the coupled inductor and LC resonance. | 03-19-2009 |
20090073623 | APPARATUS AND METHOD FOR SAFETY POWER CONTROL - An apparatus for safety power control is provided. The apparatus comprises first and second electrodes oppositely spaced a predetermined distance to each other; a first voltage generator applying first voltage between the first and second electrodes, a second voltage generator applying, between the first and second electrodes, second voltage for detecting an object put between the first and second electrodes, a voltage meter measuring voltage between the first and second electrodes, and a controller detecting the variance in voltage measured by the voltage meter, and if the measured variance is no less than a predetermined threshold value, cutting off the first voltage, whereby detecting voltage having frequency different from high voltage is applied between electrodes to which the high voltage is applied, the variance in detecting voltage between the electrodes according to ingress of a human body or an object is measured, and if voltage variance above a predetermined value is measured, the high voltage is cut off, so that it is prevented for the human body from being damaged by the high voltage in the apparatus, and that the electrodes for applying high voltage is used as it is, thereby controlling power without installing an additional sensor. | 03-19-2009 |